JP3179215B2 - Display control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control circuit for a television receiver, and more particularly to a display control circuit for a small television receiver used outdoors or in a vehicle.

[0002]

2. Description of the Related Art First, a conventional driving method of a display device using a liquid crystal display device (hereinafter, referred to as "LCD") in which thin film transistors (hereinafter, referred to as "TFT") are arranged in a matrix on a display screen will be described. Is TFT-LC
FIG. 3 is a block circuit diagram of a D panel 5 and its driving circuits 3, 4 and a control circuit 35. FIG. 4 shows a TFT-LCD panel 5
FIG. 2 is a circuit diagram of the driving circuits 3 and 4. The following video signals are based on the NTSC system.

In FIG. 3, a power supply voltage VCC is supplied to a terminal 30 of the countdown circuit 1, a terminal 27 of the control circuit 2, a terminal 13 of the signal electrode driving circuit 3, and a terminal 1 of the scanning electrode driving circuit.
7 and so on. The control circuit 2 has a terminal 7
On the basis of the composite synchronization signal S1 directly input through
A vertical synchronization pulse S4, vertical shift pulses P1 and P2 for synchronizing vertical pixels, and a line switch signal S5 are generated, and the terminals 11 and 9 of the signal electrode driving circuit 3 are connected via terminals 20, 18, 19 and 21, respectively. , 10 and 12, and also generates a horizontal synchronizing pulse S6 and horizontal shift pulses P3 and P4 for synchronizing horizontal pixels. , 14, and 15. The signal electrode drive circuit 3 outputs a video signal S input from the outside via the terminal 6.
3 is taken into the terminal 8.

Next, the operation of the signal electrode drive circuit 3 and the scan electrode drive circuit 4 for driving the TFT-LCD panel 5, which are well known, will be briefly described with reference to FIG.
FIG. 6 shows signal waveforms of the vertical shift pulses P1, P2, the vertical synchronization pulse S4, the video signal S3, the line switch signal S5, the horizontal shift pulses P3, P4, and the horizontal synchronization pulse S6 shown in FIG. In the circuit shown in FIG.
-Each transistor TFTij that operates as an electrode selection switch of each liquid crystal display element LCDij on the LCD panel 5,
The fine field effect transistors are provided so as to be arranged in a matrix in the form of a TFT. The video signal S3 input to the terminal 8 is output simultaneously and in parallel to each source s of the i-th transistor TFTi from the left that controls the line memory 32. The vertical synchronizing pulse S4 input to the terminal 11 and the vertical shift pulses P1 and P2 input to the terminals 9 and 10 cause the stages of the shift register 31 in the signal electrode driving circuit 3 to sequentially go from left to right. When the transistor TFTi is turned on for a certain pulse duration, a voltage is applied to the gate g of the transistor TFTi during that period, and the transistor TFTi turns on one after another for a certain pulse duration. The terminals 13, 17
Is supplied with a power supply voltage VCC.

As a result, in the signal electrode drive circuit 3,
The temporally continuous video signal S4 is 1 in the horizontal direction of one scanning line.
The voltage is divided into pixels and stored in the capacitors Ci on the line memory 32 and connected to the drain d of each transistor TFTi as a voltage applied to one pixel. The image signal for one scanning line is applied to all the capacitors Ci.
These signals are stored in a time-division manner in the transistor T which operates as a switch of the line memory 32.
The source s and the drain d of the FTLi are connected to the terminal g at the gate g.
Is turned on by the line switch signal S5 applied through the switch, and each capacitor Ci and each signal electrode Li are turned on.

On the other hand, the scanning electrode driving transistor TFTj connected to the scanning electrode is supplied from the horizontal synchronizing pulse S6 inputted from the terminal 16 and the terminals 14 and 15 by the horizontal shift register 33 in the scanning electrode driving circuit 4. In synchronization with the horizontal shift pulses P3 and P4, the pixels are driven so as to be turned on one by one sequentially from the top to the bottom of the first row for one scanning line period. As a result, the transistor TF connected to the j-th scan electrode is synchronized with the horizontal synchronization pulse S6.
When Tj is turned on, all the sources s and drains d of the transistors TFT1j, TFT2j, TFT3j,..., TFTij,. State, and the voltage stored in each capacitor Ci that is electrically connected to each of the signal electrodes L1, L2, L3, ..., Li, ... is applied to each capacitance Cij of the pixel electrode in the ith column and jth row. Moved. The capacitance Cij is the sum of the capacitances of the liquid crystal display element LCDij and the signal storage capacitance C′ij connected in parallel, and the transmittance of the liquid crystal display element LCDij is controlled by the voltage stored therein.

When the above operation is performed from top to bottom in order from the first row of the TFT-LCD panel 5, image signals are transferred to all the liquid crystal display elements LCDij. Further, by repeating this operation, a moving image can be obtained based on the intercepted video signal.

However, as shown in FIG. 3, in the control circuit 2, the unstable composite synchronizing signal S
When 1 is used as it is, the vertical synchronizing signal (not shown) generated from the composite synchronizing signal S1 also becomes unstable, and therefore, the horizontal synchronizing pulse S6 generated in synchronization with the vertical synchronizing signal is generated.
Will be disturbed frequently. In particular, the horizontal synchronization pulse S6
When the image is interrupted, a phenomenon occurs in which a jitter occurs or an image flows vertically, which hinders display. Therefore, when the composite synchronization signal S1 is not stable, the countdown circuit 1 is required as a stable supply source of the vertical synchronization signal.

The countdown circuit 1 is generally provided outside the control circuit 2 as a separate component, takes in the composite synchronizing signal S1 via a terminal 28, and is formed from an oscillation signal output from a ceramic oscillator 34 connected exclusively. A stable vertical synchronizing signal S2 is supplied from a terminal 29 to a terminal 26 of the control circuit 2.

FIG. 5 is a block circuit diagram of the control circuit 2 and its periphery. 5, the same portions as those shown and described in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.
The oscillator 37 generates an oscillation signal S7 having an oscillation frequency f0 = nfH obtained by multiplying the horizontal frequency fH by an integer n by an fH frequency divider 38.
Give to. As an example, the oscillation frequency f0 is set to 7.68 MHz.
z (f0 = 488fH). The fH frequency divider 38 converts the input oscillation signal S7 into an internal horizontal synchronizing signal S8 having a frequency fH (= f0 / 488 = 15.74 KHz) obtained by dividing the input oscillation signal S7 by a factor of 488. The signal is output to the LCD control circuit 47 via the signal input terminal 50. At the same time, a horizontal frequency signal S8 'having the same pulse as the internal horizontal synchronizing signal S8 and having the frequency fH is output to the phase comparator 39.

The phase comparator 39 compares the phase of the input horizontal frequency signal S8 'with the phase of the external horizontal synchronizing signal S1' included in the composite synchronizing signal S1, and adjusts the phase difference between the two signals based on the result. The adjustment signal S9 is output to the loop filter 36. The loop filter 36 has an oscillation control voltage S10 adjusted based on the input adjustment signal S9.
Is output to the oscillator 37.

The phase comparator 39 inside the control circuit 2
fH frequency divider 38 and loop filter 3 outside control circuit 2
6. Since the PLL circuit section 40 (omitted in FIG. 3) is constituted by the oscillator 37, the internal horizontal synchronizing signal S8 and the external horizontal synchronizing signal S1 'are synchronized with the oscillation frequency f0.

The LCD control circuit 47 has horizontal shift pulses P3, P synchronized with the input stable vertical synchronization signal S2.
4 and the horizontal synchronization pulse S6, and the vertical shift pulses P1 and P2 synchronized with the input stable internal horizontal synchronization signal S8.
And a vertical synchronization pulse S4 and a line switch signal S5
To the signal electrode drive circuit 3 via the control signal output terminal 48.
And output to the scan electrode drive circuit 4.

[0014]

As described above, in order to obtain a more stable and fine image, a stable vertical synchronizing signal S2 is required.
Is indispensable, and the control circuit 2 of the display device must receive the supply of the vertical synchronizing signal S2 stabilized by the countdown circuit 1. In particular, if the display device is a TFT-LC
In the case where the display elements are provided in a matrix such as a D display panel, if the timing of the scanning signal line and the data signal line is shifted, jitter may occur or an image may flow vertically. In order to solve such a problem, it is effective to use the vertical synchronization signal generated by the above-described countdown method.

However, the countdown circuit 1 exists independently as a one-chip integrated circuit, and requires a dedicated ceramic oscillator 34 for obtaining a vertical oscillation signal having a large mounting area. In addition, a dedicated oscillator 37 for obtaining the horizontal synchronizing signal S8 is connected as a separate component in the control circuit 2, and the mounting area is further increased.

An object of the present invention is to solve such a problem and to provide a display control circuit capable of reducing a mounting area.

[0017]

In order to achieve the above object, a display control circuit according to the present invention comprises a first frequency divider for dividing the output of an oscillator to a horizontal frequency, and a first frequency divider for the first frequency divider. A first phase comparator for comparing the output with the input horizontal synchronizing signal and controlling the oscillator based on the comparison output; a second frequency divider for dividing the output of the oscillator to obtain a vertical frequency; the based second phase comparator for comparing the output of the vertical synchronizing signal and the second frequency divider, the output of the second phase comparator
The phase difference compared by the phase comparator is within a predetermined threshold.
If so, it is determined that the phases match, and the output of the second frequency divider is output.
Force, and if the phase difference exceeds a predetermined threshold
If the input vertical synchronizing signal is
A switching circuit for selecting and outputting a signal, and a control circuit for driving and controlling a display device based on the output of the first frequency divider and the output of the switching circuit are provided in a one-chip integrated circuit device. And In this case, the display device includes display elements arranged in a matrix, and the signal timings of the scanning signal lines and the data signal lines are controlled by the output of the control circuit.

[0018]

In this case, the output of one oscillator becomes the first
Is used as a horizontal frequency signal by being divided by the second divider, and is used as a vertical frequency signal by being divided by the second divider, so that only one oscillator is required. The first and second frequency dividers, the first and second phase comparators,
Since the switching circuit and the control circuit are provided in the one-chip integrated circuit device, the mounting area is reduced in combination with the need for only one oscillator as described above.

[0019]

FIG. 1 is a block circuit diagram showing a control circuit 35 of a TFT-LCD device 5 embodying the present invention and its periphery. The video signal according to this embodiment is NT
It is based on the SC system. In FIG. 1, the control circuit 35 includes an LCD control circuit 47, phase comparators 39 and 43,
fH divider 38, 4fH divider 41, fV divider 42,
The output switch 44 is manufactured on the same semiconductor substrate as a one-chip integrated circuit, has all the functions of the control circuit 2 of FIG. 3 described above, and further includes a circuit of a countdown vertical synchronization output unit 46. It is. An oscillator 37 used for the control circuit 35 and a loop filter 36 for controlling the oscillator 37 are arranged outside the control circuit 35 and connected by soldering or the like.

The oscillator 37 outputs an oscillation signal S7 having an oscillation frequency f0 = nfH obtained by multiplying the horizontal frequency fH by an integer n to fH.
The signal is output to the frequency divider 38, and at the same time, the oscillation signal S7 is output to the 4fH frequency divider 41. As an example, the oscillation frequency f0 is set to 7.68 MHz (f0 = 488fH) as in the conventional case. The fH frequency divider 38 divides the oscillation frequency f0 of the input oscillation signal S7 by a factor of 488 to obtain a frequency fH (=
f0 / 488 = 15.73 KHz) and converts it to the internal horizontal synchronizing signal input terminal 50.
To the LCD control circuit 47 via. At the same time, a horizontal frequency signal S8 'having the same frequency as the internal horizontal synchronizing signal S8 and having the frequency fH is supplied to the phase comparator 39.

The phase comparator 39 compares the phase of the input horizontal frequency signal S8 'with the phase of the external horizontal synchronizing signal S1' included in the composite synchronizing signal S1, and matches the phase difference between the two signals based on the result. The adjustment signal S9 is output to the loop filter 36. The loop filter 36 has an oscillation control voltage S10 adjusted based on the input adjustment signal S9.
Is output to the oscillator 37.

The phase comparator 3 in the control circuit 35 described above
9, since the PLL circuit section 40 (omitted in FIG. 2) comprises the fH frequency divider 38, the loop filter 36 outside the control circuit 35, and the oscillator 37, the internal horizontal synchronizing signal S8 and the External horizontal synchronization signal S1 '
Will be synchronized.

On the other hand, the 4fH frequency divider 41 outputs the oscillation frequency f
0 is received from the oscillator 37, and the
Frequency 4fH (= 4f0 / 488 = f0) divided by 1 /
/122=62.94 KHz) is output to the fV divider 42 as the reference clock signal S11. The fV frequency divider 42 receives the reference clock signal S11,
Vertical synchronization frequency fV obtained by dividing fH by 1/1050
(= 4fH / 1050 = 59.94 Hz) is output to the phase comparator 43 and the output switch 44 as the vertical frequency signal S12.

The frequency separation circuit 45 receives the composite synchronizing signal S1 inputted from the terminal 7, separates the composite synchronizing signal S1, and compares only the components of the vertical synchronizing signal S13 having the vertical synchronizing frequency fV (= 59.94 Hz). Output to the switch 43 and the output switch 44.

The phase comparator 43 compares the phases of the input vertical frequency signal S12 and vertical synchronizing signal S13 having the same vertical synchronizing frequency fV (= 59.94 Hz), and outputs an output switching signal S14 as a result of the phase comparison. Output switch 4
4 is output. Vertical frequency signal S12 and vertical synchronization signal S
If the phase difference of No. 13 is within a predetermined threshold value (for example, 1 / 4fH = about 16 μs), it is determined that the phases are matched, and "
When the phase difference exceeds the threshold value, it is determined that the phase is shifted, and the level becomes “High.” When the vertical synchronization signal S13 is not detected, the “Low” level is obtained. However, the operation of changing the level of the output switching signal S14 is not performed every one vertical cycle, but is performed every predetermined period (for example, four times the vertical period).

The output switch 44 outputs a vertical frequency signal S1 based on the voltage level of the input output switch signal S14.
2 and the vertical synchronization signal S13 are switched as the vertical synchronization signal S2 to the vertical synchronization signal input terminal 49 of the LCD control circuit 47 in the control circuit 35. When the output switching signal S14 is at the "Low" level, the vertical synchronization signal S12 is switched as the vertical synchronization signal S2, and when the output switching signal S14 is at the "High" level, the vertical synchronization signal S12 is switched.
13 is switched as the vertical synchronization signal S2.

At this time, the output switch 44 repeatedly outputs a reset signal S15 having a reset pulse based on the vertical synchronizing signal S2 to the fV frequency divider 42 in order to match the phases, so that the vertical synchronizing signal S12 and the vertical synchronizing signal S13
Are shifted, the vertical synchronizing signal S13 is selected as the vertical synchronizing signal S2, the same vertical synchronizing frequency fV (= 59.94H) as the vertical synchronizing signal S13 is originally used.
The phase of the vertical frequency signal S12 having z) immediately matches the phase of the vertical synchronization signal S13. Similarly, since the phases of the vertical synchronizing signal S12 and the vertical synchronizing signal S13 match, when the vertical synchronizing signal S12 is selected as the vertical synchronizing signal S2, the phase of the vertical frequency signal S12 coincides with its own phase. Indirectly coincides with the phase of the vertical synchronization signal S13. This operation is repeatedly performed in real time, and the phase of the vertical frequency signal S12 constantly coincides with the phase of the vertical synchronization signal S13. It can be a substitute signal for the signal S12.

If the output switching signal S14 is "High"
In the case of the level, the vertical synchronization signal S12 has a vertical frequency that is not in a normal relationship with the horizontal frequency, so the vertical synchronization signal S13 is used without using the vertical synchronization signal S12.
Is switched as the vertical synchronization signal S2.

The LCD control circuit 47 generates a horizontal shift pulse P synchronized with the input stable internal horizontal synchronizing signal S8.
3, P4 and the horizontal synchronizing pulse S6
, Via the control signal input terminal 48, and the vertical shift pulse P1 synchronized with the input stable vertical synchronizing signal S2,
P2 and vertical synchronization pulse S4 and line switch signal S
5 is supplied to the signal electrode drive circuit 3 through the control signal output terminal 48 as shown in FIG.

FIG. 2 shows a TFT-L according to the present invention.
FIG. 3 is a block circuit diagram of a CD panel 5 and its driving circuits 3, 4 and a control circuit 35. In FIG. 2, the same parts as those shown and described in FIGS. As a display device controlled by the control circuit 35 having the above-described countdown vertical synchronization output section 46, the TFT-LCD display panel 5 shown in FIG. 2 has the same configuration as that of FIG. As a display device, such a TFT-L
The display device is not limited to the CD display panel 5, but may be another display device such as an electroluminescence display (not shown) or a plasma display (not shown).

[0031]

As described above, according to the present invention,
Oscillation signals obtained from the display device control signal oscillator can be frequency-divided to generate a vertical synchronizing signal, so that the number of oscillators can be reduced to one, which reduces the mounting area and the manufacturing cost. As a result, the manufacturing process can be simplified, and the yield rate can be improved. In the present invention, the input
The phase difference between the vertical synchronization signal and the output of the second frequency divider is
If within the predetermined threshold, the output of the second frequency divider is
Select as a sync signal and if it exceeds a predetermined threshold
For example, a switching circuit that selects and outputs the input vertical synchronization signal is provided.
So that the phase difference exceeds the threshold value.
The output of the second frequency divider (in this case,
Incorrect vertical sync signal), not the input vertical sync signal
Signal is selected and the output of the switching circuit is used.
A malfunction can be prevented from occurring in the subsequent circuit.

Further, since the countdown vertical synchronization output section for supplying a stable vertical synchronization signal and the control circuit are formed as a one-chip integrated circuit in one process on the same semiconductor substrate, the countdown circuit and the control circuit are controlled. The circuit does not need to be treated as a separate component, the mounting area can be significantly reduced, and the entire display device can be reduced in size.
At the same time, the manufacturing cost is reduced, the manufacturing process can be simplified, and the yield rate is improved.

Further, when the display device has display elements in a matrix such as a TFT-LCD display panel, the signal timings of the scanning signal lines and the data signal lines are controlled by the output of the control circuit. This makes it possible to obtain a stable image without causing jitter or vertical image flow.

In particular, if the display device is a liquid crystal display device, the entire display device can be made thinner and smaller, and its application range is further increased.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a control circuit of a TFT-LCD device embodying the present invention and its periphery.

FIG. 2 is a block circuit diagram of a TFT-LCD panel embodying the present invention and a driving circuit and a control circuit thereof.

FIG. 3 is a block circuit diagram of a conventional TFT-LCD panel and its driving circuit and control circuit.

FIG. 4 is a circuit diagram showing a conventional TFT-LCD panel and its peripherals;

FIG. 5 is a block circuit diagram showing a control circuit of a conventional TFT-LCD device and its periphery.

FIG. 6 is a waveform chart of each signal in the TFT-LCD device.

[Description of Signs] 1 Countdown circuit 2 Control circuit 3 Signal electrode drive circuit 4 Scan electrode drive circuit 5 TFT-LCD panel 6 to 30 Terminal 31 Vertical shift register 32 Line memory 33 Horizontal shift register 34 Ceramic oscillator 35 Control circuit 36 Loop Filter 37 Oscillator 38 fH frequency divider 39 Phase comparator 40 PLL circuit 41 4 fH frequency divider 42 fV frequency divider 43 Phase comparator 44 Output switch 45 Frequency separation circuit 46 Countdown vertical synchronization output unit 47 LCD control circuit 48 Control signal Output terminal 49 Vertical synchronization signal input terminal 50 Internal horizontal synchronization signal input terminal S1 Composite synchronization signal S1'External horizontal synchronization signal S2 Vertical synchronization signal S3 Video signal S4 Vertical synchronization pulse S5 Line switch signal S6 Horizontal synchronization pulse S7 Oscillation signal S8 Internal water Synchronization signal S8 'Horizontal frequency signal S9 Adjustment signal S10 Oscillation voltage S11 Reference clock signal S12 Vertical frequency signal S13 Vertical synchronization signal S14 Output switching signal S15 Reset signal VCC Power supply voltage TFT transistor C Capacitance C' signal storage capacitor L Signal electrode LCD Liquid crystal display element P1, P2 Vertical shift pulse P3, P4 Horizontal shift pulse

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Kawaguchi 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Co., Ltd. (56) References Japanese Utility Model Sho-63-55682 (JP, U) (58) Field (Int.Cl. ⁷ , DB name) H04N 5/66

Claims (3)

(57) [Claims] A first frequency divider for dividing the output of the oscillator to a horizontal frequency, comparing the phase of the output of the first frequency divider with an input horizontal synchronizing signal, and controlling the oscillator with the comparison output A first phase comparator, a second frequency divider for dividing the output of the oscillator to obtain a vertical frequency, and a second frequency comparator for comparing an input vertical synchronization signal with the output of the second frequency divider. A phase comparator, based on an output of the second phase comparator ,
If the compared phase difference is within a predetermined threshold, the phase is
Judging that they match, select the output of the second frequency divider,
If the phase difference exceeds a predetermined threshold, the phase
Output signal and select and output the input vertical sync signal.
And a control circuit for driving and controlling a display device based on an output of the first frequency divider and an output of the switching circuit, wherein the control circuit is provided in a one-chip integrated circuit device. circuit. 2. The display device according to claim 1, wherein the display device includes display elements arranged in a matrix, and controls signal timings of a scanning signal line and a data signal line by an output of the control circuit. Display control circuit. 3. The display control circuit according to claim 2, wherein said display device is a liquid crystal display device.