JPH06153122A - Display control circuit - Google Patents

Abstract

PURPOSE:To provide the display device in which its mount area is reduced by providing a count-down circuit to the control circuit of the display device and employing only one oscillation circuit. CONSTITUTION:An fV frequency divider 42 outputs a vertical frequency signal S12 to a phase comparator 43 and an output changeover device 44. The phase comparator 43 compares the phase of the inputted vertical frequency signal S12 with the phase of a vertical synchronizing signal S13 and outputs an output switching signal S14 used to represent the result to the output changeover device 44. Upon the recognition of a phase deviation, the output changeover device 44 measures a timing for phase matching and outputs a reset signal S15 to the fV frequency divider 42. Thus, the phase of the vertical frequency signal S12 and the phase of the vertical synchronizing signal S13 are coincidence at all times. When a fault takes place in the vertical synchronizing signal S13, the output changeover device 44 selects the vertical frequency signal S12 having the same phase as the vertical synchronizing signal S13 in the normal state as an output as a vertical synchronizing signal S2 to a vertical synchronizing signal input terminal 49 of an LCD voltage controlled oscillator 47 immediately.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control circuit for a television receiver, and more particularly to a display control circuit for a small television receiver used outdoors or in a vehicle.

[0002]

2. Description of the Related Art First, a conventional driving method of a display device using a liquid crystal display device (hereinafter referred to as "LCD") in which thin film transistors (hereinafter referred to as "TFT") are arranged in a matrix on a display screen will be described. Is TFT-LC
4 is a block circuit diagram of a D panel 5, its drive circuits 3 and 4, and a control circuit 35. FIG. FIG. 4 shows a TFT-LCD panel 5
3 is a circuit diagram of the drive circuits 3 and 4. FIG. The following video signals are based on the NTSC system.

In FIG. 3, the power supply voltage Vcc is the terminal 30 of the countdown circuit 1, the terminal 27 of the control circuit 2, the terminal 13 of the signal electrode drive circuit 3, and the terminal 1 of the scan electrode drive circuit.
7 is applied. The control circuit 2 is externally connected to the terminal 7
Based on the composite sync signal S1 directly input via
A vertical synchronizing pulse S4, vertical shift pulses P1 and P2 for synchronizing the vertical pixels, and a line switch signal S5 are generated, and the terminals 11 and 9 of the signal electrode driving circuit 3 are generated via terminals 20, 18, 19 and 21, respectively. 10 and 12, and also generates a horizontal synchronizing pulse S6 and horizontal shift pulses P3 and P4 for synchronizing the horizontal pixels, and the terminals 16 of the scan electrode driving circuit 4 are supplied via the terminals 22, 24 and 23, respectively. , 14, 15 are output. The signal electrode drive circuit 3 receives the video signal S input from the outside through the terminal 6.
3 is taken into the terminal 8.

The operation of the signal electrode drive circuit 3 and the scan electrode drive circuit 4 for driving the TFT-LCD panel 5, which is well known, will be briefly described with reference to FIG.
FIG. 6 shows the signal waveforms of the vertical shift pulses P1 and P2, the vertical synchronizing pulse S4, the video signal S3, the line switch signal S5, the horizontal shift pulses P3 and P4, and the horizontal synchronizing pulse S6 shown in FIG. In the circuit shown in FIG. 4, the TFT
-Each transistor TFTij that operates as an electrode selection switch of each liquid crystal display element LCDij on the LCD panel 5,
The fine field effect transistors are provided so as to be arranged in a matrix in the form of TFTs. The video signal S3 input to the terminal 8 is simultaneously output in parallel to each source s of the i-th transistor TFTi from the left which controls the line memory 32. By the vertical synchronizing pulse S4 input to the terminal 11 and the vertical shift pulses P1 and P2 input to the terminals 9 and 10, the respective stages of the shift register 31 in the signal electrode driving circuit 3 are sequentially moved from left to right. When it is made conductive for a certain pulse duration, a voltage is applied to the gate g of the transistor TFTi accordingly during that period, and the transistor TFTi is made conductive one after another for a certain pulse duration. The terminals 13 and 17
A power supply voltage Vcc is applied to the.

As a result, in the signal electrode drive circuit 3,
The temporally continuous video signal S4 is 1 in the horizontal direction of one scanning line.
The pixels are divided into pixels, and the capacitors Ci, which are on the line memory 32 and are connected to the drains d of the transistors TFTi, are sequentially stored as applied voltages of one pixel. The image signal for one scanning line is for all capacitors Ci
When these signals are time-divided and stored in the transistor T, they operate as a switch of the line memory 32.
The source s and drain d of FTLi are connected to the gate g at the terminal 12
The line switch signal S5 applied via the switch makes the capacitors C i and the signal electrodes L i conductive.

On the other hand, the scan electrode driving transistor TFTj connected to the scan electrode is input by the horizontal shift register 33 in the scan electrode driving circuit 4 from the horizontal synchronizing pulse S6 input from the terminal 16 and the terminals 14 and 15. In synchronism with the horizontal shift pulses P3 and P4, the driving is performed one by one from the first row to the lower row in order to be in a conductive state for one scanning line period. As a result, the transistor TF connected to the jth scan electrode in synchronization with the horizontal synchronization pulse S6.
When Tj is turned on, all sources s and drains d of the transistors TFT1j, TFT2j, TFT3j, ..., TFTij, ... The voltage stored in each capacitor Ci, which is in conduction with each of the signal electrodes L1, L2, L3, ..., Li, ..., Is stored in each capacitance Cij of the pixel electrode in the i-th column and the j-th row. Be transferred. The electrostatic capacitance Cij is the sum of capacitances of the liquid crystal display element LCDij and the signal storage capacitance C'ij connected in parallel, and the transmittance of the liquid crystal display element LCDij is controlled by the voltage stored therein.

When the above operation is performed from the first row of the TFT-LCD panel 5 in order from top to bottom, the image signals are transferred to all the liquid crystal display elements LCDij. Furthermore, by repeating this operation, a moving image can be obtained based on the intercepted video signal.

However, as shown in FIG. 3, in the control circuit 2, the unstable composite synchronizing signal S taken into the terminal 25 is received.
If 1 is used as it is, the vertical synchronizing signal (not shown) generated from the composite synchronizing signal S1 also becomes unstable, and therefore the horizontal synchronizing pulse S6 generated in synchronization with the vertical synchronizing signal S6.
Will be disturbed frequently. In particular, the horizontal sync pulse S6
If the image is interrupted, a phenomenon occurs such that jitter occurs or an image flows vertically, which hinders display. Therefore, when the composite sync signal S1 is not stable, the countdown circuit 1 is required as a stable supply source of the vertical sync signal.

The countdown circuit 1 is generally provided as a separate component outside the control circuit 2 and takes in the composite synchronizing signal S1 via a terminal 28, and is made from an oscillation signal output from a ceramic oscillator 34 connected exclusively. The stable vertical synchronizing signal S2 is supplied from the terminal 29 to the terminal 26 of the control circuit 2.

FIG. 5 is a block circuit diagram of the control circuit 2 and its periphery. 5, the same parts as those shown and described in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.
The oscillator 37 produces an oscillation signal S7 having an oscillation frequency f0 = nfH obtained by multiplying the horizontal frequency fH by an integer n, by an fH frequency divider 38.
Give to. As an example, the oscillation frequency f0 is 7.68 MH
z (f0 = 488fH). The fH frequency divider 38 converts the input oscillation signal S7 into an internal horizontal synchronization signal S8 having a frequency fH (= f0 / 488 = 15.74 KHz) obtained by dividing the oscillation signal S7 by a factor of 1/488 to perform internal horizontal synchronization. The signal is output to the LCD control circuit 47 via the signal input terminal 50. At the same time, the horizontal frequency signal S8 'having the same pulse as the internal horizontal synchronizing signal S8 and having the frequency fH is output to the phase comparator 39.

The phase comparator 39 compares the phases of the input horizontal frequency signal S8 'and the external horizontal synchronizing signal S1' contained in the composite synchronizing signal S1, and based on the result, adjusts the phase difference between the two signals. The adjustment signal S9 is output to the loop filter 36. The loop filter 36 adjusts the oscillation control voltage S10 based on the input adjustment signal S9.
Is output to the oscillator 37.

The phase comparator 39 inside the control circuit 2 described above,
fH frequency divider 38 and loop filter 3 outside the control circuit 2
6. Since the PLL circuit section 40 (not shown in FIG. 3) is constituted by the oscillator 37, the internal horizontal synchronizing signal S8 and the external horizontal synchronizing signal S1 'are synchronized with the oscillation frequency f0.

The LCD control circuit 47 has horizontal shift pulses P3 and P3 synchronized with the input stable vertical synchronizing signal S2.
4 and the horizontal synchronizing pulse S6 and the vertical shift pulses P1 and P2 synchronized with the input stable internal horizontal synchronizing signal S8.
And vertical synchronizing pulse S4 and line switch signal S5
To the signal electrode drive circuit 3 via the control signal output terminal 48.
And to the scan electrode drive circuit 4.

[0014]

As described above, in order to obtain a more stable fine image, the stable vertical synchronizing signal S2
Is essential, and the control circuit 2 of the display device must be supplied with the vertical synchronizing signal S2 stabilized by the countdown circuit 1. In particular, the display device is TFT-LC
In the case where the display elements are provided in a matrix form such as a D display panel, if the timings of the scanning signal lines and the data signal lines are deviated, jitter may occur or an image may flow vertically. In order to solve such a problem, it is effective to use the vertical synchronizing signal generated by the above-mentioned countdown method.

However, the countdown circuit 1 exists independently as a one-chip integrated circuit and requires a dedicated ceramic oscillator 34 for obtaining a vertical oscillation signal having a large mounting area. Furthermore, in the control circuit 2 as well, a dedicated oscillator 37 for obtaining the horizontal synchronizing signal S8 is connected as a separate component, and the mounting area is further increased.

An object of the present invention is to provide a display control circuit which solves such a problem and can reduce the mounting area.

[0017]

In order to achieve the above object, the display control circuit of the present invention comprises a first frequency divider for dividing an output of an oscillator into a horizontal frequency, and a first frequency divider of the first frequency divider. A first phase comparator for phase-comparing the output with an input horizontal synchronizing signal and controlling the oscillator with the comparison output; and a second frequency divider for dividing the output of the first oscillator into a vertical frequency. A second phase comparator for comparing the input vertical synchronizing signal and the output of the second frequency divider, and the output of the second frequency divider based on the output of the second phase comparator and the input vertical A switching circuit that selects and outputs one of the synchronization signals, and a control circuit that drives and controls the display device based on the output of the first frequency divider and the output of the switching circuit are included in a one-chip integrated circuit device. It is characterized by being provided. In this case, the display device includes display elements arranged in a matrix, and the signal timings of the scanning signal lines and the data signal lines are controlled by the output of the control circuit. A liquid crystal display device is used as this display device.

[0018]

In this way, the output of one oscillator is the first
Since it is used as a horizontal frequency signal by being divided by the frequency divider of 1 and used as a vertical frequency signal by being divided by the second frequency divider, one oscillator is sufficient. The first and second frequency dividers, the first and second phase comparators,
Since the switching circuit and the control circuit are provided in the one-chip integrated circuit device, the mounting area is reduced in combination with the fact that one oscillator is sufficient as described above.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A block circuit diagram of a control circuit 35 of a TFT-LCD device 5 embodying the present invention and its peripherals will be described with reference to FIG. The video signal relating to the present embodiment is NT
It is based on the SC method. In FIG. 1, the control circuit 35 includes an LCD control circuit 47, phase comparators 39 and 43,
fH frequency divider 38, 4fH frequency divider 41, fV frequency divider 42,
The output switch 44 is manufactured on the same semiconductor substrate as a one-chip integrated circuit, has all the functions of the control circuit 2 of FIG. 3 described above, and is further provided with a circuit of the countdown vertical synchronization output unit 46. Is. The oscillator 37 used for the control circuit 35 and the loop filter 36 for controlling the oscillator 37 are arranged outside the control circuit 35 and are connected by soldering or the like.

The oscillator 37 fH produces an oscillation signal S7 having an oscillation frequency f0 = nfH obtained by multiplying the horizontal frequency fH by an integer n.
The oscillation signal S7 is output to the frequency divider 38, and at the same time, the oscillation signal S7 is output to the 4fH frequency divider 41. As in the conventional case, the oscillation frequency f0 is set to 7.68 MHz (f0 = 488 fH) as an example. The fH frequency divider 38 divides the oscillation frequency f0 of the input oscillation signal S7 by a factor of 488, fH (=
f0 / 488 = 15.73 KHz) and the internal horizontal synchronizing signal S8 is converted into an internal horizontal synchronizing signal S8.
To the LCD control circuit 47. At the same time, a horizontal frequency signal S8 'having the same frequency as the internal horizontal synchronizing signal S8 and having a frequency fH is supplied to the phase comparator 39.

The phase comparator 39 compares the phases of the input horizontal frequency signal S8 'and the external horizontal synchronizing signal S1' included in the composite synchronizing signal S1, and based on the result, adjusts the phase difference between the two signals. The adjustment signal S9 is output to the loop filter 36. The loop filter 36 adjusts the oscillation control voltage S10 based on the input adjustment signal S9.
Is output to the oscillator 37.

The phase comparator 3 in the control circuit 35 described above
9. Since the PLL circuit unit 40 (not shown in FIG. 2) is composed of the loop filter 36 outside the fH frequency divider 38, the control circuit 35, and the oscillator 37, the internal horizontal synchronizing signal S8 is generated for the oscillation frequency f0. External horizontal sync signal S1 '
Will be synchronized.

On the other hand, the 4fH frequency divider 41 has an oscillation frequency f
The oscillation signal S7 of 0 is received from the oscillator 37 and
Frequency divided by 1 / 4h (= 4f0 / 488 = f0
It is output to the fV frequency divider 42 as a reference clock signal S11 having /122=62.94 KHz). The fV frequency divider 42 receives the reference clock signal S11 and outputs the frequency 4
Vertical sync frequency fV obtained by dividing fH by 1/1050
The vertical frequency signal S12 having (= 4fH / 1050 = 59.94Hz) is output to the phase comparator 43 and the output switch 44.

The frequency separating circuit 45 receives the composite synchronizing signal S1 inputted from the terminal 7 and separates it, and phase compares only the component of the vertical synchronizing signal S13 having the vertical synchronizing frequency fV (= 59.94 Hz). To the output device 43 and the output switching device 44.

The phase comparator 43 compares the phases of the input vertical frequency signal S12 and vertical synchronization signal S13 having the same vertical synchronization frequency fV (= 59.94 Hz), and the output switching signal S14 as a result of the phase comparison. Output switch 4
Output to 4. Vertical frequency signal S12 and vertical synchronization signal S
If the phase difference of 13 is within a predetermined threshold value (for example, 1/4 fH = about 16 μs), it is determined that the phases are matched.
Low level, and if the phase difference exceeds the threshold value, it is determined that the phases are out of phase and becomes High level. Further, when the vertical synchronization signal S13 is not detected, it is at Low level. However, the operation of changing the level of the output switching signal S14 in this way is not performed every vertical cycle but is performed every predetermined period (for example, four times the vertical period).

The output switching unit 44, based on the voltage level of the input output switching signal S14, outputs the vertical frequency signal S1.
2 or the vertical synchronizing signal S13 is switched to be output as the vertical synchronizing signal S2 to the vertical synchronizing signal input terminal 49 of the LCD control circuit 47 in the control circuit 35. When the output switching signal S14 is at "Low" level, the vertical synchronizing signal S12 is switched as the vertical synchronizing signal S2, and when the output switching signal S14 is at "High" level, the vertical synchronizing signal S12.
13 is switched as the vertical synchronizing signal S2.

At this time, the output switching unit 44 repeatedly outputs the reset signal S15 having a reset pulse based on the vertical synchronizing signal S2 to the fV frequency divider 42 in order to match the phases, so that the vertical synchronizing signal S12 and the vertical synchronizing signal S13
When the vertical synchronizing signal S13 is selected as the vertical synchronizing signal S2 because the phase of the vertical synchronizing signal is shifted, the vertical synchronizing frequency fV (= 59.94H) which is originally the same as the vertical synchronizing signal S13.
The phase of the vertical frequency signal S12 having z) instantly matches the phase of the vertical synchronizing signal S13. Similarly, when the vertical synchronizing signal S12 is selected as the vertical synchronizing signal S2 because the vertical synchronizing signal S12 and the vertical synchronizing signal S13 are in phase with each other, the phase of the vertical frequency signal S12 coincides with its own phase. , Indirectly and immediately coincides with the phase of the vertical synchronizing signal S13. This operation is repeatedly performed in real time, and the phase of the vertical frequency signal S12 constantly matches the phase of the vertical synchronizing signal S13. Therefore, the vertical frequency signal S13 can be synchronized with the vertical synchronizing signal whenever there is a request for switching. It can be an alternative signal to the signal S12.

If the output switching signal S14 is "High".
In the case of the level, since the vertical synchronizing signal S12 has a vertical frequency that is not in a normal relationship with the horizontal frequency, the vertical synchronizing signal S13 is not used and the vertical synchronizing signal S13 is not used.
Is switched as the vertical synchronizing signal S2.

The LCD control circuit 47 has a horizontal shift pulse P synchronized with the input stable internal horizontal synchronizing signal S8.
3, P4 and horizontal synchronizing pulse S6 are applied to the scan electrode driving circuit 4
A vertical shift pulse P1, which is synchronized with the stable vertical synchronizing signal S2 input thereto,
P2, vertical sync pulse S4, and line switch signal S
5 is applied to the signal electrode drive circuit 3 via the control signal output terminal 48 as shown in FIG.

FIG. 2 shows a TFT-L embodying the present invention.
4 is a block circuit diagram of a CD panel 5, its drive circuits 3 and 4, and a control circuit 35. FIG. In FIG. 2, the same parts as those shown and described in FIGS. As a display device controlled by the control circuit 35 having the above-described countdown vertical synchronization output section 46, the TFT-LCD display panel 5 shown in FIG. 2 has the same configuration as that of FIG. As a display device, such a TFT-L
The display device is not limited to the CD display panel 5 and may be another display device such as an electroluminescence display (not shown) or a plasma display (not shown).

[0031]

As described above, according to the present invention,
Since the vertical synchronizing signal can be generated by dividing the oscillation signal obtained from the display device control signal oscillator, the number of oscillators can be reduced to one, and the mounting area can be reduced and the manufacturing cost can be reduced. As a result, the manufacturing process can be simplified and the yield rate can be improved.

Further, since the countdown vertical synchronization output section for stable vertical synchronization signal supply and the control circuit are manufactured as a one-chip integrated circuit in one step on the same semiconductor substrate, the countdown circuit and the control circuit are controlled. The circuit does not have to be treated as a separate component, the mounting area can be significantly reduced, and the entire display device can be downsized.
At the same time, the manufacturing cost is reduced, the manufacturing process can be simplified, and the yield rate is improved.

Further, when the display device has a matrix of display elements such as a TFT-LCD display panel, the signal timing of the scanning signal line and the data signal line is controlled by the output of the control circuit. As a result, it is possible to obtain a stable image without causing jitter or vertically flowing the image.

In particular, if this display device is a liquid crystal display device, the entire display device can be made thin and small, and its application range is further increased.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a control circuit of a TFT-LCD device embodying the present invention and its periphery.

FIG. 2 is a block circuit diagram of a TFT-LCD panel embodying the present invention and its drive circuit and control circuit.

FIG. 3 is a block circuit diagram of a conventional TFT-LCD panel and its drive circuit and control circuit.

FIG. 4 is a circuit diagram showing a conventional TFT-LCD panel and its drive circuit periphery.

FIG. 5 is a block circuit diagram of a control circuit of a conventional TFT-LCD device and its periphery.

FIG. 6 is a waveform diagram of each signal in the TFT-LCD device.

[Explanation of symbols]

 1 countdown circuit 2 control circuit 3 signal electrode drive circuit 4 scan electrode drive circuit 5 TFT-LCD panel 6 to 30 terminals 31 vertical shift register 32 line memory 33 horizontal shift register 34 ceramic oscillator 35 control circuit 36 loop filter 37 oscillator 38 fH Frequency divider 39 Phase comparator 40 PLL circuit 41 4fH frequency divider 42 fV frequency divider 43 Phase comparator 44 Output switcher 45 Frequency separation circuit 46 Countdown vertical synchronization output section 47 LCD control circuit 48 Control signal output terminal 49 Vertical synchronization Signal input terminal 50 Internal horizontal sync signal input terminal S1 Composite sync signal S1 'External horizontal sync signal S2 Vertical sync signal S3 Video signal S4 Vertical sync pulse S5 Line switch signal S6 Horizontal sync pulse S7 Oscillation signal S8 Internal horizontal sync signal S8 Horizontal frequency signal S9 Adjustment signal S10 Oscillation voltage S11 Reference clock signal S12 Vertical frequency signal S13 Vertical synchronization signal S14 Output switching signal S15 Reset signal Vcc power supply voltage TFT transistor C Capacitance C'Signal storage capacitor L Signal electrode LCD Liquid crystal display element P1, P2 vertical shift pulse P3, P4 horizontal shift pulse

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Kawaguchi 22-22 Nagaike-cho, Abeno-ku, Osaka City, Osaka Prefecture

Claims (3)

[Claims] 1. A first frequency divider for dividing an output of an oscillator into a horizontal frequency and a phase comparison of an output of the first frequency divider with an input horizontal synchronizing signal and controlling the oscillator by a comparison output thereof. A first phase comparator, a second frequency divider that divides the output of the first oscillator into a vertical frequency, and compares an input vertical synchronization signal with the output of the second frequency divider. A second phase comparator; a switching circuit that selects and outputs one of the output of the second frequency divider and the input vertical synchronization signal based on the output of the second phase comparator; and the first frequency divider. And a control circuit for driving and controlling the display device on the basis of the output of the switching device and the output of the switching circuit, the display control circuit being provided in a one-chip integrated circuit device. 2. The display device comprises display elements arranged in a matrix, and the signal timings of the scanning signal lines and the data signal lines thereof are controlled by the output of the control circuit. Display control circuit. 3. The display control circuit according to claim 2, wherein the display device is a liquid crystal display device.