JPH09307786A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale and to decrease electromagnetic noise to be emitted. SOLUTION: The image display device 100 is made up of a camera block 110 and a display block 120. In the camera block 110, an image pickup signal outputted from an image pickup element 111 is processed by a signal processing circuit 112 to obtain a video signal SV corresponding to an object. In the display block 120, a video signal SV outputted from the camera block 110 is fed to a liquid crystal display element 121 via the signal processing circuit 122 and an image corresponding to an object is displayed on the display element 121. The display block 120 has no reference oscillator. A timing generator 123 of the display block 120 generates a drive signal or the like for the display element 121 based on a reference clock signal CK generated by a reference oscillator 114 and a horizontal synchronizing signal HD and a vertical synchronizing signal VD outputted from a synchronizing signal generator 115.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for displaying an image based on a video signal output from a video section on a display element of a display section. Specifically, by providing only a reference oscillator for generating the reference clock signal used in the video section and the display section, the circuit scale is reduced and the radiated electromagnetic wave noise is reduced. It relates to the device.

[0002]

2. Description of the Related Art FIG. 15 shows an example of a conventional image display device 200. In this example, CCD (charge coupled d
camera block 210 using a solid-state image sensor
And a liquid crystal display (LCD)
And a display block 220 using

The camera block 210 has a CCD solid-state image pickup device 211 and a signal processing circuit 212 for processing an image pickup signal output from the CCD solid-state image pickup device 211 to obtain a video signal SV. Signal processing circuit 212
Then, processing such as edge enhancement, color reproduction correction, knee compression, and gamma correction is performed on the image pickup signal.

The camera block 210 includes a timing generator 213 for generating a CCD driving signal used in the CCD solid-state image pickup device 211 and a clock / synchronization signal for camera signal processing used in the signal processing circuit 212. A reference oscillator 214 for generating a reference clock signal CK1 in the camera block 210, and a clock / synchronization for generating a CCD driving signal used in the timing generator 213 based on the reference clock signal CK1 generated by the reference oscillator 214. It has a synchronization generator 215 for generating a clock / synchronization signal for processing a signal and a camera signal used in the signal processing circuit 212.

The display block 220 includes a liquid crystal display element 22.
1, a signal processing circuit 222 that performs processing such as amplification on the video signal SV output from the signal processing circuit 212 of the camera block 210 and supplies it to the liquid crystal display 221, and an LCD used in the liquid crystal display element 221. It has a timing generator 223 for generating a driving signal and a clock / synchronization signal for LCD signal processing used in the signal processing circuit 222.

Further, the display block 220 has a video signal S
It has a sync separation circuit 224 for separating the horizontal sync signal HD and the vertical sync signal VD from V, and a reference oscillator 225 for generating a reference clock signal CK2 synchronized with the horizontal sync signal HD separated by the sync separation circuit 224. ing.
In the timing generator 223 described above, based on the synchronization signals HD and VD separated by the synchronization separation circuit 224 and the reference clock signal CK2 generated by the reference oscillator 225, a clock / LCD driving signal / clock for LCD signal processing is generated.
A sync signal is generated.

The operation of the image display device 200 shown in FIG. 15 will be described.

In the camera block 210, the CCD
The image pickup signal output from the solid-state image pickup device 211 is supplied to a signal processing circuit 212 and subjected to edge enhancement, color reproduction correction, knee compression, gamma correction, etc., and the signal processing circuit 212 outputs a video signal SV corresponding to the subject. can get. Further, in the display block 220, the video signal SV supplied from the camera block 210 is supplied to the signal processing circuit 222, and after being subjected to processing such as amplification, the liquid crystal display element 221.
The image corresponding to the subject is displayed on the liquid crystal display element 221.

[0009]

As described above, FIG.
In the image display device 200 shown in FIG. 5, the horizontal synchronizing signal HD separated from the video signal SV is displayed on the display block 220.
It has a reference oscillator 225 for generating a reference clock signal CK2 synchronized with. In this case, a PLL (phase-locked loop) circuit is required for phase-locking the reference clock signal CK2 with the horizontal synchronizing signal HD, and the circuit size of the reference oscillator 225, that is, the display block 220.
However, there was a problem that the circuit scale of was large.

In the image display device 200 shown in FIG. 15, the frequency of the reference clock signal CK2 generated by the reference oscillator 225 is uniquely determined by the number of horizontal pixels of the liquid crystal display element 221. Therefore, it is necessary to prepare a liquid crystal display element 221 of each type for each frequency of the reference clock signal CK2, which causes a cost increase.

Further, in the image display device 200 shown in FIG. 15, the frequency of the reference clock signal CK1 generated by the reference oscillator 214 of the camera block 210 and the reference clock signal CK2 generated by the reference oscillator 225 of the display block 220. If the frequency is different, display block 2
The image displayed on the liquid crystal display device 221 of 20 has a display unevenness in the horizontal direction due to the influence of folding back due to resampling, and there is a defect that the line width of the character varies depending on the display position and is difficult to see.

Further, in the image display device 200 shown in FIG. 15, the reference clock signal CK is supplied to the camera block 210.
Besides having a reference oscillator 214 for generating 1,
Since the display block 220 has the reference oscillator 225 for generating the reference clock signal CK2, it has a drawback that the electromagnetic wave noise radiated increases.

Therefore, the present invention provides an image display device which reduces the circuit scale and reduces radiated electromagnetic noise. The present invention also provides an image display device capable of coping with the frequencies of a plurality of reference clock signals with a single display element. Further, the present invention provides an image display device in which a display image is not or hardly influenced by a horizontal display position.

[0014]

The present invention provides an image display device comprising a video section for outputting a video signal and a display section for displaying an image based on the video signal output from the video section on a display element. , And has only one reference oscillator for generating the reference clock signal used in the video section and the display section.

A video signal output from a video unit such as a video camera or a video tape recorder is supplied to the display unit,
An image based on a video signal is displayed on a display element of this display unit, for example, a liquid crystal display element. Only one reference oscillator is provided. The reference oscillator is arranged in, for example, the video section or the display section, and the reference clock signal generated by the reference oscillator is used in the video section and the display section.

For example, in the display section, the reference clock signal generated by the reference oscillator is directly used as the reference clock signal of the driving signal for driving the display element. In the display section, the reference clock signal generated by the reference oscillator is multiplied and divided to form the reference clock signal of the driving signal for driving the display element. Further, in the display unit, the ratio of the effective display area to the input video signal is changed by stopping the vertical or horizontal display position control at a constant interval.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an image display device 100 according to the first embodiment. This image display device 100 is composed of a camera block 110 using a CCD solid-state image pickup device and a display block 120 using a liquid crystal display device.

The camera block 110 has a CCD solid-state image pickup device 111 and a signal processing circuit 112 for processing an image pickup signal output from the CCD solid-state image pickup device 111 to obtain a video signal SV. Signal processing circuit 112
Then, processing such as edge enhancement, color reproduction correction, knee compression, and gamma correction is performed on the image pickup signal.

The camera block 110 includes a timing generator 113 for generating a CCD driving signal used in the CCD solid-state image pickup device 111 and a clock / synchronization signal for camera signal processing used in the signal processing circuit 112. A reference oscillator 114 for generating a reference clock signal CK in the camera block 110, and a clock / synchronization for generating a CCD driving signal used in the timing generator 113 based on the reference clock signal CK generated by the reference oscillator 114. It has a synchronization generator 115 for generating a clock / synchronization signal for processing a signal and a camera signal used in the signal processing circuit 112.

The display block 120 is a liquid crystal display element 12.
1 and a signal processing circuit 122 that performs processing such as amplification on the video signal SV output from the signal processing circuit 112 of the camera block 110 and supplies the processed signal to the liquid crystal display element 121.
It has a timing generator 123 that generates an LCD drive signal used in the liquid crystal display element 121 and an LCD signal processing clock / synchronization signal used in the signal processing circuit 122.

Here, the timing generator 123 is supplied with the reference clock signal CK generated by the reference oscillator 114 of the camera block 110, and the horizontal synchronization signal HD output from the synchronization generator 115 of the camera block 110. And the vertical synchronizing signal VD are supplied. And
The timing generator 123 generates an LCD drive signal and an LCD signal processing clock / sync signal based on the sync signals HD and VD and the reference clock signal CK.

The operation of the image display device 100 shown in FIG. 1 will be described.

In the camera block 110, the CCD
The image pickup signal output from the solid-state image pickup device 111 is supplied to a signal processing circuit 112 to be subjected to edge enhancement, color reproduction correction, knee compression, gamma correction, etc., and the signal processing circuit 112 outputs a video signal SV corresponding to a subject. can get. Further, in the display block 120, the video signal SV output from the camera block 110 is supplied to the signal processing circuit 122, and after being subjected to processing such as amplification, the liquid crystal display element 121.
The image corresponding to the subject is displayed on the liquid crystal display element 121.

According to the image display device 100 shown in FIG.
Since the reference clock signal CK generated by the reference oscillator 114 of the camera block 110 is also used in the display block 120, the display block 120 does not need to be provided with a reference oscillator having a PLL circuit. The circuit scale of the image display device 100 can be reduced. Further, the electromagnetic noise radiated can be reduced by the amount that the display block 120 is not provided with the reference oscillator.

In the image display device 100 shown in FIG. 1, since the reference clock signal CK generated by the reference oscillator 114 of the camera block 110 is also used in the display block 120, the driving frequency of the liquid crystal display element 121 is , Which is equal to the driving frequency of the CCD solid-state image sensor 111.

In the NTSC system, (a) 4fsc = 910fh (= 1) is used as the reference drive frequency currently used for driving the CCD solid-state image sensor of the video camera and signal processing.
4.31818MHz, fsc is color subcarrier frequency, fh
Is the horizontal frequency), (b) 858 fh (= 13.5 MHz) which is the reference frequency of the digital format, (c) 1
820 fh / 3 (= 9.54 MHz). On the other hand, the reference drive frequency used for driving the CCD solid-state image sensor of the PAL video camera and signal processing is
(A) 908 fh (14.1875 MHz), (b) 4
fsc = 910fh (= 17.734475 MHz),
(C) 86 which is the reference frequency of the digital format
4fh (= 13.5MHz), (c) 1816fh / 3
(= 9.458 MHz).

The number of horizontal display pixels of the liquid crystal display element 121 of the image display device 100 shown in FIG. 1 is determined by the formula (1) from the reference drive frequency and the horizontal effective display ratio. Horizontal display pixel number = reference drive frequency x (horizontal scanning period-horizontal retrace line period) x horizontal effective display ratio (1)

For example, NTSC system, reference drive frequency =
When 4 fsc and the horizontal effective display ratio = 90%, the number of horizontal display pixels is as shown in equation (2). Number of horizontal display pixels = 14.31818MHz x (63.556μs-10.9μs) x 0.9 = 678.5 ≈ 679 (2)

Therefore, the image display device 10 shown in FIG.
At 0, there is a disadvantage that the degree of freedom in selecting the number of horizontal display pixels of the liquid crystal display element 121 is small.

FIG. 2 shows an image display device 100A according to a second embodiment of the present invention. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The image display device 100A is composed of a camera block 110A using a CCD solid-state image pickup device and a display block 120A using a liquid crystal display device. The camera block 110A is configured similarly to the camera block 110 in the image display device 100 shown in FIG. 1, and includes a CCD solid-state image sensor 111, a signal processing circuit 112, and
It has a timing generator 113, a reference oscillator 114 and a synchronization generator 115.

The display block 120A is similar to the display block 120 in the image display device 100 shown in FIG.
It has a liquid crystal display element 121, a signal processing circuit 122, and a timing generator 123. Further, the display block 120A has a multiplication circuit 124 for multiplying the reference clock signal CK generated by the reference oscillator 114 of the camera block 110A by n (n is a positive integer), and the output signal of the multiplication circuit 124 is divided by m. (M is a positive integer) to obtain a reference clock signal CKa used in the display block 120A. In this case, the multiplying circuit 124 and the dividing circuit 125 constitute the reference clock signal forming means.

Here, the timing generator 123 is supplied with the reference clock signal CKa output from the frequency dividing circuit 125, and the horizontal synchronization signal HD and vertical synchronization output from the synchronization generator 115 of the camera block 110A. The signal VD is supplied. And the timing generator 1
At 23, an LCD driving signal and an LCD signal processing clock / synchronization signal are generated based on the synchronization signals HD and VD and the reference clock signal CKa.

In the image display device 100A shown in FIG. 2, as in the image display device 100 shown in FIG. 1, the video signal SV corresponding to the object is output from the camera block 110A and is displayed on the liquid crystal display element 121 of the display block 120A. Displays an image according to the video signal SV. According to this image display device 100A, it is not necessary to provide the reference oscillator having the PLL circuit in the display block 120A, and the image display device 1 is similar to the image display device 100 shown in FIG.
No. 00 circuit size can be reduced, and radiated electromagnetic noise can be reduced.

In the image display device 100A shown in FIG. 2, the number of horizontal display pixels of the liquid crystal display element 121 is n,
It depends on the value of m. For example, consider a case where the NTSC system, the standard drive frequency = 4 fsc, and the horizontal effective display ratio = 90%. When n = 1 and m = 1, the equation (2) is obtained. Then, when n = 2 and m = 3, it becomes as shown in the equation (3), and n = 4 and m = 3.
When it is, it becomes like Formula (4). Horizontal display pixel number = (14.31818MHz x 2/3) x (63.556μs-10.9μs) x 0.9 = 452.4≈452 ... (3) Horizontal display pixel number = (14.31818MHz x 4/3) x (63.556μs) −10.9 μs) × 0.9 = 904.7 ≒ 905 ・ ・ ・ (4)

As described above, the image display device 10 shown in FIG.
At 0A, the number of horizontal display pixels of the liquid crystal display element 121 can be changed by changing the values of n and m, and the degree of freedom in selecting the number of horizontal display pixels can be increased. The same applies when the order of the frequency multiplying circuit 124 and the frequency dividing circuit 125 shown in FIG. 2 is reversed.

As in the image display device 100A shown in FIG. 2, a method of forming the reference clock signal CKa used in the display block 120A from the reference clock signal CK by using the frequency multiplying circuit 124 and the frequency dividing circuit 125. Forming the reference clock signal CKa having the same frequency for driving the liquid crystal display element 121 having the same number of pixels in the horizontal direction from two reference clock signals CK having adjacent frequencies makes it difficult to realize a high multiplication circuit. From not practical.

For example, the frequency of the reference clock signal CK (reference clock frequency) is 4 fsc of the NTSC system.
= 14.31818MHz, 858fh = 13.5M
Consider Hz. In this case, if the liquid crystal display element 121 having a reference driving frequency of 13.5 MHz is used, when the reference clock frequency is 13.5 MHz, n = 1 and m = 1 and the reference clock of 13.5 MHz is used. Signal CKa, while the reference clock frequency is 1
When the frequency is 4.31818 MHz, for example, n = 19,
When m = 20, 13.6MHz (= 14.31818MHz × 19
The reference clock signal CKa of ÷ 20) is formed, but it is difficult to realize the 19-multiplier circuit.

By the way, FIG. 3 is a diagram for explaining an example of the scanning order of the liquid crystal display element 121. 3A shows the liquid crystal video signal LV corresponding to the video signal SV supplied to the liquid crystal display element 121, and FIG. 3B schematically shows the display pixels of the liquid crystal display element 121. In this example, the scanning is performed in the same direction as the scanning direction of the television system. In that case, CRT (cathode-ray tub
Instead of interlaced scanning as in e), scanning is performed from left to right and then from top to bottom.

In the conventional scanning method, A1 → A2 → every drive frequency period (pixel period) in the first one horizontal period period.
Display from left to right like A3 → ...
Up to n (n is the number of pixels in the horizontal direction) are displayed. In the next one horizontal cycle period, B1 → B2 → B3 →
... is displayed sequentially from left to right, and Bn is displayed. Hereinafter, similarly, the display is sequentially performed from the top to the bottom every one horizontal cycle period. When the video signal SV is of a television system compatible with interlaced scanning, the interlaced scanning → sequential scanning conversion is performed on the video signal SV in advance before use, or such conversion is not performed. The even field and the odd field are displayed at the same position.

FIG. 4 shows a concrete example of the structure of the liquid crystal display element 121. This example is of the active matrix drive type, and has 650 horizontal pixels and 220 vertical pixels.

TFTs (thin fil) as switching elements are provided corresponding to the respective display pixels arranged in a matrix.
m transistor) is arranged. The source of each TFT is
It is connected to the common electrode through a parallel circuit of the liquid crystal cell SCL and the storage capacitor CS. The common electrode terminal 11 is led out from the common electrode. The drains of the TFTs corresponding to the first to 650th horizontal display pixels are connected to the first to 650th signal electrodes extending in the vertical direction, respectively. Further, the gates of the TFTs corresponding to the first to 220th vertical display pixels are connected to the first to 220th scanning electrodes extending in the horizontal direction, respectively.

The liquid crystal display element 121 includes a horizontal shift register 12 for scanning in the horizontal direction, a vertical shift register 13 for scanning in the vertical direction, and field effect transistors T1 to T1 to select the horizontal scanning position. It has T650.

The horizontal shift register 12 has an input terminal 1
A start pulse HST (shown in FIG. 5A) is supplied from 2a, and shift clocks HCK1 and HCK2 (shown in FIG. 5B) whose phases are mutually inverted are supplied from input terminals 12b and 12c. As a result, the horizontal position selection pulse h1 to the output terminals of the 1st to 650th stages of the horizontal shift register 12 are sequentially set to the high level "H" in each driving frequency period after the start pulse HST is supplied.
h650 is obtained (illustrated in Figure 5C).

The vertical shift register 13 has an input terminal 1
A start pulse VST (shown in FIG. 6A) is supplied from 3a, and shift clocks VCK1 and VCK2 (shown in FIG. 6B) whose phases are mutually inverted are supplied from input terminals 13b and 13c. As a result, the vertical position selection pulses v1 to v220 that sequentially become high level "H" every horizontal period after the start pulse VST is supplied to the output terminals of the first to 220th stages of the vertical shift register 13.
Is obtained (illustrated in FIG. 6C).

First to 65th stages of the horizontal shift register 12
The zero-stage output terminals are connected to the gates of the transistors T1 to T650, respectively, and the sources of the transistors T1 to T650 are connected to the first to 650th signal electrodes extending in the vertical direction, respectively. And this transistor T1 ~
The drains of T650 are commonly connected to a video signal input terminal 14 to which the liquid crystal video signal LV is input. The output terminals of the first to 220th stages of the vertical shift register 13 are connected to the first to 220th scan electrodes extending in the horizontal direction, respectively.

In the above configuration, in each horizontal cycle period, the horizontal position at which the output terminals of the first to 650th stages of the horizontal shift register 12 sequentially become the high level "H" for each drive frequency cycle (pixel cycle). Since the selection pulses h1 to h650 are obtained and the transistors T1 to T650 are sequentially turned on for each drive frequency cycle, horizontal scanning is performed. In each vertical cycle period, the first shift of the vertical shift register 13 is performed.
The vertical position selection pulses v1 to v220 which sequentially become high level “H” are obtained at the output terminals of the second to 220th stages, and the TFTs corresponding to the first to 220th scanning electrodes are set to 1
Since it is sequentially turned on every horizontal cycle, scanning in the vertical direction is performed.

In this case, the video signal LV is applied to the liquid crystal cells SCL of the display pixels corresponding to the horizontal and vertical scanning positions, and the liquid crystal capacitance CLC and the storage capacitance CS are charged and discharged by the video signal LV. As a result, the video signal L
V is sampled and held for the non-scan period. Therefore, the voltage corresponding to the video signal LV is applied to the liquid crystal cell SCL of each display pixel of the liquid crystal display element 121, and the liquid crystal display element 121 can display an image by the video signal LV.

In such a scanning method, the above-mentioned (1)
In addition to the equation, the following equation (5) is established. Number of vertical display pixels = number of vertical effective scanning lines × vertical effective display ratio (5)

For example, in the case of NTSC system, vertical effective display ratio = 90%, even / odd field same position display,
The number of vertical display pixels is as shown in equation (6). Vertical display pixel number = 485/2 x 0.9 = 218.3 ≈ 218 (6)

Here, in the image display device 100 shown in FIG. 1, the frequency (reference clock frequency) of the reference clock signal CK generated by the reference oscillator 114 of the camera block 110 is 4fsc = 14.31818M in the NTSC system.
The case of Hz and 858fh = 13.5 MHz will be described. In this case, the liquid crystal display element 121 has 650 pixels in the horizontal direction and 220 pixels in the vertical direction, and its physical dimension aspect ratio is 4: 3.

In the conventional scanning method shown in FIG. 3, the reference clock frequencies are 14.31818 MHz and 13.5 M.
The horizontal effective display ratio and the vertical effective display ratio in the case of Hz are as shown in Expressions (7) to (10). (A) Horizontal effective display ratio 14.31818MHz: 650 ÷ (14.31818MHz × 52.656μs) = 0.862 ・ ・ ・ (7) 13.5MHz: 650 ÷ (13.5MHz × 52.656μs) = 0.914・ ・ ・ (8) (b) Vertical effective display ratio 14.31818MHz: 220 ÷ (485 ÷ 2) = 0.907 ・ ・ ・ (9) 13.5MHz ・ ・ ・ 220 ÷ (485 ÷ 2) = 0.907 (10)

In this case, as described above, the aspect ratio of the image displayed on the liquid crystal display element 121 having the physical dimension aspect ratio of 4: 3 is 4 × when the reference clock frequency is 13.5 MHz. (0.914 / 0.907) = 4.0
3: 3, almost correct display (0.907 / in the horizontal direction)
0.914 = 0.992 times the display), but when the reference clock frequency is 14.31818 MHz, 4 × (0.862 / 0.907) = 3.80:
3, which is 0.907 / 0.862 = 1.05 in the horizontal direction.
The display is doubled.

FIG. 7 shows an image display device 100B as a third embodiment of the present invention. 7, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The image display device 100B is composed of a camera block 110B using a CCD solid-state image pickup device and a display block 120B using a liquid crystal display device. The camera block 110B is configured similarly to the camera block 110 in the image display device 100 shown in FIG. 1, and includes a CCD solid-state image sensor 111, a signal processing circuit 112, and
It has a timing generator 113, a reference oscillator 114 and a synchronization generator 115.

The display block 120B includes the liquid crystal display element 1
21B and the signal processing circuit 11 of the camera block 110B.
The signal processing circuit 1 that performs processing such as amplification on the video signal SV output from the device 2 and supplies it to the liquid crystal display element 121B.
22 and a timing generator 123B that generates an LCD driving signal used in the liquid crystal display element 121B and a clock / synchronization signal for LCD signal processing used in the signal processing circuit 122. The liquid crystal display element 121B has 650 pixels in the horizontal direction and 220 pixels in the vertical direction, and its physical dimension aspect ratio is 4: 3 × (0.907 /
0.862) = 3.16. The liquid crystal display element 121B is different only in physical dimension aspect ratio.
Other configurations are similar to those of the liquid crystal display element 121 shown in FIG.

The reference clock signal CK generated by the reference oscillator 114 of the camera block 110B is supplied to the timing generator 123B, and the camera block 1 is also supplied.
The horizontal sync signal HD and the vertical sync signal VD output from the sync generator 115 of 10B are supplied. Then, the timing generator 123B generates an LCD drive signal and a clock / sync signal for LCD signal processing based on the sync signals HD and VD and the reference clock signal CK.

In the image display device 100B shown in FIG. 7, the frequency (reference clock frequency) of the reference clock signal CK generated by the reference oscillator 114 of the camera block 110B is 14.31818 MHz or 13.5 M.
It is set to Hz. The mode control signal MDC is supplied to the timing generator 123B. This mode control signal MD
C has, for example, a reference clock frequency of 14.31818.
When it is MHz, it is set to high level "H", and when the reference clock signal is 13.5 MHz, it is set to low level "L".

As a result, when the reference clock frequency is 14.31818 MHz, the LCD drive signal generated by the timing generator 123B uses the same scanning method (see FIG. 3) as the conventional one in the liquid crystal display element 121B. To be executed, while the reference clock frequency is 13.5 MH
In the case of z, the liquid crystal display element 121B executes thinning-out scanning for thinning out the video signal LV at a rate of 1 horizontal period in 20 horizontal periods.

That is, the reference clock frequency is 14.3
Timing generator 123B if 1818 MHz
The shift clocks VCK1 and VCK2 supplied to the liquid crystal display element 121B are formed as shown in FIG. 6B. However, when the reference clock frequency is 13.5 MHz,
The shift clocks VCK1 and VCK2 are formed as shown in FIG. 8B. FIG. 8A shows a start pulse VST.
Is shown.

As a result, the output terminals of the first to 220th stages of the vertical shift register 13 (see FIG. 4) are connected to the output terminals of FIG.
Vertical position selection pulses v1 to v220 are obtained as shown in
Thinning-out scanning for thinning out the video signal LV is realized at a rate of one horizontal period in every 20 horizontal periods. FIG. 9 shows a state of this thinning scanning. FIG. 9A shows the video signal LV supplied to the liquid crystal display element 121B, and FIG. 9B schematically shows the display pixels of the liquid crystal display element 121B.

In the image display device 100B shown in FIG. 7, as in the image display device 100 shown in FIG. 1, the video signal SV corresponding to the subject is output from the camera block 110B, and the liquid crystal display element 121B of the display block 120B is output.
An image based on the video signal SV is displayed on. According to this image display device 100B, the display block 120B
It is not necessary to provide a reference oscillator having a PLL circuit in
Similar to the image display device 100 shown in FIG. 1, the circuit scale of the image display device 100B can be reduced, and the electromagnetic wave noise radiated can be reduced.

Further, in the image display device 100B shown in FIG. 7, when the reference clock frequency is 14.31818 MHz, vertical thinning scanning is not performed, so that the physical dimension aspect ratio is 4: 3.16. Liquid crystal display element 1
The aspect ratio of the image displayed on 21B is 4 × (0.862
/0.907)=3.80:3, and thus 4: 3.16. In this case, the aspect ratio of the image is the liquid crystal display element 121B.
Since the physical size and aspect ratio of the liquid crystal display element 1
An image by the video signal SV is displayed on 21B with the correct aspect ratio.

On the other hand, in the image display device 100B shown in FIG. 7, when the reference clock frequency is 13.5 MHz, vertical thinning-out scanning is performed at a rate of one horizontal period in 20 horizontal periods, and therefore vertical pixel When the number is 220, it means that 220 × (20/19) = 231.6≈232 horizontal period images are displayed. At this time,
The vertical effective display ratio is 232 / (485/2) =
It becomes 0.957, and the physical dimension aspect ratio is 4: 3.16.
The aspect ratio of the image displayed on the liquid crystal display element 121B is 4 × (0.914 / 0.957) = 4: 3.14. Also in this case, the aspect ratio of the image is the liquid crystal display element 121.
Since the physical dimension of B is almost the same as the aspect ratio, an image based on the video signal SV is displayed on the liquid crystal display element 121B with a substantially correct aspect ratio.

FIG. 10 shows a liquid crystal display element 121B for the NTSC system effective display area (area surrounded by an outer frame).
Shows the relationship between the areas actually displayed (hatched areas). 10A shows the case where the reference clock frequency is 13.5 MHz, and FIG. 10B shows the case where the reference clock frequency is 1.
The case of 4.31818 MHz is shown.

As described above, the image display device 10 shown in FIG.
At 0C, the reference clock frequency is 14.31818MH
Whether it is z or 13.5 MHz, the physical size and aspect ratio is 4: 3.16, and the number of horizontal pixels is 65.
0, liquid crystal display element 121 having 220 vertical pixels
On B, an image based on the video signal SV can be displayed well. In this case, it is not realized by using the above-mentioned high multiplication circuit, and there is an advantage that it can be realized easily. Although detailed description is omitted, by changing the thinning rate, the liquid crystal display element 1 can be used even at other reference clock frequencies.
It is obvious that the image by the video signal SV can be satisfactorily displayed on 21B.

Further, in the image display device 100B shown in FIG. 7, the display block 1 uses the reference clock signal CK generated by the reference oscillator 114 of the camera block 110B.
The timing generator 123B of 20 generates an LCD driving signal and a clock / synchronization signal for LCD signal processing. Each pixel portion of the video signal SV and the liquid crystal display element 1 are generated.
There is always a constant phase relationship with the 21 display pixels. Therefore, there is an advantage that the display image such as characters is not affected by the horizontal display position or is hardly affected by the horizontal display position. It should be noted that this effect can be obtained similarly in the image display device 100 shown in FIG. 1 and the image display device 100C shown in FIG.

FIG. 11 shows an image display device 100C as a fourth embodiment of the present invention. This FIG.
In FIG. 3, the same reference numerals are given to the portions corresponding to those in FIG.

The image display device 100C comprises a camera block 110C using a CCD solid-state image pickup device and a display block 120C using a liquid crystal display device. The camera block 110C is configured similarly to the camera block 110 in the image display device 100 shown in FIG. 1, and includes a CCD solid-state image sensor 111, a signal processing circuit 112,
It has a timing generator 113, a reference oscillator 114 and a synchronization generator 115.

The display block 120C is the liquid crystal display element 1
21 and the signal processing circuit 112 of the camera block 110C
The signal processing circuit 122 that performs processing such as amplification on the video signal SV output from the device and supplies it to the liquid crystal display element 121.
And a timing generator 123 for generating an LCD driving signal used in the liquid crystal display element 121 and an LCD signal processing clock / synchronization signal used in the signal processing circuit 122.
C. The liquid crystal display element 121 has 650 horizontal pixels and 220 vertical pixels, and has a physical dimension aspect ratio of 4: 3, and is configured as shown in FIG.

The reference clock signal CK generated by the reference oscillator 114 of the camera block 110C is supplied to the timing generator 123C, and at the same time, the camera block 1
The horizontal sync signal HD and the vertical sync signal VD output from the sync generator 115 of 10C are supplied. Then, the timing generator 123C generates an LCD drive signal and a clock / sync signal for LCD signal processing based on the sync signals HD and VD and the reference clock signal CK.

In the image display device 100C shown in FIG. 11, the frequency (reference clock frequency) of the reference clock signal CK generated by the reference oscillator 114 of the camera block 110C is 14.31818 MHz or 13.5 M.
It is set to Hz. A mode control signal MDC is supplied to the timing generator 123C. This mode control signal MD
C has, for example, a reference clock frequency of 14.31818.
When it is MHz, it is set to high level "H", and when the reference clock signal is 13.5 MHz, it is set to low level "L".

As a result, when the reference clock frequency is 13.5 MHz, the LCD drive signal generated by the timing generator 123C uses the same scanning method (see FIG. 3) as the conventional one in the liquid crystal display element 121. And the reference clock frequency is 14.31818 MHz.
In this case, the liquid crystal display element 121 executes thinning-out scanning for thinning out the video signal LV at a rate of 1 pixel period in 20 pixel periods.

That is, the reference clock frequency is 13.5.
In case of MHz, the shift clock HCK1, which is supplied from the timing generator 123C to the liquid crystal display element 121,
HCK2 is formed as shown in FIG. 5B. When the reference clock frequency is 14.31818 MHz, the shift clocks HCK1 and HCK2 are formed as shown in FIG. 12B. FIG. 12A shows a start pulse HST.
Is shown.

Thus, the output terminals of the first to 650th stages of the horizontal shift register 12 (see FIG. 4) are connected to the output terminals of FIG.
As shown in C, the vertical position selection pulses h1 to h650 are obtained, and thinning-out scanning for thinning out the video signal LV is realized at a rate of one pixel period in 20 pixel periods. FIG. 13 shows a state of this thinning scanning. 13A and 13B show the video signal LV supplied to the liquid crystal display element 121.
C schematically shows the display pixel of the liquid crystal display element 121.

In the image display device 100C shown in FIG. 11, as in the image display device 100 shown in FIG. 1, the video signal SV corresponding to the subject is output from the camera block 110C, and the liquid crystal display element 121 of the display block 120C.
An image based on the video signal SV is displayed on. According to the image display device 100C, the display block 120C
It is not necessary to provide a reference oscillator having a PLL circuit in
Similar to the image display device 100 shown in FIG. 1, the circuit scale of the image display device 100C can be reduced, and the radiated electromagnetic noise can be reduced.

The image display device 100C shown in FIG.
Then, when the reference clock frequency is 13.5 MHz, vertical thinning scanning is not performed, so that the aspect ratio of the image displayed on the liquid crystal display element 121 having a physical dimension aspect ratio of 4: 3 is: 4 × (0.914 / 0.907) =
The ratio becomes 4.03: 3, and an image based on the video signal SV is displayed on the liquid crystal display element 121 with a substantially correct aspect ratio.

On the other hand, the image display device 100C shown in FIG.
Then, when the reference clock frequency is 14.31818 MHz, horizontal thinning-out scanning is performed at a rate of 1 pixel period in 20 pixel periods, so that the number of horizontal pixels is 65.
In the case of 0, 650 × (20/19) = 684.2≈68
This means that an image for 4 pixel periods is being displayed. At this time, the horizontal effective display ratio is 684 / (14.31).
818 MHz × 52.656 μs) = 0.907, and the liquid crystal display element 1 has a physical dimension aspect ratio of 4: 3.
The aspect ratio of the image displayed on 21 is 4 × (0.907 /
0.907) = 4: 3. Also in this case, since the aspect ratio of the video matches the physical dimension aspect ratio of the liquid crystal display element 121, an image based on the video signal SV is displayed on the liquid crystal display element 121 with the correct aspect ratio.

FIG. 14 shows the relationship between the effective display area of NTSC system (area surrounded by an outer frame) and the area actually displayed on the liquid crystal display element 121 (hatched area). FIG. 14A shows the case where the reference clock frequency is 13.5 MHz, and FIG. 14B shows the case where the reference clock frequency is 1.
The case of 4.31818 MHz is shown.

Thus, the image display device 10 shown in FIG.
At 0C, the reference clock frequency is 14.31818MH
An image generated by the video signal SV is displayed on the liquid crystal display element 121 having a physical dimension aspect ratio of 4: 3, a horizontal display pixel number of 650, and a vertical display pixel number of 220 regardless of whether z or 13.5 MHz. Can be displayed well. In this case, it is not realized by using the above-mentioned high multiplication circuit, and there is an advantage that it can be realized easily. Although detailed description is omitted, it is clear that by changing the thinning-out ratio, an image based on the video signal SV can be satisfactorily displayed on the liquid crystal display element 121 even at other reference clock frequencies.

Although not described in the above embodiment, the display pixels of the liquid crystal display element are arranged so as to be displaced by 0.5 pixel for each scanning line according to the structure of the color filter, that is, a so-called delta liquid crystal. It goes without saying that the present invention can be similarly applied to the display element.

Further, in the above-mentioned embodiment, the liquid crystal display element is used as the display element, but the present invention is not limited to the other display elements, for example, LED (Light Emitting).
A flat panel display such as a diode) display element, an EL (Electro Luminescence) display element, or a plasma display element may be used.

In the above embodiment, the reference oscillator 114 is provided in the camera block.
The reference oscillator may be provided in the display block.
As a result, the circuit scale of the camera block can be reduced.

Further, in the above-mentioned embodiments, the video part for outputting the video signal is the camera block. However, this video part outputs the video signal, for example, a video tape recorder, a tuner, a camera. It may be a body-type video tape recorder, a tuner, a computer, a video disc device, or the like.

[0085]

According to the present invention, the only reference oscillator for generating the reference clock signal used in the video section and the display section is provided, and the circuit scale can be reduced and the radiated electromagnetic noise can be reduced. It can be reduced.

Further, by using the reference clock signal of the same frequency in the video section and the display section, each pixel portion of the video signal and the display pixel of the display element always have a constant phase relationship, and the display pixel such as a character is displayed. There is a benefit that the horizontal display position is not affected or is less affected.

Further, by multiplying and dividing the reference clock signal generated by the reference oscillator to form the reference clock signal of the drive signal for driving the display element of the display section, the number of horizontal display pixels of the display element is increased. The degree of freedom of choice can be increased.

Further, the control of the display position of the display element in the vertical direction or the horizontal direction is stopped at a constant interval to change the ratio of the effective display area to the input video signal, thereby using two reference clock signals having frequencies close to each other. Then, it is possible to easily display a good image on a display element having the same number of pixels in the horizontal direction without using a high multiplication circuit or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image display device as a first embodiment.

FIG. 2 is a block diagram showing an image display device as a second embodiment.

FIG. 3 is a diagram showing an example of a scanning order of liquid crystal display elements.

FIG. 4 is a diagram showing a specific configuration example of a liquid crystal display element.

FIG. 5 is a timing chart for explaining the operation of a horizontal shift register that constitutes a liquid crystal display element.

FIG. 6 is a timing chart for explaining the operation of a vertical shift register that constitutes a liquid crystal display element.

FIG. 7 is a block diagram showing an image display device as a third embodiment.

FIG. 8 is a timing chart for explaining an operation (vertical thinning scanning) of a vertical shift register which constitutes the liquid crystal display element according to the third embodiment.

FIG. 9 is a diagram for explaining thinning-out scanning in the vertical direction in a liquid crystal display element.

FIG. 10 is a diagram showing a relationship between an NTSC effective display area and a display area of a display element according to a third embodiment.

FIG. 11 is a block diagram showing an image display device as a fourth embodiment.

FIG. 12 is a timing chart for explaining the operation (horizontal thinning scanning) of the horizontal shift register that constitutes the liquid crystal display element according to the fourth embodiment.

FIG. 13 is a diagram for explaining thinning scanning in the horizontal direction in the liquid crystal display element.

FIG. 14 is a diagram showing a relationship between an NTSC effective display area and a display area of a display element in the fourth embodiment.

FIG. 15 is a block diagram showing an example of a conventional image display device.

[Explanation of symbols]

100, 100A, 100B, 100C ... Image display device, 110, 110A, 110B, 110C ... Camera block, 111 ... CCD solid-state image sensor, 11
2 ... Signal processing circuit, 113 ... Timing generator, 114 ... Reference oscillator, 115 ... Synchronization generator, 120, 120A, 120B, 120C ... Display block, 121, 121B ... Liquid crystal display device, 12
2 ... Signal processing circuit, 123, 123B, 123C
..Timing generator, 124 ... Multiplier circuit, 125
... Dividing circuits

Claims (14)

[Claims] 1. An image display device comprising: a video section for outputting a video signal; and a display section for displaying an image based on the video signal output from the video section on a display element. An image display device comprising a single reference oscillator for generating a reference clock signal to be used in the unit. 2. The image display device according to claim 1, wherein the reference oscillator is arranged in the video section. 3. The image display device according to claim 1, wherein the reference oscillator is arranged in the display section. 4. The video section has timing signal generating means for generating a timing signal for signal processing based on the reference clock signal generated by the reference oscillator, and the display section includes the display element. Drive signal generating means for generating a drive signal for driving, wherein the drive signal generating means of the display section generates the reference clock signal generated by the reference oscillator and the timing signal generating means by the timing signal generating means. The image display device according to claim 2, wherein the drive signal is generated based on a horizontal and vertical synchronizing signal that is generated. 5. The image display device according to claim 1, wherein the video unit is a video camera. 6. The image display device according to claim 1, wherein the video section is a video tape recorder. 7. The image display device according to claim 1, wherein the video section is a camera-integrated video tape recorder. 8. The image display device according to claim 1, wherein the video unit is a video disc device. 9. The image display device according to claim 1, wherein the video unit is a computer. 10. The image display device according to claim 1, wherein the display section uses a flat panel display as a display element. 11. The image display device according to claim 10, wherein the display section uses a liquid crystal display element as a display element. 12. The reference clock signal, wherein the display section forms a reference clock signal of a drive signal for driving the display element by multiplying and dividing the reference clock signal generated by the reference oscillator. The image display device according to claim 2, further comprising a forming unit. 13. The display unit comprises display control means for changing the ratio of the effective display area to the input video signal by stopping the display position control in the vertical direction at regular intervals. The image display device according to. 14. The display unit comprises display control means for changing the ratio of the effective display area to the input video signal by stopping the horizontal display position control at a constant interval. The image display device according to.