JPH10239661A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption and to sufficiently reduce radiation by providing a low-pass filter which is supplied with a midpoint potential of an inverted driving voltage. SOLUTION: At the midpoint of a floating source voltage EF, a lag lead type low-pass filter 70 which serves to prevent oscillation of negative feedback operation of an operational amplifier 51 is inserted to attenuate voltage variation of the midpoint potential at the time of anode inversion driving, so that variation in the midpoint voltage of the floating source voltage EF is not corrected abruptly. In this case, the output potential of the operational amplifier 51 is varied in synchronism with an offset voltage and the midpoint voltage of a common inversion driving source voltage for the operational amplifier 51 becomes as high as the output voltage of the operational amplifier 51, so that even when the offset voltage and floating source voltage are varied, the output voltage of the operational amplifier 51 stays at the midpoint potential between the upper and lower voltages of a floating power source without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a liquid crystal display device which forms an image by an active matrix system and which is suitable as a device using, for example, a plasma addressed liquid crystal display device.

[0002]

2. Description of the Related Art Recently, in order to obtain a more powerful image while taking into account, for example, an installation space that can be secured in a home, a large and thin television receiver, a rear projection, and the like have been proposed. 2. Description of the Related Art Projector devices have become widespread.

[0003] These television receivers and rear projection type projector devices have been considerably thinner than past ones with the advance of technology, but in the case of television receivers, for example, There is a limit to the reduction in thickness due to the depth of the CRT and, in the case of a projector device, structural conditions such as the angle at which the projection lens is installed.

In addition, a TFT (Thin Film Tr)
A display device using a liquid crystal panel can be configured to be thinner than the above-described television receiver or projector device. However, in order to make the display device larger, a TFT formed by IC technology is used.
With the increase in the number of devices, a more precise manufacturing technique is required, and the manufacturing yield is lowered, so that the cost becomes extremely high.

[0005] Therefore, a plasma-addressed liquid crystal element (Plasma Addressed) capable of forming a large screen equivalent to that of a television receiver or a projector device and realizing a thickness as thin as a liquid crystal display can be realized.
A liquid crystal display device using Liquid Crystal (hereinafter abbreviated as PALC) for a display portion has been considered.

A display device using this plasma-addressed liquid crystal element makes use of the advantages of a TFT liquid crystal display device of high luminance and high contrast, and also has a PDP (Plasm).
aDisplay Panel) technology makes it possible to realize a large screen.

FIG. 8 is a perspective view showing a part of the structure of a display device using PALC as a display unit, and FIG.
Is shown in cross section.

[0008] As shown in FIG.
The LC1 is sandwiched between two polarizing filters 3 and 4 whose polarization axes are orthogonal to each other, and the backlight source 2 is arranged on the back of the PALC1. The PALC 1 transmits an image by selectively transmitting a light beam emitted from a backlight light source 2 disposed on the rear surface thereof by an active matrix method in combination with the operation of the two polarizing filters 3 and 4. It has a structure as a transmission type display element to be formed.

The structure of the PALC 1 is as shown in FIG. 9 and a plasma substrate (back glass) 5 provided on the back side.
, For example, a large number of scanning grooves 7, 7, 7,..., Which are partitioned into a hollow shape in the horizontal direction by a large number of partition walls (ribs) 6, 6, 6,.・ Is formed. The partition walls are provided at regular intervals in the vertical direction of the display screen. The scanning grooves 7, 7, 7,... May be formed as cut grooves.

In each of the scanning grooves 7, an anode electrode 8 and a cathode electrode 9 are formed as a pair so as to be parallel to each other. Scanning grooves 7, 7, 7,
.. Constitute a horizontal scanning line corresponding to an effective screen of PALC1. Therefore, the scanning grooves 7 are formed by the number of scanning lines, for example, about 480.

A thin glass substrate constituting an insulating layer 10 is disposed in front of the plasma substrate 5 with the partition walls 6, 6, 6,... Interposed therebetween.
Each of the scanning grooves 7, 7, 7. Are filled with a rare gas mixture such as helium gas as a plasma gas.

A scanning voltage of, for example, a negative pulse of about -300 V is applied to the cathode electrode 9 from a driver circuit for plasma discharge not shown in FIG.
As will be described in detail later, plasma discharge is generated between the anode electrode 8 and the cathode electrode 9 by a plasma pulse supplied at a predetermined timing.

Due to the plasma discharge, the plasma gas is ionized in the scanning groove 7 and an electric conductor (plasma channel) is formed in the scanning groove 7 until the plasma particles are completely extinguished. The same selection operation (strobe) can be performed.

On the front side of the insulating layer 10 of the thin glass substrate, a liquid crystal layer 11 for forming pixels in a matrix is provided.
Is provided. Then, on the front side of the liquid crystal layer 11,
Striped color filter layers 12R, 12G, and 12B corresponding to each color of R (red), G (green), and B (blue)
With the longitudinal direction of the stripe as the vertical direction, 12R, 12
G, 12B, 12R, 12G, 12B,... Are provided so that three color filter layers are sequentially and repeatedly arranged in the horizontal direction.

The color filter layers 12R, 1R,
Striped transparent electrodes 13R, 13G, and 13B are repeatedly arranged and provided so as to overlap with each of 2G and 12B. Transparent electrodes 13R, 13G, 13B
Is composed of, for example, an ITO thin film layer.

The longitudinal direction of the color filter layer and the stripe of the transparent electrode is the vertical direction, and the scanning grooves 7, 7, 7
... is a direction orthogonal to. A set of color filter layers 12R, 12G, and 12B for three primary colors and a set of transparent electrodes 13R, 13G, and 13B, and scanning grooves 7, 7, 7,.
.. Are configured to be one display pixel. As described later, the transparent electrode 13 forming one pixel
Each of R, 13G, and 13B is supplied with a signal voltage corresponding to the data of each color component of R (red), G (green), and B (blue) that constitute one pixel data.

In the following description, the color filter layer 12 and the transparent electrode 13 except for the suffix indicate the color filter layer and the transparent electrode in units of one pixel.

In this display device, the video signal of the horizontal line is supplied to each of the transparent electrodes 13 for each horizontal section, and the plasma gas in the scanning groove 7 is sequentially discharged in the vertical direction. Thereby, the data of the pixel corresponding to the video signal is applied to the liquid crystal as the display pixel at the portion where the transparent electrode 13 (G, B, R) and the scanning groove 7 intersect. Due to the application of the pixel data, the transmittance of the light emitted from the backlight light source 2 differs for each color light component of each pixel according to the pixel data, and a color image is displayed. .

That is, as shown in FIG.
The polarization filters 3 and 4 are disposed on the incident side and the exit side of the light emitting device 1, respectively.
By sequentially moving the scanning groove 7 for generating plasma discharge in the vertical direction and applying a video signal to the transparent electrode,
The transmission amount of polarized light can be controlled in pixel units, and a color image can be obtained by the same principle as that of a normal TFT liquid crystal display device.

Next, the operation of forming an image for one field on the display screen will be described in further detail with reference to FIGS. FIG. 10A is a diagram for explaining a switching operation by a plasma channel, and FIG. 10A shows a switch SW for convenience.

As described above, when plasma discharge is performed by applying, for example, −300 V to the cathode electrode 9 as a power source, a plasma channel is formed in the scanning groove 7. This plasma channel becomes a virtual electrode and the transparent electrode 13 is formed.
A video signal voltage is applied between the gate electrode and the anode electrode 8. That is, in FIG. 10A, the switch SW is turned on.

When a plasma channel is formed by the plasma discharge, as shown in FIG.
The inside of the scanning groove 7 becomes conductive, which can be described as the operation of the FET switching element 100 as shown in FIG.

By the switching operation by the plasma channel, the insulating layer 1 made of the thin glass substrate shown in FIG.
A virtual electrode is generated on the inner surface of the zero. Here, when a video signal voltage for driving a pixel is applied to the transparent electrode 13, the liquid crystal layer 11 at the intersection of the scanning groove 7 and the transparent electrode 13 during plasma discharge is formed.
A drive voltage (video signal voltage) is applied to each pixel (for one line).

Therefore, the scanning is performed so that the plasma discharge is sequentially generated in the scanning grooves 7 of the first to 480th lines, and in synchronization with this, the first to 480th lines are applied to the transparent electrode 13. By applying a video signal voltage to the pixel of the eye (for one line), an image for one field can be displayed.

That is, after selecting which line of the image is to be formed by the plasma channel, the transparent electrode 1
By applying a drive voltage for forming an image of the line to 3 (13R, 13G, 13B), selective scanning of lines constituting one field is realized. At this time, the light beam from the backlight light source 2 passes through the color filter layer 12 (the filter layers 12R, 12G, and 12B), so that a color image can be displayed.

By forming a display device using the PALC1 capable of forming a color image with the above-described structure and operation principle for a display portion, a thin, lightweight, large-screen display device can be formed. become able to.

[0027]

However, when a liquid crystal is driven by always applying a DC voltage in one direction, the liquid crystal is also ionized fine particles. Occurs. Therefore, conventionally, the polarity of the DC voltage applied to the liquid crystal layer is inverted every horizontal scanning line or every field to prevent the liquid crystal molecules from shifting, and to prevent the image sticking phenomenon. Driving a liquid crystal has been performed.

As described above, in order to drive the liquid crystal by inverting the polarity of the applied DC voltage, the potential of the virtual electrode on the plasma channel side, in this case, the anode electrode 8 is set to zero, and the potential of the transparent electrode 13 is reduced. In principle, a method of inverting the polarity of the applied voltage to invert the polarity of the drive voltage applied to the liquid crystal layer 11 can be considered. However, in the case of this method, it is necessary to use positive and negative power supplies, and the peak-to-peak value of the drive voltage applied to the transparent electrode 13 is twice the peak-to-peak value of the signal voltage. For example, ± 7
When driving with 0V video data, about 140Vpp
(Vpp is a peak-to-peak value). Therefore, there is a problem that the semiconductor process becomes expensive and the power consumption increases.

Therefore, instead of inverting only the drive voltage applied to the transparent electrode 13, as shown in FIG. 11A, the drive voltage of the transparent electrode 13 is also inverted by inverting the voltage applied to the anode electrode 8. Can be inverted only with respect to the midpoint voltage, so that it can be generated only by a one-way (positive direction) power supply, and the peak-to-peak value of the drive voltage applied to the transparent electrode 13 is determined by the signal voltage peak·
A method of reducing power consumption in a manner almost equal to the two-peak value is used.

That is, in this method, in order to reduce the cost of the driver for driving the transparent electrode 13, a column driver using only a one-way (eg, positive) power supply is used.
The inversion voltage for inversion driving is such that all the anode electrodes 8 are used as a common (common) terminal and are driven by a rectangular wave, which is called a common anode inversion driving method.
According to the common anode inversion driving method, the common anode potential is replaced with 0 V, and based on this, as shown in FIG. 11B, the voltage for driving the transparent electrode 13 is positive and negative with 0 V as the center. It is equivalent to driving by reversing the polarity of.

That is, in this common anode inversion driving method, when writing a black signal of, for example, ± 70 V, as shown in FIG. Direct, transparent electrode 13
And a voltage of −10 V is applied to the common electrode (corresponding to the common anode electrode in the case of PALC1).

In the next line, for inversion driving, it is necessary to write a black signal of -70 V, which is an inverted version of this. In the common anode inversion driving method, first,
The video signal is converted to a 0 V video signal inverted at a midpoint potential of 30 V level and applied to the transparent electrode 13. at the same time,
When the inverted signal is being applied, a voltage of +70 V is applied to the common anode electrode.

Thus, when the electrode potential of the common anode is considered as a reference, as shown in FIG. 11B, the driving waveform is relatively ± 70 V, and the driving waveform is ± 70 Vpp.
Is equivalent to performing the direct drive of In addition, in this case, a driving voltage of 60 Vpp is sufficient for the video signal.

In a display device using the PALC 1 as a display unit as shown in FIG. 9, the relationship between the voltage applied to the transparent electrode 13 (ITO drive voltage) and the transmittance (hereinafter referred to as VT)
FIG. 12 shows a curve as shown in FIG. 12. In an actual display, a non-saturation region in a range of about 10 V to 70 V is used. When a drive voltage in this region is obtained, a bias voltage of about 10 V is required. Therefore, as described above, by applying -10 V as a common voltage when driving a positive voltage and applying 70 V when driving an inversion voltage, The driving voltage of 0V to 60V on the positive side is equivalent to the driving waveform of 10V to 70V, and the driving voltage of 0V to -60V on the inversion side is equivalent to the driving waveform of -10V to -70V, so that the non-saturated display region of the liquid crystal can be used efficiently. Will be possible. In this case, -10V and +70
The common anode inversion voltage of V is alternately switched every horizontal cycle and applied to the common anode electrode.

Actually, in the VT characteristic of the liquid crystal, since the saturation characteristic on the low voltage side fluctuates due to manufacturing variations of the display element, the adjustment range of the bias voltage of 10 V is as follows.
A width of about 0 to 20 V is required, and the variable voltage of the common voltage is, as shown in FIG. 11A, a variable width of 0 V to −20 V on the negative side and a tracking voltage of 60 V to 80 V on the positive side. A variable width with good characteristics is required.

That is, when the amplitudes of the positive and negative common voltages are adjusted, since the drive voltage of the liquid crystal needs to have accurate symmetry, the midpoint between the positive and negative common voltages is required. Must be equal to the midpoint potential of the driving voltage of the liquid crystal, 30 V, as shown in FIG.

In order to realize this requirement, a midpoint voltage matching circuit as shown in FIG. 13 has been conventionally used. In the case of this example, for example, (60 + 2α) Vp is floated to generate a power supply voltage to be supplied to the common anode electrode.
A power supply voltage EF of p is prepared. Here, α is a bias voltage adjustment voltage, and α = 0 to 20V.

The upper potential Eu of the power supply voltage EF of the floating power supply is applied to the common anode electrode through a switch circuit composed of an N-type MOS transistor 56 in this example. The lower potential Ed is a P-type M in this example.
It is configured to be applied to the common anode electrode through a switch circuit including the OS transistor 57.

Then, M constituting these switch circuits
The OS transistors 56 and 57 cause the pulse INV to be inverted every one horizontal section (shown as 1H in the figure), thereby causing 1
By being turned on alternately in each horizontal section, the upper potential Eu and the lower potential Ed of the floating power supply are alternately applied to the common anode electrode every horizontal section.

The upper potential Eu and the lower potential Ed are:
As described below, the midpoint voltage of the floating power supply voltage EF is determined so as to be equal to the midpoint potential of the driving voltage of the liquid crystal.

That is, the midpoint voltage of the floating power supply voltage EF divided by the resistors 52 and 53 is supplied to one input terminal of the operational amplifier 51, and a resistor is connected to the other input terminal of the operational amplifier 51. 61, 62, 6
The midpoint voltage of the transparent electrode driving power supply voltage Vdc divided at 3 is supplied.

The comparison error voltage obtained at the output terminal of the operational amplifier 51 is determined by the NPN transistor 54 and the PNP
The common supply is supplied to the base of the transistor 55. These NPN transistor 54 and PNP transistor 55
Are connected in common, and the connection point is grounded. The upper potential Eu of the floating power supply is applied to the collector of the NPN transistor 54,
The lower potential Ed of the floating power supply is applied to the collector of the NP transistor 55.

As a result of the above configuration, the operational amplifier 51 compares the two midpoint voltages supplied to the one and the other input terminals, and drives the NPN transistor 54 and the PNP transistor 55 with the comparison error voltage. .
Since the emitters of the NPN transistor 54 and the PNP transistor 55 are commonly connected and the connection point is grounded, the midpoint potential of the floating power supply voltage EF and the midpoint potential of the transparent electrode driving power supply voltage Vdc The negative feedback operation of the operational amplifier 51 is performed so that the potentials become equal, and the upper potential Eu and the lower potential Ed of the floating power supply are determined.

That is, since the relationship of (Eu−Ed) / 2 = 30 {Eu− (60 + 2α−Eu)} / 2 = 30 ΔEu = 60 + α is established, as shown in FIG. Voltage (60 + 2α)
The positive potential Eu of Vpp is determined to be (60 + α) V, and the negative potential Ed is a potential of −αV. The upper (positive side) and lower (negative side) voltages of the floating power
As described above, the two MOS transistors 56 and 57
By using a switching element such as this to alternately switch every horizontal section, a voltage required for common anode inversion driving can be obtained.

In the above description, the offset with respect to the midpoint potential of the transparent electrode driving power supply voltage Vdc has been described as zero, but in practice, the offset voltage VOF
F needs to be considered.

That is, the potential of the lower portion of the insulating layer 10 (thin glass) in the plasma discharge channel is substantially equal to the potential on the anode side, that is, the ground potential. +20
In some cases, the offset voltage may be equivalent to V.

The offset voltage is, for example, -10V,
PAL when the bias voltage (α) is 10 V
FIG. 15 shows the relationship between the transmittance of C1 and the drive voltage. When there is no offset voltage, driving with a symmetrical waveform of ± 10 to ± 70 V may be used. However, when there is an offset voltage of −10 V, as shown by a dotted line in FIG. The positive side requires a drive voltage of 0V to 60V, and the negative side requires a drive voltage of -20V to -80V.

Therefore, as shown in FIGS. 13 and 14, the resistor 62 is configured as a variable resistor, and the resistance value of the variable resistor 62 is adjusted so that the midpoint of the power supply voltage Vdc for driving the transparent electrode. In this example, the potential can be varied by ± 20 V. And, this variable resistor 62
Is supplied to one input terminal of the operational amplifier 51 to operate the negative feedback circuit of the operational amplifier 51 so as to match the midpoint potential of the floating power supply as described above. As a result, the offset voltage is also generated for the inversion voltage supplied to the common anode electrode.

FIG. 14 shows the offset voltage VOFF,
6 shows the relationship with the inversion voltage supplied to the common anode electrode. By adjusting the variable resistor 62, the offset voltage VOFF can be controlled to the positive side and the negative side.

However, in the conventional midpoint voltage matching circuit of FIG. 13, α = 20 V and the floating power supply voltage EF
Is set to 80 Vpp, for example, the offset voltage V
When OFF is shifted to the positive side by +20 V, the floating lower voltage Ed changes from −10 V to +10 V. However, since the output potential of the operational amplifier 51 is fixed to the ground potential, the lower voltage Ed is It saturates at 0V due to the problem of the dynamic range of the operational amplifier 51,
There is a problem that the voltage does not rise above 0V.

Therefore, in the circuit configuration shown in FIG. 13, another bias power supply is required to freely adjust the offset voltage VOFF to the positive side or the negative side.

As described above, the power supply voltage on the upper side and the lower side of the floating power supply is switched to the common anode electrode for each horizontal section using a switching element, and the common inversion drive power supply is used. The common inversion drive power supply charges and discharges the capacitance component of the electrode. As a capacitance component of the anode electrode, for example, a panel of 20 ″ class generally has a capacitance of tens of thousands of pF.
When the common inversion drive power supply is switched, a large current flows as a current at the time of charging and discharging the capacitance component, and a large spike occurs in the upper and lower power supply voltages of the floating power supply.

That is, when the common anode electrode is driven by an ideal square wave of, for example, about 80 Vpp (see FIG. 16A) as described above, a large anode driving current as shown in FIG. (Charge / discharge current) flows,
The floating power supply voltage for the operational amplifier 51 is shown in FIG.
It fluctuates as shown in (c) and (e). As a result, the midpoint voltage of the power supply for the operational amplifier circuit 51 that determines the offset value of the power supply voltage also changes at the moment of this switching, as shown in FIG.
However, since the variation is quickly corrected, a large current flows to the output stage of the offset voltage and the output stage of the operational amplifier 51, and power consumption increases.

In particular, PALC requires a large power consumption due to a high power supply voltage and a large capacity between the anode electrode and the transparent electrode (for example, about 15000 pF) for a large screen. Therefore, the transistor 5
4, 55 required a large heat sink.

As described above, in the conventional plasma-addressed liquid crystal display device, a large heat sink is provided for increasing power consumption, and another power supply circuit is provided for adjusting the offset voltage. Therefore, there is a problem that the weight of the display device increases and miniaturization is hindered.

An object of the present invention is to provide a plasma addressed liquid crystal display device which can solve the above problems.

[0057]

According to a first aspect of the present invention, there is provided a liquid crystal display device comprising a plurality of display pixels arranged in first and second directions orthogonal to each other. A liquid crystal layer for constituting, and a plurality of first scanning electrodes arranged on one surface side of the liquid crystal layer at a repetition pitch of the display pixels in the first direction;
On the surface of the liquid crystal layer opposite to the one surface, the electrodes are provided at the repetition pitch of the display pixels in the second direction, and electrodes to which a scanning voltage is supplied are commonly connected to each other. A signal voltage corresponding to a pixel value to be displayed is applied to each of the plurality of second scan electrodes and each of the plurality of first scan electrodes using a unidirectional power supply in a positive or negative direction. A signal voltage inverted around a midpoint potential is applied to display pixels adjacent in the second direction or to display pixels in a section adjacent in the time direction of the same display pixel. And a reverse drive voltage that reverses around a midpoint potential in synchronization with an inversion cycle of the signal voltage on each of the electrodes commonly connected to the plurality of second scan electrodes. Invert to apply A low-pass filter to which a midpoint potential of the inverted drive voltage is supplied; a midpoint potential of the inverted drive voltage passed through the lowpass filter; and a midpoint potential of the signal voltage. And a midpoint voltage matching circuit that sets an upper potential and a lower potential of the inversion drive voltage so that both midpoint potentials match by controlling using the comparison output. I do.

According to the present invention having such a configuration, since an appropriate low-pass filter is inserted in the midpoint potential detecting section of the floating power supply, the capacitance of the anode electrode is switched when the common inversion drive power supply is switched. Spikes in the upper and lower power supply voltages of the floating power supply during charging and discharging of components are reduced, and as a correction operation to match the midpoint voltage, steep correction is not performed, so dynamic power consumption Is improved to be smaller.

Further, in the liquid crystal display device according to the third aspect of the present invention, a liquid crystal layer for forming a plurality of display pixels arranged in first and second directions orthogonal to each other; On one surface side, a plurality of first pixels arranged at a repetition pitch of the display pixels in the first direction.
Scanning electrodes and electrodes provided on the surface of the liquid crystal layer opposite to the one surface at a repetition pitch of the display pixels in the second direction, and supplied with a scanning voltage. A plurality of second scan electrodes connected to each other, and each of the plurality of first scan electrodes,
A unidirectional power supply in a positive or negative direction is used to apply a signal voltage corresponding to a pixel value to be displayed, and the display pixels adjacent in the second direction or the same display pixel are applied. And a signal drive circuit for applying a signal voltage inverted around a midpoint potential to display pixels in a section adjacent in the time direction, and the plurality of second scan electrodes are commonly connected. An inversion drive circuit that applies an inversion drive voltage that inverts around a midpoint potential to each of the electrodes in synchronization with the inversion cycle of the signal voltage; a midpoint potential of the inversion drive voltage; A circuit for comparing the point potential with the point potential, setting the upper potential and the lower potential of the inversion drive voltage so that the two midpoint potentials match by controlling using the comparison output. The part to be Connected to a point where the midpoint potential of the power supply voltage of the driving circuit is obtained, so that the comparison output becomes the midpoint potential of the power supply voltage of the signal drive circuit so that the two midpoint potentials match. And a point voltage matching circuit.

According to such a configuration, since the portion where the comparison output voltage is obtained is connected to the portion where the midpoint potential of the power supply voltage of the signal drive circuit is obtained, the comparison output voltage is not the ground potential but the offset voltage. It changes according to. Therefore, it is possible to secure a sufficient range as the adjustment range of the offset voltage.

[0061]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a plasma addressed liquid crystal display device according to the present invention will be described with reference to the drawings.

FIG. 2 is a diagram showing a partial circuit block of a display device of this embodiment, particularly, a video system. It should be noted that in FIG.
Is a configuration of a display element using the PALC1 described with reference to FIGS. In the following description, this plasma address type liquid crystal display element 37 is referred to as a PALC display element 37.

Although not shown in this display device, N
A TSC (National Television System Committee) is provided in front of the demodulation unit 21 with a broadcast receiving means such as an NTSC U / V tuner and a BS tuner and a standard video signal reproduced by an external device such as a VTR. A plurality of external input terminals are provided.

The standard video signal selected by the broadcast receiving means and the external standard video signal input from one or more external input terminals are selected in the display device and input to the NTSC demodulation section 21. You.

The video signal input to the NTSC demodulation unit 21 is demodulated into a luminance signal and a color difference signal,
Supplied to The synchronization signal extracted by the NTSC demodulation unit 21 is supplied to an LCD controller 29 described later, and the LCD controller 29 generates an operation clock of each functional circuit described below, and performs various signal processing. It is configured to be synchronized.

The double speed conversion section 22 is provided with a frame memory capable of storing one frame of video signal (luminance signal, color difference signal), and a motion component is detected by the frame memory. Then, in the still image area, the video signal of the current field and the one horizontal period preceding by one field are read twice consecutively at twice the writing speed.

In the moving image area, the video signal of one horizontal period of the field information at that time and the interpolated video signal generated by the interpolation process using the video signals of one horizontal period before and after that are read out at double speed. , 525 lines / 60 Hz.

The video signal that has been subjected to the double-speed processing is supplied from the double-speed conversion unit 22 to the video signal processing unit 23. After undergoing color adjustment, hue adjustment, and the like in the video signal processing unit 23, the video signal is subjected to inverse matrix processing. R (red) color, G
Primary color signals of (green) and B (blue) are generated. Each primary color signal generated here is converted into digital video data V8b by an A / D converter 24 having 8-bit quantization accuracy, and furthermore, an error diffusion processing unit 25
Is equivalently converted into 7-bit video data V7b having an accuracy equivalent to 8 bits.

Then, the video data V7b (R color, G color,
Each of the 7 bits for each of the B colors is supplied to a liquid crystal column driver 27 after being subjected to white balance processing by a white balance adjustment unit 26.

The liquid crystal column driver 27 has, for example, 854
Video data of one horizontal period composed of pixels, that is, 854
The video data V7b of the pixel of the pixel × 3 channels (R color, G color, B color) is latched, and the video data V7
b is held for one horizontal period. When a plasma discharge is generated in a predetermined scanning groove 7 (FIG. 9) by a plasma driver 32 to be described later, the video data V7b for each pixel is read for each horizontal line, and further D / A conversion is performed. The signal is converted into an analog signal by the detector 28 and applied to the transparent drive electrodes 13R, 13G, and 13B of the PALC display element 37, respectively.

The LCD controller 29 is configured to operate with a power supply of, for example, 5 V, and count clock CLK for driving the S-shaped correction waveform generator 30 by an operation clock generated based on a synchronization signal from the NTSC demodulator 21. , An anode inversion pulse INV for driving the anode inversion drive circuit 31 and a plasma pulse PR for driving the plasma driver 32 to cause plasma discharge for each scanning groove 7 (horizontal line).

The S-shaped correction waveform generator 30 is driven by the count clock CLK to generate an S-shaped corrected waveform VR for controlling the driving rate in accordance with the transmittance characteristics of liquid crystal molecules to be pixels. The generated S-shaped correction waveform VR is supplied to the liquid crystal column driver 27, and S-shaped correction (gamma correction) is performed on the video data V7b that has undergone white balance processing.

The plasma driver 32 applies a power supply voltage of −300 V from the power supply circuit 35 to the cathode electrode 9. In this embodiment, a horizontal scanning line corresponding to about 480 lines constituting an NTSC screen, that is, a PA
The scanning grooves 7 formed in the LC display element 37 are sequentially selected, a plasma pulse PR is supplied, and a plasma discharge is generated by a power supply voltage of about −300 V applied to the cathode electrode 9 of the scanning grooves 7.

That is, in synchronization with the double-speed video data V7b input to the liquid crystal column driver 27, the scanning grooves 7,
Are driven sequentially in the vertical direction of the screen of the PALC display element 37, for example, from top to bottom, and the discharge state is repeated for each field to drive the PALC display element 37 in accordance with the video data. Will be able to As a result, the input video signal can be displayed as a video.

The backlight circuit 36 drives a backlight light source for illuminating the PALC display element 37 from the back side. A light beam emitted from the backlight light source passes through predetermined pixels of the PALC display element 37 to form a display image. In this example, the backlight circuit 36 is controlled by the microcomputer control unit 34 and can perform picture adjustment by adjusting the brightness of the backlight light source.

The microcomputer control unit 34 allows the user to operate the operation unit 3.
In accordance with a command input from the control unit 3, the above-mentioned various controls such as tuning of each tuner, image adjustment, and power ON / OFF are performed.

Next, the plasma driver 32 will be described in detail. As shown in FIG.
For example, a power supply voltage of about −300 V is used, which is connected to the first line L1 to the 480th line L480.
The cathode electrodes 9 (1), 9 (2),.
, 9 (480) (where (n) indicates the n-th line; the same applies hereinafter).

Each of the cathode electrodes 9 (1) to 9 (480) is arranged as a switching element for plasma discharge, for example, an NMOS.
(N-channel MOS) transistors Tr (1), Tr
(2),..., Connected to the drain of Tr (480). These NMOS transistors Tr (1) to Tr
The source electrodes of (480) are commonly connected, and further connected to, for example, a current source IA of about 100 mA, so that the current at the time of plasma discharge is controlled to be constant so that stable plasma discharge is performed. I have to.

Each of the cathode electrodes 9 is connected to a plasma power supply 35 via a drain resistor RD.

The NMOS transistors Tr (1) to
A plasma pulse PR, which is a positive pulse having a pulse width of about 10 μsec, for example, is sequentially applied to the gate electrode of Tr (480) from the LCD controller 29 line by line.

Then, the NMOS transistor Tr (1)
When the plasma pulse PR is applied to, for example, the gate electrode of the NMOS transistor Tr (1) among the transistors Tr (480) to Tr (480), as shown in a hatched pattern on the first line L1 in FIG. 8 (1), a plasma discharge occurs between the cathode electrode 9 (1).

As described above, by sequentially applying the plasma pulse PR to the cathode electrodes of the first line L1 to the 480th line L480 in synchronization with the pixel signals of one line, the image of one field is displayed. Can be formed.

Next, the phase relationship between the video drive signal of the PALC display element 37 and the plasma pulse PR will be described.

The scanning period for one line is, for example, 32 μs.
ec, a certain line, for example, N of the first line L1
10 μm is applied to the gate input of the MOS transistor Tr (1).
A positive-polarity plasma pulse PR having a width of sec is applied. Then, plasma discharge occurs in the scanning groove 7 of the corresponding line.
FIG. 4C shows a cathode waveform of the scanning line.

Thus, in a state where the scanning groove 7 of a certain line is plasma-discharged, a maximum of 70 V video signal sampled and held for each pixel shown in FIG. , The video signal for one line can be written to the PALC display element 37.

That is, FIG. 4A shows the waveform of a sampled and held video signal for one pixel. Each of the 854 pixels included in the line where plasma discharge occurs in the scanning groove 7 is shown in FIG. In the same way, one line is displayed by applying a voltage corresponding to the video signal data to the transparent electrode 13 corresponding to each pixel for about 20 μsec.

Then, in the next second line L2, as shown in FIG. 4D, a positive plasma pulse PR having a width of 10 .mu.sec is applied to the NMOS transistor Tr (2). While discharging,
As shown in FIG. 4A, a sample-and-hold is performed for each pixel, and an inverted video signal (inverted data) of a maximum of −70 V on the second line is continuously applied for, for example, about 20 μsec.

In this way, by inverting and outputting the video signal between the odd-numbered lines and the even-numbered lines, the PALC display element 37 is driven by AC, and the deterioration of the liquid crystal molecules due to the continuous application of DC voltage is prevented. I am trying to do it.

By writing the video signals for 480 lines sequentially to the PALC display element 37 at the above timing, an image for one field can be formed and displayed.

The sample and hold for each pixel of the video signal as shown in FIG.
7 and the D / A converter 28. Next, the configuration and operation of the liquid crystal column driver 27 and the D / A converter 28 will be described.

FIG. 5 shows the liquid crystal column drivers 27 and D
FIG. 6 is a block diagram of a circuit configuration example of the / A converter 28, and FIG.
Shows the operation waveform. In this example, a so-called charge-and-hold type D / A conversion circuit is used. Note that the circuit of FIG. 5 is provided for each color data of a pixel, and the D / A conversion output is a corresponding one-color transparent electrode among the transparent electrodes 13R, 13G, and 13B for one pixel. This is applied to the electrodes. In this example, each color is 7-bit (a value from 0 to 127) data as described above.

As shown in FIG. 5, the shift register 41
, A video signal (data of each color) for one line is sequentially recorded for each pixel, and the last video data of one line is taken in, and at the same time, parallel data is transferred to the video data latch circuit 42, The counter 43 is reset. Thereafter, the output of the up / down counter 43 for 128 clocks and the output data of the video data latch circuit 42 are compared in the comparator circuit 44, and the MOS transistor 46 is turned on until the data match, and the charge / discharge capacitor 45 To charge the ramp waveform VR.

The ramp waveform VR is converted by the S-shaped correction waveform generator 30 into the characteristics of the transmittance of the liquid crystal and the drive electrode voltage (FIG. 12).
7) is a voltage waveform generated by correcting the non-linear characteristic of FIG.

As shown in FIG. 6, for example, when the digital value of the video data is “125”, the up / down counter 43 keeps counting until the 125th count clock is reached.
Since the output count value data of the up / down counter 43 is smaller than the digital value of the video data latch circuit 42, the output of the comparator circuit 44 becomes high level as shown in FIG. Then, the ramp waveform VR is charged up to the capacitor 45 (see FIG. 6B).

When the count value data of the up / down counter 43 becomes 126, which is larger than the digital value of the video data latch circuit 42, the output of the comparator circuit 44 goes low. At the moment when the output of the comparator circuit 44 becomes low level, M
Since the OS transistor 46 is turned off, the capacitor 4
5 holds the voltage at that time. That is, the operation of the charge & hold type D / A conversion is performed.

When the ramp waveform VR gradually decreases and becomes lower than the hold voltage as shown in the latter half of FIG. 9B, the charged voltage of the capacitor 45 is discharged through the diode 47. Thus, a hold voltage corresponding to the video signal data for each horizontal section as shown in FIG. 4A is obtained, and the transparent electrodes 13R, 13R of the corresponding pixels are obtained.
G, 13B.

On the other hand, 1 from the anode inversion drive circuit 31
When the common anode power supply voltage inverted every horizontal period is P
By being supplied to the common anode electrode of the ALC display element 37, the inversion drive is performed every one horizontal period as shown in FIG. Next, a circuit example of the anode inversion drive circuit 31 in this embodiment is shown in FIG. This anode inversion drive circuit 31 forms a midpoint voltage coincidence circuit. In the circuit of FIG. 1, the same parts as those in the conventional circuit of FIG. Description is omitted.

The anode inversion drive circuit 31 of this example supplies a midpoint voltage of the floating power supply voltage EF to one input terminal of the operational amplifier 51 through a low-pass filter (hereinafter, referred to as a low-pass filter). When,
The point that the common emitter connection point of the transistors 54 and 55 is not grounded but is connected so as to be the same as the potential of the variable resistor 62 for setting the midpoint potential including the offset voltage of the transparent electrode driving power supply voltage Vdc. , And FIG.

That is, the connection midpoint between the resistors 52 and 53 (one input terminal of the operational amplifier 51) is grounded through the resistor 71 and the capacitor 72, and
Is provided with a lag-lead type low-pass filter 70 which also serves to prevent oscillation of the negative feedback operation. This low-pass filter 70
The method described above attenuates the voltage fluctuation of the midpoint potential during the anode inversion driving as described later so that the fluctuation of the floating power supply voltage is not suddenly corrected. The correction current at this time is set to a fraction of the conventional value by appropriately selecting the time constant of the low-pass filter 70.

A movable element of a variable resistor 62 for adjusting the midpoint potential of the transparent electrode driving power supply voltage Vdc and its offset voltage is connected to the other input terminal of the operational amplifier 51, and the variable resistor 62 Are supplied to the bases of the NPN transistor 81 and the PNP transistor 82 in common. The collector of the NPN transistor 81 has a transparent electrode driving power supply voltage Vd.
c is connected to a terminal from which the PNP transistor 82 is obtained.
Are grounded.

The emitters of the NPN transistor 81 and the PNP transistor 82 are commonly connected, and the connection point is connected to the common connection point of the emitters of the transistors 54 and 55 which is equal to the output point of the operational amplifier 51. As a result, as described later, the dynamic range of the adjustment range of the offset voltage by the variable resistor 62 becomes wider than before.

First, the fact that the current consumption is reduced will be described.

That is, as described above, in the case of the large-sized display device of the PALC system, the capacitance component between the commonly connected anode electrode and the transparent electrode is about 1500.
There is 0 pF. For this reason, when the low-pass filter 70 is not provided, the common anode
When driven by an ideal square wave of about 0 Vpp shown in FIG. 16A, a large anode drive (charge / discharge) current flows as shown in FIG. 16B, and the floating power supply voltage for the operational amplifier 51 becomes It fluctuates as shown in FIGS. As a result, the midpoint potential also fluctuates as shown in FIG. 16D, and FIG. 16 for correcting this voltage fluctuation.
Large currents as shown in (g) and (i) flow to the output stage of the offset voltage and the output stage of the operational amplifier 51, and the transistors 54, 55, 81, and 82 need large heat sinks.

The drive waveform of the actual common anode drive voltage is not an ideal square wave as shown in FIG. 16A, but a waveform whose rising and falling are slightly reduced as shown in FIG. 7A. As shown in FIGS. 7B and 7D, the voltage on the positive side and the negative side of the floating power supply has a small voltage drop as compared with that shown in FIG. 16, but is still large.

However, in this embodiment, as shown in FIG. 1, a lag-lead type low-pass filter 70 which also prevents oscillation of the negative feedback operation of the operational amplifier 51 is inserted at the midpoint of the floating power supply voltage EF. The voltage fluctuation of the midpoint potential during the anode inversion driving is attenuated as shown in FIG. 7C, so that the fluctuation of the midpoint voltage of the floating power supply voltage EF is not suddenly corrected.

The correction current at this time is reduced to a fraction of the conventional value as shown in FIGS. 7 (e) and 7 (f) by appropriately selecting the time constant of the low-pass filter 70. Become. FIG. 7E shows a correction current for raising the midpoint potential by the transistors 81 and 55, and FIG.
This is a correction current for lowering the midpoint potential by the transistors 54 and 82. By providing the low-pass filter 70 in this manner, in this embodiment, the correction current can be reduced to a fraction of the conventional value, so that the current consumption can be reduced.

As described above, a slight voltage drop occurs between the positive and negative voltages of the floating power supply, and the actual anode inversion drive voltage waveform becomes as shown in FIG. Since the rise and fall are still steep, there is a problem of unnecessary radiation. However, the anode inversion drive voltage waveform when the low-pass filter 70 is present as in this example is as shown in FIG. 7 (g), which has the effect of reducing the above-described radiation interference from the switching transistor.

Next, the adjustment range of the offset voltage will be described.

As described above, in this embodiment, as shown in FIG. 1, the buffer output of the operational amplifier 51 is adjusted to the midpoint adjustment voltage for varying the offset voltage. In the example of FIG. By connecting to the buffer output of the midpoint voltage of the voltage Vdc, the lower dynamic range of the floating power supply is expanded, and the offset voltage can be adjusted over a wide range. Similarly, the adjustment range on the small amplitude side (for example, 60 Vpp) of the common anode inversion drive voltage can be set wide.

That is, for example, when the offset voltage VOFF is set to +20 V, the output of the operational amplifier 51 is set to 50 V obtained by adding the offset voltage (Voff) 20 V to the midpoint potential 30 V of the transparent electrode drive power supply voltage Vdc. And for floating common voltage drive,
For example, the upper voltage of the 60 + 20 = 80 Vpp power supply is 60
+ 10 + 20 = 90V, lower voltage is -10 + 20 = 1
Although the output voltage of the operational amplifier 51 using the power supply is fixed to 0 V, the output voltage of the operational amplifier 51 is connected to the midpoint of the upper and lower voltages of the common power supply, that is, 50 V. do not do. Further, the operation current of the transistor in the output stage of the operational amplifier 51 is equally divided, so that the power consumption of the transistor is not biased.

Even when the amplitude of the common inversion drive voltage is reduced to, for example, 60 Vpp, the middle voltage of the transparent electrode drive power supply voltage Vdc and the output potential of the operational amplifier remain at 50 V.
+ 20V = 80V, lower voltage is 0V + 20V = 20V
And the dynamic range problem does not occur.

Further, the offset voltage VOFF is set to -20V
The case where it is set to is described. The output of the operational amplifier 51 is
30-20 = 10 V, and a floating common inversion drive power supply, for example, 80 Vpp (α
= 10) is 60 + 10−20 = 5
0V and the lower voltage are fixed at -10V-20V = -30V, but the output voltage of the operational amplifier using the power supply is between the upper and lower voltages of the floating common inversion drive power supply. Since it is connected to 10V which is equal to the point, no problem occurs in the dynamic range.

Even if the amplitude of the common inversion driving power supply is reduced to 60 Vpp, the voltage on the upper side is 60 Vpp.
V-20V = 40V, lower voltage is 0V-20V = -2
Although it becomes 0 V, since the midpoint potential of the transparent electrode driving power supply and the output potential of the operational amplifier remain at 30-20 = 10 V, the problem of the dynamic range does not occur.

As described above, by changing the output potential of the operational amplifier 51 in synchronization with the offset voltage, the midpoint voltage of the floating common inversion drive power supply voltage for the operational amplifier 51 becomes the output voltage of the operational amplifier 51. Even if the offset voltage or the floating power supply voltage is changed, the output voltage of the operational amplifier 51 always remains at the midpoint potential between the upper and lower voltages of the floating power supply, so that there is no problem in the dynamic range. .

As described above, the plasma addressed liquid crystal display element has a common anode inversion drive voltage of the TFT.
About 10 times the voltage is required compared to the system, and a low-pass filter is inserted in the voltage fluctuation component at the middle point when switching this voltage, so that the mid-point voltage-matched operational amplifier feedback system is used. In such a case, the correction current at the output stage of the floating voltage midpoint determination circuit can be reduced to about 1/4. Therefore, the heat sink can be downsized and the shield case for radiation measures can be simplified, and a low-cost display device can be configured.

The common anode inversion drive voltage is applied to all the anode electrodes by switching the power supply output on the upper side and the lower side of the inversion drive voltage, for example, every horizontal section. Since the rising waveform of the wave is dull, it is possible to reduce the switching loss of the power supply switching element and the radiation from the anode electrode driving waveform.

Therefore, according to the present invention, it is possible to achieve a simple heat radiation design and a sufficient effect for reducing radiation due to a dull driving waveform.

When the offset voltage of the midpoint voltage is changed, the midpoint potential of the transparent electrode driving power supply side is changed up and down. By combining the buffer output of the midpoint voltage and the output of the operational amplifier, The output operating point of the operational amplifier is optimized with respect to the adjustment width of the offset voltage and the adjustment width of the common voltage, and a sufficient adjustment range can be secured.

In the above example, the upper and lower power supply outputs of the inversion drive voltage are switched for each horizontal section, but may be switched for each field. Further, the above example is a case of a display device using a PALC display element, but the present invention is equally effective for a common inversion driving method of a normal TFT type liquid crystal display element.

[0120]

As described above, according to the present invention, by providing the low-pass filter, the current consumption can be reduced, thereby simplifying the heat radiation design and dulling the drive waveform. Therefore, it is possible to obtain a sufficient effect on radiation reduction.

Further, in the common anode inversion driving method, it is possible to widen the offset adjustment range at the midpoint of the transparent electrode driving power supply voltage for driving the liquid crystal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration example of a main part of an embodiment of the present invention.

FIG. 2 is a block diagram showing a basic configuration of a display device using a plasma addressed liquid crystal display element to which an embodiment of the present invention is applied.

FIG. 3 is an example of a circuit diagram of a plasma discharge driver used in the embodiment of the present invention.

FIG. 4 is a diagram showing a phase relationship between video data written to a liquid crystal display element and a plasma discharge pulse in the embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a charge-and-hold type D / A converter as a partial circuit example of the embodiment of the present invention;

FIG. 6 is a timing chart for explaining the principle of the D / A conversion operation of FIG. 5;

FIG. 7 is an operation waveform diagram for explaining a main part of the embodiment of the present invention.

FIG. 8 is a diagram showing a structure of a display device using a PALC display element used in an embodiment of the present invention.

FIG. 9 is a diagram illustrating a structure of a display device using a PALC display element used in the embodiment of the present invention.

FIG. 10 shows a PALC used in the embodiment of the present invention.
FIG. 3 is a diagram for explaining a plasma channel of a display element.

FIG. 11 is a diagram for explaining a common anode inversion driving method.

FIG. 12 is a diagram illustrating a relationship between a driving voltage and a transmittance of a PALC display element.

FIG. 13 is a diagram illustrating an example of a midpoint potential matching circuit that determines a midpoint potential of a common anode inversion drive power supply in a conventional system.

FIG. 14 is a diagram for explaining an operation principle of a midpoint potential matching circuit for determining a midpoint potential of a common anode inversion drive power supply.

FIG. 15 is a diagram showing a relationship between a driving voltage of a PALC display element and transmittance and an offset voltage.

FIG. 16 is an operation waveform diagram of a midpoint potential determination circuit in a conventional system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... PALC display element, 2 ... backlight, 4 ... polarizing filter, 5 ... plasma substrate (back glass), 6 ... partition (rib), 7 ... scanning groove (plasma channel), 8 ... anode electrode, 9 ... Cathode electrode, 10 insulating layer (thin glass), 11 liquid crystal layer, 12 (12R, 12G, 12
B) Color filter layer 13 (13R, 13G, 13
B): transparent electrode (ITO thin film), 14: front glass, 2
1: NTSC demodulator, 22: frame double speed conversion circuit, 2
3 video signal processing circuit, 24 A / D converter, 25 error diffusion unit, 26 white balance adjustment circuit, 27 liquid crystal column driver, 28 D / A converter, 29 LCD
Controller, 30: S-shaped correction waveform generation circuit, 31: anode inversion drive circuit, 32: plasma driver, 33 ...
Operation unit, 34: microcomputer control unit, 35: power supply circuit, 36
... Backlight light source, 37 ... Plasma address type liquid crystal display element

Claims (5)

[Claims] 1. A liquid crystal layer for forming a plurality of display pixels arranged in first and second directions orthogonal to each other, and a display surface of the display pixels in the first direction on one surface side of the liquid crystal layer. A plurality of first scanning electrodes arranged at a repetition pitch, and provided on the surface of the liquid crystal layer opposite to the one surface at the repetition pitch of the display pixels in the second direction; A plurality of second scan electrodes to each of which electrodes to which a voltage is supplied are commonly connected to each other, and a positive or negative unidirectional power supply for each of the plurality of first scan electrodes. And applying a signal voltage corresponding to a pixel value to be displayed, to a display pixel adjacent in the second direction, or to a display pixel in a section adjacent to the same display pixel in the time direction. Is centered on the midpoint potential A signal driving circuit so as to apply the inverted signal voltage Te, each common to the connected electrodes of the plurality of second scan electrodes, in synchronization with the inversion cycle of the signal voltage,
An inversion drive circuit that applies an inversion drive voltage that inverts around the midpoint potential; a low-pass filter to which the midpoint potential of the inversion drive voltage is supplied; and the inversion that passes through the low-pass filter The midpoint potential of the driving voltage is compared with the midpoint potential of the signal voltage, and the upper and lower potentials of the inverted driving voltage are controlled by using the comparison output so that the two midpoint potentials match. A liquid crystal display device comprising: a midpoint voltage matching circuit to be set. 2. The method according to claim 1, wherein the plurality of second scan electrodes are located at positions opposed to a surface of the liquid crystal layer opposite to the one surface.
A plasma discharge channel is formed in the first direction, and the electrodes are provided at a repetition pitch of the display pixels in the second direction, and electrodes to which a scanning voltage is supplied are commonly connected to each other. Wherein the inversion drive circuit applies a midpoint potential to each of the commonly connected electrodes of the plurality of second scan electrodes in synchronization with the inversion cycle of the signal voltage. 2. The liquid crystal display device according to claim 1, wherein an inversion drive voltage for inverting the liquid crystal around the center is applied. 3. A liquid crystal layer for forming a plurality of display pixels arranged in first and second directions orthogonal to each other, and the display pixels are arranged in the first direction on one surface side of the liquid crystal layer. A plurality of first scanning electrodes arranged at a repetition pitch, and provided on the surface of the liquid crystal layer opposite to the one surface at the repetition pitch of the display pixels in the second direction; A plurality of second scan electrodes to each of which electrodes to which a voltage is supplied are commonly connected to each other, and a positive or negative unidirectional power supply for each of the plurality of first scan electrodes. And applying a signal voltage corresponding to a pixel value to be displayed, to a display pixel adjacent in the second direction, or to a display pixel in a section adjacent to the same display pixel in the time direction. Is centered on the midpoint potential A signal driving circuit so as to apply the inverted signal voltage Te, each common to the connected electrodes of the plurality of second scan electrodes, in synchronization with the inversion cycle of the signal voltage,
An inversion drive circuit that applies an inversion drive voltage that inverts around the midpoint potential; and compares the midpoint potential of the inversion drive voltage with the midpoint potential of the signal voltage, and controls using the comparison output. A circuit for setting an upper potential and a lower potential of the inversion drive voltage so that both middle potentials coincide with each other. A midpoint voltage matching circuit connected to the obtained portion so that the comparison output is at a midpoint potential of the power supply voltage of the signal drive circuit so that the two midpoint potentials match. Characteristic liquid crystal display device. 4. The liquid crystal device according to claim 1, wherein the plurality of second scan electrodes are located at positions opposed to a surface of the liquid crystal layer opposite to the one surface.
A plasma discharge channel is formed in the first direction, and the electrodes are provided at a repetition pitch of the display pixels in the second direction, and electrodes to which a scanning voltage is supplied are commonly connected to each other. Wherein the inversion drive circuit applies a midpoint potential to each of the commonly connected electrodes of the plurality of second scan electrodes in synchronization with an inversion cycle of the signal voltage. 4. The liquid crystal display device according to claim 3, wherein an inversion driving voltage for inverting the liquid crystal around the center is applied. 5. The method according to claim 1, wherein a portion from which the comparison output voltage is obtained is connected to a buffer output of an offset adjustment voltage close to the midpoint potential instead of the midpoint potential of the power supply voltage of the signal drive circuit. The liquid crystal display device according to claim 3.