JP2001007660A - Analog signal processing circuit, a/d converter, semiconductor device test unit and oscilloscope - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog signal processing circuit that properly selects its input impedance. SOLUTION: This analog signal processing circuit 10 is provided with a signal input circuit 70, a level shift section 60, an amplifier 62 and a gain amplifier 20. The signal input circuit 70 is provided with an input terminal 50, an input changeover section 52, a high impedance input path 54, a low impedance input path 56 and an output changeover section 58. The high impedance input path 54 and the low impedance input path 56 are connected in parallel. The output changeover section 58 outputs an analog signal 22, passing through either of the high impedance input path 54 and the low impedance input path 56. A low input impedance is realized, where a resistive component of the low impedance input path 56 and a resistive component in the level shift section 60 are lower than the input impedance of the high impedance input path 54. With this configuration, when the analog signal 22 passes through the low impedance input path 56, deterioration in the distortion characteristic of the transmission signal can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an analog signal processing circuit for processing an analog signal, and more particularly, to an analog signal processing circuit capable of switching input impedance.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a conventional differential signal processing circuit 10. The differential signal processing circuit 10 includes a termination resistance switching unit 12, an input buffer circuit 14, a differential amplifier 16,
A level shift unit 18 and a gain amplifier 20 are provided.
The termination resistance switching unit 12 receives the analog signals 22 (22a and 22b) differentially. The termination resistance switching unit 12
The input impedance is switched according to the transmitted analog signal 22 to match the impedance. The input buffer circuit 14 receives the analog signal 22 output from the termination resistance switching unit 12 and outputs the analog signal 22 to the differential amplifier 16. The differential amplifier 16 outputs a voltage signal 24 proportional to the difference between the analog signals 22a and 22b to the level shift unit 18. The level shift unit 18 generates a shift voltage signal 26 obtained by removing a predetermined offset from the voltage signal 24,
Output to the gain amplifier 20. The gain amplifier 20 switches the amplitude range of the shift voltage signal 26 and outputs it to a subsequent circuit (not shown).

FIG. 2 shows a specific circuit configuration of a conventional differential signal processing circuit 10. As in FIG. 1, the differential signal processing circuit 10 includes a termination resistance switching unit 12, an input buffer circuit 1,
4, a differential amplifier 16, a level shift unit 18, and a gain amplifier 20.

The terminating resistance switching section 12 includes a switching relay 28
a, 28b and terminating resistors 30a, 30b.
The terminating resistors 30a and 30b are provided to realize a low input impedance, and for example, both have a resistance value of 50Ω. The input buffer circuit 14 has buffers 32a and 32b. Buffers 32a and 3
The input resistance 2b is much larger than the terminating resistors 30a and 30b, for example, each having a resistance value of about 1 MΩ. The differential amplifier 16 has a resistor r (34a, 34
b), resistor R (36a, 36b) and operational amplifier 38
Having. At this time, the amplification factor of the differential amplifier 16 is R /
r. The level shift unit 18 is an addition circuit that removes a predetermined DC offset (DCV) from the voltage signal 24 amplified by the differential amplifier 16. The level shift unit 18 outputs the shift voltage signal 26 to the gain amplifier 20, and the gain amplifier 20 amplifies and outputs the shift voltage signal 26.

As described above, buffers 32a and 3a
2b has a high impedance. In the conventional differential signal processing circuit 10, switching relays 28a and 28b
The input impedance is switched by opening and closing the switch.

FIG. 3 is a diagram for explaining switching of input impedance in the conventional differential signal processing circuit 10. As shown in FIG. The buffer 32a has an input resistance 48a of about 1 MΩ. When the switching relay 28a is open (that is, in the state shown in the figure), the input impedance becomes high (1 MΩ). On the other hand, when the switching relay 28a is closed, the resistance 30a and the resistance 48a are connected in parallel, so that the input impedance is low (about 50Ω). As described above, in the conventional differential signal processing circuit 10, the transmission line and the low-resistance section (50) are switched by the switching relays 28a and 28b.
Ω) is connected or disconnected to adjust (switch) the input impedance.

[0007]

As described above, the conventional differential signal processing circuit 10 includes the switching relays 28a and 28a.
The input impedance is adjusted by opening and closing 8b. For example, when the characteristic impedance is high, the switching relays 28a and 28b are opened to set the input impedance to a high impedance of 1 MΩ.
On the other hand, when the characteristic impedance is low, the switching relays 28a and 28b are closed to set the input impedance to a low impedance of about 50Ω. Further, the input impedance may be adjusted depending on the driving capability of the device. For example, when the output drive capability of the device is strong and the output signal frequency is high, the input impedance of the subsequent path is set to a low impedance of about 50Ω. In particular,
When the output signal frequency exceeds 10 MHz, it is necessary to lower the input impedance of the subsequent path in order to match the impedance. On the other hand, when the output drive capability of the device is weak and the output signal frequency is low, the input impedance of the subsequent stage is set to a high impedance of 1 MΩ. If the output signal frequency of the device is low, it is not necessary to match the impedance. Therefore, regardless of the output drive capability, the post-stage path input impedance may be set to a high impedance. As described above, the differential signal processing circuit 10 adjusts the input impedance according to the type of the transmitted signal.

To realize a high input impedance, F
It is effective to use the ET input buffers 32a and 32b. However, the signal passing through the input buffers 32a and 32b of the FET has a disadvantage that the distortion characteristic is deteriorated by the input-output characteristics of the FET. In particular, a high-frequency signal exceeding, for example, 10 MHz is input buffer 3.
When input to 2a and 32b, such high frequency signals may be unacceptably distorted. For this reason, it is preferable to use an FET buffer capable of ensuring low distortion performance up to high frequencies, but it is actually difficult and expensive to form such an FET buffer. In the conventional differential signal processing circuit 10, since a transmission signal is always input to the FET input buffers 32a and 32b, it is difficult to transmit a high-frequency signal without deteriorating distortion characteristics.

Accordingly, an object of the present invention is to provide an analog signal processing circuit capable of solving the above-mentioned problems. Another object of the present invention is to apply the principle of the analog signal processing circuit according to the present invention to equipment such as a waveform digitizer, an oscilloscope, and a semiconductor device test apparatus. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

[0010]

According to a first aspect of the present invention, there is provided an analog signal processing circuit for processing an analog signal, comprising: an input terminal to which the analog signal is input; Provided for the input terminal,
A high-impedance input path having a predetermined input impedance, a low-impedance input path provided for the input terminal and having a lower input impedance than the high-impedance input path, and the high-impedance input path or the low-impedance input path And an output switching unit that outputs the analog signal that has passed through any one of the above. The analog signal processing circuit according to the first embodiment is characterized in that the input impedance can be adjusted by providing two paths, a high impedance input path and a low impedance input path.

In one aspect of the first embodiment, when the analog signal is a differential signal, an analog signal processing circuit is provided with two input terminals to which two signals constituting the differential signal are input. And the high impedance input path, the low impedance input path, and the output switching unit provided for each of the input terminals. By providing a high-impedance input path and a low-impedance input path for each of the two signals constituting the differential signal, it is possible to adjust the input impedance also for the differential signal.

In another aspect of the first aspect, an analog signal processing circuit supplies the analog signal input to the input terminal to one of the high impedance input path and the low impedance input path. A switching unit may be provided.

[0013] In still another aspect of the first aspect, the high impedance input path includes a buffer circuit.

[0014] In still another aspect of the first aspect, the analog signal processing circuit may further include a constant impedance circuit having a predetermined impedance and electrically connected to the output switching unit.

[0015] In still another aspect of the first aspect, a resistor is provided for connecting the low impedance input path to the ground, and the resistor and the predetermined impedance in the constant impedance circuit are connected to the high impedance input path. The input impedance of the path may be lower than the input impedance.

In still another aspect of the first aspect, the analog signal processing circuit may further include a level shifter for removing a predetermined voltage from at least one of the signals output by the output switcher.

In still another aspect of the first aspect, the level shift unit can remove the predetermined voltage from both signals output by the output switching unit.

In still another mode of the first mode, the level shift section can remove the predetermined voltage from only one of the signals output by the output switching section.

In still another aspect of the first aspect, the level shift section may include a constant impedance circuit having a predetermined impedance and electrically connected to the output switching section.

In still another aspect of the first aspect, a power supply voltage of the buffer circuit may be varied based on an offset voltage of the analog signal.

[0021] In still another mode of the first mode, the analog signal processing circuit may further include an amplifier for amplifying the output of the level shift unit.

Further, the second embodiment of the present invention provides an AD converter for converting an analog signal input as a differential signal into a digital signal by using the analog signal processing circuit in the first embodiment. . The AD converter includes two input terminals to which two signals constituting the differential signal are input, a high impedance input path having a predetermined input impedance provided for each of the input terminals, A low-impedance input path provided for each of the input terminals and having an input impedance lower than the high-impedance input path; and the high-impedance input path or the low-impedance input path provided for each of the input terminals An output switching unit that outputs the analog signal, and a differential amplifier that outputs a voltage signal based on a voltage difference between the analog signals output from the output switching unit; And an AD converter that converts the digital signal into a digital signal. By providing two signal paths, a high impedance input path and a low impedance input path, at the input section of the AD converter, it is possible to adjust the input impedance of the AD converter. Therefore, this AD converter can perform highly reliable A / D conversion.

In one aspect of the second aspect, the AD converter may further include a constant impedance circuit having a predetermined impedance and electrically connected to each of the output switching units.

In another embodiment of the second aspect, a resistor for connecting the impedance input path to the ground is further provided, and the resistance and the predetermined impedance in the constant impedance circuit are connected to the high impedance input path. It is preferable that the input impedance is lower than the input impedance of the input.

A third embodiment of the present invention utilizes the analog signal processing circuit of the first embodiment, and further comprises a waveform digitizer for converting an analog signal output from the device under test into a digital signal; A semiconductor device test apparatus for testing a device under test, comprising: a measurement unit configured to measure pass / fail of the device under test based on a signal. In the semiconductor device test apparatus, the waveform digitizer may include an input terminal to which the analog signal is input, a high impedance input path having a predetermined input impedance, and a high impedance input path provided for the input terminal. A low-impedance input path having an input impedance lower than the high-impedance input path, and an output switching unit that outputs the analog signal through one of the high-impedance input path and the low-impedance input path. And an AD converter that converts the analog signal output from the output switching unit to the digital signal. In the semiconductor device test apparatus according to the third embodiment, impedance can be matched at the input part of the waveform digitizer, so that a highly reliable analog device test can be realized.

In one embodiment of the third mode, the waveform digitizer has two input terminals to which two signals constituting the analog signal, which are differential signals, are input, and the input terminal has two input terminals. The high impedance input path, the low impedance input path and the output switching unit, and a differential amplifier that outputs a voltage signal based on a voltage difference between the analog signals output from the output switching unit. An AD converter for converting the voltage signal into the digital signal. This waveform digitizer can convert an analog signal input differentially into a digital signal with high reliability.

A fourth aspect of the present invention, utilizing the analog signal processing circuit of the first aspect, comprises at least one contact terminal and a transmission line for transmitting an electric signal input to the contact terminal. An oscilloscope comprising: a signal input circuit to which the electric signal transmitted by the transmission path is input, and a processing unit that processes the electric signal input to the signal input circuit. In this oscilloscope, the signal input circuit is provided for an input terminal to which the electric signal is input, a high impedance input path having a predetermined input impedance provided for the input terminal, and provided for the input terminal. An output switch that outputs, to the processing unit, a low-impedance input path having an input impedance lower than the high-impedance input path and the electric signal that has passed through one of the high-impedance input path and the low-impedance input path And a unit. By using the analog signal processing circuit according to the first embodiment, the oscilloscope according to the fourth embodiment of the present invention can have an input unit capable of matching impedance.

Note that the above summary of the present invention does not list all of the necessary features of the present invention, and sub-combinations of these features can also constitute the present invention.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

FIG. 4 shows a first embodiment of the present invention.
1 shows an analog signal processing circuit 100 that processes an analog signal. The analog signal processing circuit 100 includes a signal input circuit 7
0, a level shift unit 60, an amplifier 62, and a gain amplifier 20. The signal input circuit 70 includes an input terminal 50,
It has an input switching section 52, a high impedance input path 54, a low impedance input path 56, and an output switching section 58. Input switching unit 52, high impedance input path 5
4. Low impedance input path 56 and output switching section 5
8 is provided for the input terminal 50. The high impedance input path 54 has a predetermined high impedance. On the other hand, the low impedance input path 56 realizes a lower input impedance than the high impedance input path 54. The high impedance input path 54 and the low impedance input path 56 are provided in parallel with each other.

The analog signal 22 is input to the input terminal 50. The input switching unit 52 supplies the analog signal 22 input to the input terminal 50 to either the high impedance input path 54 or the low impedance input path 56. For example, when the drive capability of the device that outputs the analog signal 22 is weak and the analog signal 22 is a low-frequency signal, the input switching unit 52 preferably supplies the analog signal 22 to the high-impedance input path 54. On the other hand, when the drive capability of the device that outputs the analog signal 22 is strong and the analog signal 22 is a high-frequency signal, the input switching unit 52 preferably supplies the analog signal 22 to the low-impedance input path 56.

The output switching section 58 outputs the analog signal 22 that has passed through either the high impedance input path 54 or the low impedance input path 56. The input switching section 52 and the output switching section 58 can cooperate to selectively switch the signal path. That is, when the input switching unit 52 supplies the analog signal 22 to the high impedance input path 54, the output switching unit 58 outputs the analog signal 22 that has passed through the high impedance input path 54.
On the other hand, when the input switching unit 52 supplies the analog signal 22 to the low impedance input path 56, the output switching unit 58
Analog signal 2 passed through low impedance input path 56
2 is output. Here, the low impedance input path 56
And the resistance component of the level shift unit 60 may realize an input impedance lower than the input impedance of the high impedance input path 54.

The analog signal 22 output from the output switching unit 58 is supplied to a level shift unit 60. The level shift unit 60 can remove a predetermined voltage from the analog signal 22. For example, the level shift unit 60
Can remove the DC common mode voltage of the differential output signal and the DC offset voltage of the output signal from the analog signal 22. Thus, the level shift unit 60
Outputs a shift voltage signal 26 shifted by a predetermined level from the analog signal 22 to the amplifier 62. Amplifier 6
2 amplifies the shift voltage signal 26. Further, the gain amplifier 20 can switch the amplitude range of the signal output from the amplifier 62.

As described above, the analog signal processing circuit 100 according to the first embodiment selectively switches the signal path according to the type of the analog signal 22, so that impedance matching can be achieved.

FIG. 5 shows a second embodiment of the present invention.
1 shows an analog signal processing circuit 100 that processes an analog signal that is a differential signal. The analog signal processing circuit 100
Two signal input circuits 70a, 70b, level shift unit 6
0, an amplifier 62 and a gain amplifier 20. The signal input circuit 70a includes an input terminal 50a, an input switching unit 52
a, a high impedance input path 54a, a low impedance input path 56a, and an output switching unit 58a.
Similarly, the signal input circuit 70b includes an input terminal 50b, an input switching unit 52b, a high impedance input path 54b, a low impedance input path 56b, and an output switching unit 58b.
Having. The input switching units 52a and 52b, the high impedance input paths 54a and 54b, the low impedance input paths 56a and 56b, and the output switching units 58a and 58b include the input switching unit 52, the high impedance input path 54, and the low impedance shown in FIG. It has the same or similar configuration and function as the input path 56 and the output switching unit 58.

Two analog signals 22a and 22b constituting a differential signal are input to input terminals 50a and 50b, respectively. Since the signal input circuits 70a and 70b have the same configuration, the operation of the signal input circuit 70a will be described below on behalf of both.

The input switching section 52a supplies the analog signal 22a input to the input terminal 50 to either the high impedance input path 54a or the low impedance input path 56a. For example, a device that outputs the analog signal 22a has a weak driving capability and the analog signal 22a
Is a low frequency signal, the input switching unit 52a preferably supplies the analog signal 22a to the high impedance input path 54a. On the other hand, when the drive capability of the device that outputs the analog signal 22a is strong and the analog signal 22a is a high-frequency signal, the input switching unit 52a preferably supplies the analog signal 22a to the low impedance input path 56a.

The output switching section 58a outputs the analog signal 22a that has passed through either the high impedance input path 54a or the low impedance input path 56a.
The input switching unit 52a and the output switching unit 58a can selectively switch a signal path in cooperation. That is, when the input switch 52a supplies the analog signal 22a to the high impedance input path 54a, the output switch 5
8a outputs the analog signal 22a that has passed through the high impedance input path 54a. On the other hand, the input switching unit 52a transmits the analog signal 22a to the low impedance input path 56a.
, The output switching unit 58a outputs the analog signal 22a passing through the low impedance input path 56a. Here, the resistance component of the low impedance input path 56a and the resistance component of the level shift unit 60 may realize an input impedance lower than the input impedance of the high impedance input path 54a.

Similarly, also in the signal input circuit 70b,
The output switching unit 58b is connected to the high impedance input path 54b.
Alternatively, it outputs the analog signal 22b that has passed through one of the low impedance input paths 56b. It is preferable that the signal paths selected in the signal input circuits 70a and 70b are the same as each other.

The analog signal 22a output from the output switching section 58a is supplied to the level shift section 60. Similarly, the analog signal 22 output from the output switching unit 58b
b is supplied to the level shift unit 60. The level shift unit 60 can remove a predetermined voltage from each of the analog signals 22a and 22b. For example,
The level shift unit 60 can remove the DC common mode voltage of the differential output signal and the DC offset voltage of the output signal from the analog signal 22. Analog signal 22
When a is the positive component of the differential signal and the analog signal 22b is the negative component of the differential signal, the level shift unit 60 may remove the common voltage of the differential signal from the analog signals 22a and 22b. When the analog signal 22a is a single-ended signal and the analog signal 22b is a ground signal, the level shifter 60 may remove the offset voltage from the analog signal 22a.
The level shift unit 60 includes the analog signals 22a and 22
b, a shift voltage signal 26 shifted by a predetermined level
a and 26b are output.

The amplifier 62 amplifies the output of the level shift unit 60. In the second embodiment, the amplifier 62
This is a differential amplifier that amplifies and outputs the difference between the shift voltage signals 26a and 26b. The gain amplifier 20 can switch the amplitude range of the signal output from the amplifier 62.

As described above, the analog signal processing circuit 100 according to the second embodiment selectively switches the signal path according to the type of the analog signal 22 that is a differential signal, so that impedance matching can be achieved. It becomes possible.

FIG. 6 shows an example of a specific circuit configuration of the analog signal processing circuit 100 according to the second embodiment of the present invention. The analog signal processing circuit 100 includes two signal input circuits 70a and 70b, a level shift unit 60, and an amplifier 6
2 and a gain amplifier 20. Signal input circuit 70
a is an input terminal 50a, an input switching unit 52a, a high impedance input path 54a, a low impedance input path 56
a, an output switching unit 58a and a resistor 82a. Similarly, the signal input circuit 70b has an input terminal 50b, an input switching unit 52b, a high impedance input path 54b, a low impedance input path 56b, an output switching unit 58b, and a resistor 82b. Since the signal input circuits 70a and 70b have the same configuration, the configuration and operation of the signal input circuit 70a will be described below as a representative of both.

The high impedance input path 54a includes a buffer circuit 80a, which has an input resistance of about 1 MΩ. The input switching unit 52a and the output switching unit 58a are connected to the high impedance input path 54a.
When the connection is made, the input impedance at the input terminal 50a becomes high impedance. On the other hand, the low impedance input path 56a is
It has no impedance component (resistance component) connected in series. In this embodiment, one end of a resistor 82a having a resistance value R is connected to the low impedance input path 56a, and the resistor 72a and the resistor 82a provided in the level shift unit 60 are connected.
Realizes an input resistance of 50Ω. The other end of the resistor 82a is grounded. Therefore, the input switching unit 52a and the output switching unit 58a
a, the input impedance at the input terminal 50a is low. Input switching unit 52
a and the output switching unit 58a are switching relays, and have a function of switching a signal transmission path.

The level shift section 60 has constant impedance circuits 84a and 84b, resistors 72c and 72d, a switching relay 76, and a -Voffset supply section 78. The constant impedance circuit 84a includes resistors 72a and 72e and an operational amplifier 74a, and has a predetermined impedance. Similarly, the constant impedance circuit 84b includes resistors 72b and 72f and an operational amplifier 74b, and has a predetermined impedance. Resistance 72a, 72b
Has a resistance value r. As described above, in this embodiment, the resistance 82a (resistance R) and the resistance 72a (resistance r) connected to the low impedance input path 56a are:
An input resistance (impedance) of 50Ω is realized. That is, r and R satisfy the relationship of r · R / (r + R) = 50. Therefore, the resistance value R of the low impedance input path 56a is set as follows: R = r · 50 / (r−50)

Input switching section 52a and output switching section 58a
However, by selecting a signal path on the low impedance input path 56a side, a low input impedance of 50Ω can be realized. r = 50 and R = ∞. If the resistance value r of the resistor 72a is fixed,
By making the resistance value R of a variable, the input impedance of the signal path can be arbitrarily changed.
At this time, the input impedance of the signal path is not limited to 50Ω and can be set to a desired value.

The level shift section 60 includes a signal input circuit 70
a function of removing a predetermined voltage from at least one of the analog signals 22a and 22b supplied from the signals a and 70b. The voltage to be removed includes a common voltage of a differential signal, an observed waveform center voltage in a single-ended signal, and the like. Hereinafter, these voltages are collectively called an offset voltage Voffset.

When the analog signal 22a is the positive component of the differential signal and the analog signal 22b is the negative component of the differential signal, the level shift unit 60 outputs the common signal of the differential signal from both the analog signals 22a and 22b. Voltage can be removed. At this time, in the -Voffset supply unit 78, Voffset is set to the DC common voltage of the differential output,
The switching relay 76 is switched to the -Voffset supply unit 78 side.

When the analog signal 22a is a single-ended signal and the analog signal 22b is a ground signal, the level shift unit 60 performs the observation so that the observed waveform operates around 0 V only from the analog signal 22a. The waveform center voltage can be removed. At this time, -V
In the offset supply unit 78, Voffset is set to the observation waveform center voltage. Further, since there is no need to shift the level of the ground signal, the switching relay 76 is switched to the ground side.

The operational amplifiers 74a and 74b output level-shifted shift voltage signals 26a and 26b. As described above, when the analog signal 22b is a ground signal, the shift voltage signal 26b may not be level-shifted. The shift voltage signals 26a and 26b are input to the amplifier 62 at the subsequent stage. In the present embodiment, the amplifier 62 is the differential amplifier 1 shown in FIG.
It may be 6. Amplifier 62 has a shift voltage signal 26a
And an amplified signal 64 obtained by amplifying the difference between 26b and 26b. Further, the gain amplifier 20 can switch the amplitude range of the amplified signal 64.

FIG. 7A shows analog signals 22a and 22b when analog signal 22a is the positive component of the differential signal and analog signal 22b is the negative component of the differential signal.
3 shows the signal waveforms of FIG. As shown, the differential signal 22a
And 22b, an offset voltage Voffset, which is a DC common voltage, is added.

FIG. 7 (b) shows a predetermined voltage Voffset from the analog signals 22a and 22b shown in FIG. 7 (a).
5 shows a signal waveform of an amplified signal 64 output from the amplifier 62 after removing (common voltage). In this example, the amplification factor of the amplified signal 64 is 1. Offset voltage Voffset
As a result, the amplified signal 64 has a signal waveform centered on 0V.

FIG. 7C shows signal waveforms of the analog signals 22a and 22b when the analog signal 22a is a single-ended signal and the analog signal 22b is a ground signal. A predetermined offset voltage Voffset is added to the analog signal 22a. Analog signal 22
b is fixed to 0V.

FIG. 7D shows a signal waveform of the amplified signal 64 output from the amplifier 64 after a predetermined voltage Voffset (observed waveform center voltage) is removed from the analog signal 22a shown in FIG. Show. As a result of removing the offset voltage Voffset, the amplified signal 64 has a signal waveform centered on 0V.

FIG. 8 shows the signal input circuit 70 shown in FIG.
5 shows a modified example of a. This signal input circuit 70a does not include the input switching unit 52a, unlike the signal input circuit 70a shown in FIG. High impedance input path 54a
Includes an input buffer circuit 80a. The output switching unit 58a in this modified example selectively implements the same function as the signal input circuit 70a shown in FIG. 6 by selectively switching the high impedance input path 54a or the low impedance input path 56a. Becomes When the output switching unit 58a is closed on the low impedance input path 56a side, the resistance 82a and the resistance 72a
It is preferable to form a low resistance of Ω.

FIG. 9 shows a modification of the specific circuit diagram of the analog signal processing circuit 100 according to the second embodiment of the present invention. The analog signal processing circuit 100 includes signal input circuits 70a and 70b, a level shift unit 60, an amplifier 62, and a gain amplifier 20. The signal input circuit 70a
It includes a buffer circuit 80a, and the signal input circuit 70b includes a buffer circuit 80b. The level shift unit 60 has a function of -V
poffset supply unit 78a, -Vnoffset supply unit 78b, resistors 72c and 72d, constant impedance circuits 84a and 84
b. In FIG. 9, the components denoted by the same reference numerals as those in FIG. 6 have the same or similar configurations as the corresponding configurations in FIG. In the modification shown in FIG. 9, the analog signal processing circuit 1 shown in FIG.
Points different from 00 will be described.

The buffer circuit 80a in the signal input circuit 70a is driven by positive and negative power supply voltages. Similarly, the buffer circuit 80b in the signal input circuit 70b is driven by the positive and negative power supply voltages. For example,
Under normal conditions, the positive power supply voltage is + 5V,
The negative power supply voltage is -5V.

In this modification, the analog signal 22
In order to make a and 22b signal waveforms centered on 0 V,-
Vpoffset supply unit 78a and -Vnoffset supply unit 78
b are provided respectively. In the embodiment shown in FIG. 6, one -Voffset supply unit 78 is provided to shift the voltages of the analog signals 22a and 22b. On the other hand, the modified example shown in FIG. 9 is characterized in that the -Vpoffset supply unit 78a and the -Vnoffset supply unit 78b are provided independently for each of the analog signals 22a and 22b. . By independently providing the -Vpoffset supply unit 78a and the -Vnoffset supply unit 78b, the analog signal 2
It is also possible to independently remove each offset voltage of 2a and the analog signal 22b.

Further, in analog signal processing circuit 100 shown in FIG. 9, buffer circuits 80a and 80b
One of the features is that the power supply voltage is adjusted. Specifically, positive power supply voltage VPP and negative power supply voltage VPM supplied to buffer circuit 80a are adjusted as follows.

VPP = + 5V + Vpoffset VPM = -5V + Vpoffset Similarly, the positive power supply voltage VNP and the negative power supply voltage VNM supplied to the buffer circuit 80b are adjusted as follows.

VNP = + 5V + Vnoffset VNM = -5V + Vnoffset As described above, the offset voltages (Vpoffset and Vnoffset)
offset) to adjust the power supply voltage.
Buffer circuits 80a and 80b can be driven around an optimum operating voltage.

FIG. 10 shows that the analog signal processing circuit 100 shown in FIG. 9 supplies power supply voltages (VPP, VPM, VNP, VNP,
VNM) and offset voltage (Vpoffset, Vnoffs)
e) shows one embodiment of a voltage supply circuit 90 for supplying the voltage supply circuit of FIG. The voltage supply circuit 90 includes a DAC (digital / analog converter) 92, a protection circuit 144, a positive differential signal power supply voltage supply section 140a, a negative differential signal power supply voltage supply section 140b, and an offset voltage supply section 14.
2 and an earth switching unit 130. DAC92
Receives a digital voltage shift signal designating the amount of voltage shift and outputs an analog voltage shift signal.

The offset voltage supply unit 142 includes a filter 146, a ground switching unit 128, and output terminals 132,
34. The filter 146 includes resistors 120 and 12
4, including an operational amplifier 122 and a capacitance 126,
Configure an active filter. In the filter 146, the resistor 120 is connected to the negative input of the operational amplifier 122. The positive input of the operational amplifier 122 is grounded. The output of the operational amplifier 122 is connected to the resistor 12 connected in parallel.
4 and the capacitance 126 provide negative feedback. The output of the operational amplifier 122 is connected to the output terminal 132 and one input terminal of the ground switching unit 128. Therefore, the voltage shift signal filtered by the filter 146 is supplied to the output terminal 132 and one input terminal of the ground switching unit 128. The ground switching unit 128 outputs one of the output of the operational amplifier 122 and the ground potential,
It is supplied to the output terminal 134.

As a result, the output terminal 132 is supplied with the offset voltage Vpoffset, and the output terminal 134 is supplied with the offset voltage Vnoffset. Vnoffset is
It is equal to Vpoffset or ground potential. Referring to FIG. 9, offset voltage Vpoffset is output terminal 13
2 to the -Vpoffset supply unit 78a, and the offset voltage Vnoffset is supplied from the output terminal 134 to -Vnoffset.
It is supplied to the supply unit 78b.

The protection circuit 144 has a resistor 94 and a Zener diode section 96. Zener diode section 96
Are constituted by zener diodes in opposite directions, and one end is connected to the ground.

Power supply voltage supply section 14 for positive differential signals
0a denotes a filter 148a, a voltage follower 104a, zener diodes 106a and 108a, a constant current circuit 11
0a, buffers 150a and 152a, and output terminal 1
12 and 114. The filter 148a includes a resistor 98
a and a capacitance 102a to form a passive filter. Similarly, the negative differential signal power supply voltage supply unit 140b includes a filter 148b, a voltage follower 10
4b, zener diodes 106b and 108b, constant current circuit 110b, buffers 150b and 152b, and output terminals 116 and 118. Filter 148b is
It has a resistor 98b and a capacitance 102b and constitutes a passive filter.

The output of filter 148a is connected to the positive input of voltage follower 104a. The Zener diodes 106a and 108a are connected in series in the same direction, and the output of the voltage follower 104a is connected to a transmission line connecting the Zener diodes 106a and 108a. The constant current circuit 110a
a is supplied with a reverse current. Buffers 150a and 152a are connected to both ends of the connection between the Zener diodes 106a and 108a, respectively. Buffers 150a and 152a are connected to output terminal 11 respectively.
2 and 114 are supplied with power supply voltages VPP and VPM. Referring to FIG. 9, VPP is a buffer circuit 80a.
Is supplied as a positive power supply voltage, and VPM is supplied as a negative power supply voltage.

Power supply voltage supply section 14 for negative differential signals
0b is also a positive differential signal power supply 140a.
It has the same or similar function and configuration. The switching unit 130 is provided in a stage preceding the power supply unit 140b for the negative differential signal. One input terminal of the switching unit 130 is connected to the DAC 92 via the protection circuit 144, and the other input terminal is grounded. The switching unit 130 operates in conjunction with the switching unit 128 described above. That is, when the switching unit 128 switches the connection to the ground input terminal side, the switching unit 130 also switches the connection to the ground input terminal side, and when the switching unit 128 switches the connection to the other input terminal, the switching unit 130 also switches the connection to the other input terminal. Switch to the input terminal. As described with respect to the power supply voltage supply unit for positive differential signal 140a, also in the power supply voltage supply unit for negative differential signal 140b, the power supply voltages VNP and VNP are applied to the output terminals 116 and 118, respectively.
Each of the NMs is provided. Referring to FIG.
Is supplied to the buffer circuit 80b as a positive power supply voltage, and VNP is supplied as a negative power supply voltage.

FIG. 11 shows another modification of the voltage supply circuit 90 shown in FIG. In this modification, a voltage generation circuit that generates an offset voltage Vpoffset and power supply voltages VPP and VPM, and a voltage generation circuit that generates an offset voltage Vnoffset and power supply voltages VNP and VNM have independent configurations. This voltage supply circuit 90
Includes DACs 92a and 92b, a power supply voltage supply unit 140a for positive differential signals, a power supply voltage supply unit 140b for negative differential signals, protection circuits 144a and 144b, and filters 146a and 146b. The power supply unit 140 for the positive differential signal includes a filter 148a, a voltage follower 104a, a Zener diode 106a,
8a, constant current circuit 110a, buffers 150a, 152
a and output terminals 112 and 114. Similarly,
The negative differential signal power supply voltage supply unit 140b includes a filter 148b, a voltage follower 104b, zener diodes 106b and 108b, a constant current circuit 110b, buffers 150b and 152b, and output terminals 116 and 118.
Having. In FIG. 11, the components denoted by the same or similar reference numerals as those in FIG. 10 are the same or similar configurations as the corresponding components in FIG. 10.

The DAC 92a receives a digital voltage shift signal for a positive differential signal, and outputs an analog positive voltage shift signal. On the other hand, DAC92
b receives a digital voltage shift signal for a negative differential signal and outputs an analog negative voltage shift signal. As described above, the voltage shift signal for the positive differential signal and the voltage shift signal for the negative differential signal are independently supplied to the voltage supply unit 90. As a result, the offset voltage Vpoffset, the power supply voltages VPP and VPM, and the offset voltage Vnoffset And power supply voltages VNP and VNM can be generated independently. Vpoffset, VPP, VPM and Vnoffset, VN generated independently
P and VNM are independently supplied to the analog signal processing circuit 100 shown in FIG.

Hereinafter, an invention in which the analog signal processing circuit 100 described above is applied will be described.

FIG. 12 is a block diagram of a semiconductor device test apparatus 200 for testing a device under test 210.
The semiconductor device test apparatus 200 includes a test signal generator 20.
2, a signal input / output unit 204, a waveform digitizer 206, and a measurement unit 208. During the test, the device under test 2
Reference numeral 10 is electrically connected to the signal input / output unit 204. When the device under test 210 is mounted on an IC package, the signal input / output unit 204 is electrically connected to pins of the device. In this embodiment, the device under test 21
0 may be an analog circuit.

The test signal generator 202 generates a test signal to be input to the device under test 210. The test signal generator 202 can generate an arbitrary test signal according to a test item. The signal input / output unit 204 receives the test signal and supplies the test signal to the device under test 210.
The device under test 210 outputs an analog signal as an output result based on the test signal. The output analog signal is supplied to the waveform digitizer 206 via the signal input / output unit 204. Waveform digitizer 206 converts an analog signal into a digital signal and outputs the digital signal to measurement section 208. The measuring unit 208 measures the quality of the device under test 210 based on the digital signal. Specifically, the measurement unit 208 determines whether the device under test 210 is good or not by comparing an expected value expected as a response of a normal device with a digital signal supplied from the waveform digitizer 206. it can. In FIG. 12, the device under test 210 includes a test signal generator 20.
2, the test signal is not necessarily input to the device under test 210. Whether or not a test signal is input to the device under test 210 depends on the type of the device under test 210. For example, if the device under test 210 is an analog element having an oscillator, the device under test 210 can be set up at the start of a test and then output an analog signal.

FIG. 13 shows an embodiment of the waveform digitizer 206 included in the semiconductor device test apparatus 200 shown in FIG. The waveform digitizer 206 includes an AD (analog / digital) converter 220 and a waveform memory 228.
And a clock generator 226. AD converter 2
Reference numeral 20 denotes an analog signal processing circuit 100, an anti-aliasin glow-pass filter 222, and an AD converter 2.
24. The anti-aliasin glow-pass filter 222 is an AD converter pre-filter provided to limit the band of the analysis analog signal to within the Nyquist frequency. In this embodiment, the analog signal (22a,
22b), but in another embodiment,
The analog signal need not be a differential signal.

The analog signal processing circuit 100 corresponds to the analog signal processing circuit 100 described with reference to FIGS. 4 to 11, and a detailed description of the analog signal processing circuit 100 will be omitted. Analog signal processing circuit 100
Outputs an analog voltage signal related to the voltage difference between the two analog signals 22a and 22b constituting the differential signal. The voltage signal is input to the anti-aliasin glow-pass filter 222. The anti-aliasin glow-pass filter 222 limits the band of the voltage signal to within the Nyquist frequency. The band-limited voltage signal is supplied to the AD converter 224. The AD converter 224 converts the voltage signal into a digital signal. Thus, the AD converter 220
Can convert analog signals (22a, 22b) into digital signals.

A clock generator 226 controls the operation of the AD converter 224 and the waveform memory 228. AD
Converter 224 samples an analog signal in synchronization with a clock supplied from clock generator 226, and waveform memory 228 stores a converted digital signal (data) in synchronization with the clock.
In the semiconductor device test apparatus 200 shown in FIG.
8 is read.

FIG. 14 shows an oscilloscope 240 for displaying or measuring the quantity of electricity of an object. The oscilloscope 240 includes an oscilloscope main body 242, contact terminals 244a and 244b, and a transmission path 246. The oscilloscope 242 includes a signal input circuit 70, a processing unit 250
And a display unit 252. In this embodiment, two contact terminals (244a, 244b) are provided,
In another embodiment, one or three or more contact terminals may be provided. Also, contact terminals (244a, 24
4b) is preferably formed by a conductor having a constant impedance.

In this embodiment, for example, the contact terminals 24
4a contacts the measurement point of the object, and the contact terminal 244b is grounded. The transmission line 246 includes the contact terminals 244a and 244a.
The electric signal input to the oscilloscope main body 2
42. At this time, the transmission path 246 is preferably a coaxial cable.

The electric signal is differentially input to the signal input circuit 70. The signal input circuit 70 corresponds to the signal input circuit 70 described with reference to FIGS.
A detailed description of 0 is omitted. In this embodiment, the signal input circuit 70 includes two signal input circuits 70a and 70b.

The output of the signal input circuit 70 is sent to the processing unit 250
Supplied to The processing section 250 preferably has, at the input section, the level shift section 60 having the constant impedance circuits 84a and 84b shown in FIG. Processing unit 25
0 processes the electric signal output from the signal input circuit 70. For example, the processing unit 250 performs a process for displaying a voltage waveform on the display unit 252. Display unit 252
Can display a voltage waveform or the like based on a signal sent from the processing unit 250.

The embodiment in which the analog signal processing circuit 100 according to the present invention is applied has been described with reference to FIGS. 12 to 14. However, the embodiment can be applied to other devices and the like. One feature of the analog signal processing circuit 100 according to the present invention is that the input impedance can be suitably changed, and the analog signal processing circuit 100 can be provided at an input section of various signal transmission paths.

As is clear from the above description, according to the present invention, it is possible to provide an analog signal processing circuit 100 having a variable input impedance. Further, according to the present invention, it is possible to provide devices such as an AD converter and an oscilloscope incorporating the analog signal processing circuit 100. As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such modifications or improvements are also included in the technical scope of the present invention.

[0083]

According to the present invention, it is possible to provide an analog signal processing circuit capable of changing the input impedance.

[Brief description of the drawings]

FIG. 1 shows a block diagram of a conventional differential signal processing circuit 10.

FIG. 2 shows a specific circuit configuration of a conventional differential signal processing circuit 10.

FIG. 3 is a diagram for explaining impedance switching performed in a conventional differential signal processing circuit 10.

FIG. 4 shows an analog signal processing circuit 100 for processing an analog signal according to the first embodiment of the present invention.

FIG. 5 is an analog signal processing circuit 100 for processing an analog signal that is a differential signal according to a second embodiment of the present invention.
Is shown.

FIG. 6 shows an example of a specific circuit diagram of an analog signal processing circuit 100 according to a second embodiment of the present invention.

7A shows the signal waveforms of the analog signals 22a and 22b, and FIG. 7B shows the signal waveform of the amplified signal 64 output based on the analog signals 22a and 22b shown in FIG. , (C) are analog signals 22a
And (b) show signal waveforms of the amplified signal 64 output based on the analog signal 22a shown in (c).

FIG. 8 shows a modified embodiment of the signal input circuit 70a shown in FIG.

FIG. 9 shows a modification of the specific circuit diagram of the analog signal processing circuit 100 according to the second embodiment of the present invention.

10 is an analog signal processing circuit 100 shown in FIG.
FIG. 1 shows an embodiment of a voltage supply circuit 90 for supplying power supply voltages (VPP, VPM, VNP, VNM) and offset voltages (Vpoffset, Vnoffset).

11 shows another modification of the voltage supply circuit 90 shown in FIG.

FIG. 12 shows a block diagram of a semiconductor device test apparatus 200 for testing a device under test 210.

13 is a semiconductor device test apparatus 2 shown in FIG.
1 shows an embodiment of a waveform digitizer 206 included in 00.

FIG. 14 illustrates an oscilloscope 240 that displays or measures an electrical quantity of an object.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Differential signal processing circuit, 12 ... Terminal resistance switching part, 14 ... Input buffer circuit, 16 ... Differential amplifier, 18 ... Level shift part, 20 ... Gain amplifier, 22, 22a, 22b ... analog signal, 24
..Voltage signals, 26, 26a, 26b ... shift voltage signals, 28a, 28b ... switching relays, 30a, 30
b: termination resistance, 32a, 32b: buffer, 3
4a, 34b, 36a, 36b ... resistance, 38, 40
... Op amp, 48a ... Input resistance, 50, 50
a, 50b ... input terminals, 52, 52a, 52b ...
-Input switching unit, 54, 54a, 54b ... high impedance input path, 56, 56a, 56b ... low impedance input path, 58, 58a, 58b ... output switching unit, 60 ... level shift unit , 62 ... amplifier
64: amplified signal, 70, 70a, 70b: signal input circuit, 72a, 72b, 72c, 72d, 72e,
72f: resistor, 74a, 74b: operational amplifier,
76 ... switching relay, 78 ... -Voffset supply unit,
78a ... Vpoffset supply unit, 78b ... Vnoffs
et supply unit, 80a, 80b... buffer circuit, 82
a, 82b: resistor, 84a, 84b: constant impedance circuit, 90: voltage supply circuit, 92: D
AC (digital / analog converter), 94 ...
Resistance, 96: Zener diode part, 98a, 98
b: resistor, 100: analog signal processing circuit, 1
02a, 102b ... capacitance, 104a, 1
04b ... voltage follower, 106a, 106b, 10
8a, 108b ... Zener diode, 110a,
110b ... constant current circuit, 112, 114, 116,
118 output terminal, 120, 124 resistance, 1
22 ... operational amplifier, 126 ... capacitance,
128: ground switching unit, 130: ground switching unit, 132, 134: output terminal, 140a: power supply voltage unit for positive differential signal, 140b: power supply voltage for negative differential signal Supply unit, 142 ... offset voltage supply unit, 144, 144a, 144b ...
Protection circuit, 146, 146a, 146b ... filter, 148a, 148b ... filter, 150a, 1
50b, 152a, 152b ... buffer, 200
..Semiconductor device test equipment, 202 ... test signal generator, 204 ... signal input / output unit, 206 ... waveform digitizer, 208 ... measurement unit, 210 ... device under test, 220 ...・ AD (analog / digital)
Conversion device, 222: anti-aliasing glow-pass filter, 224: AD converter, 226 ...
Clock generator, 228 ... waveform memory, 240 ...
・ Oscilloscope, 242 ・ ・ ・ Oscilloscope body,
244a, 244b: contact terminal, 246: transmission line, 250: processing unit, 252: display unit

Claims (18)

[Claims] 1. An analog signal processing circuit for processing an analog signal, comprising: an input terminal to which the analog signal is input; and a high impedance input path having a predetermined input impedance provided for the input terminal. A low-impedance input path provided for the input terminal and having an input impedance lower than the high-impedance input path, and the analog signal passing through one of the high-impedance input path and the low-impedance input path. An analog signal processing circuit, comprising: an output switching unit for outputting. 2. The input device according to claim 2, wherein the analog signal is a differential signal, two input terminals to which two signals constituting the differential signal are input, and the high terminal provided for each of the input terminals. The analog signal processing circuit according to claim 1, further comprising an impedance input path, the low impedance input path, and the output switching unit. 3. An input switching unit for supplying the analog signal input to the input terminal to one of the high impedance input path and the low impedance input path. 5. The analog signal processing circuit according to claim 1. 4. The analog signal processing circuit according to claim 1, wherein said high impedance input path includes a buffer circuit. 5. The power supply device according to claim 5, wherein the output switching unit is electrically connected to the output switching unit.
The analog signal processing circuit according to any one of claims 1 to 4, further comprising a constant impedance circuit having a predetermined impedance. 6. The high impedance input path further includes a resistor for connecting the low impedance input path and the ground, wherein the resistance and the predetermined impedance in the constant impedance circuit are higher than the input impedance of the high impedance input path. The analog signal processing circuit according to claim 5, wherein the analog signal processing circuit has a low impedance. 7. The analog signal processing circuit according to claim 4, further comprising a level shift unit that removes a predetermined voltage from at least one of the signals output by the output switching unit. 8. The analog signal processing circuit according to claim 7, wherein the level shift unit removes the predetermined voltage from both signals output from the output switching unit. 9. The analog signal processing circuit according to claim 7, wherein the level shifter removes the predetermined voltage from only one of the signals output from the output switch. 10. The analog according to claim 7, wherein said level shift unit includes a constant impedance circuit having a predetermined impedance and electrically connected to said output switching unit. Signal processing circuit. 11. The analog signal processing circuit according to claim 4, wherein a power supply voltage of said buffer circuit is varied based on an offset voltage of said analog signal. 12. The apparatus according to claim 7, further comprising an amplifier for amplifying an output of said level shift unit.
The analog signal processing circuit according to any one of the above. 13. An AD converter for converting an analog signal input as a differential signal into a digital signal, comprising: two input terminals to which two signals constituting the differential signal are input; A high impedance input path having a predetermined input impedance provided for each of the terminals; a low impedance input path having a lower input impedance than the high impedance input path, provided for each of the input terminals; An output switching unit that is provided for each of the input terminals and that outputs the analog signal through one of the high impedance input path and the low impedance input path; and A differential amplifier that outputs a voltage signal based on a voltage difference between the analog signals, An AD converter, comprising: an AD converter that converts the voltage signal into a digital signal. 14. The A / D converter according to claim 13, further comprising a constant impedance circuit having a predetermined impedance and electrically connected to each of said output switching units. 15. The high-impedance input path further includes a resistor connecting the impedance input path and ground, wherein the resistance and the predetermined impedance in the constant impedance circuit are lower than the input impedance of the high impedance input path. The AD converter according to claim 14, wherein the AD converter constitutes an impedance. 16. A semiconductor device test apparatus for testing a device under test, a waveform digitizer for converting an analog signal output from the device under test to a digital signal, and the device under test based on the digital signal. A measurement unit for measuring pass / fail of the input terminal, wherein the waveform digitizer includes: an input terminal to which the analog signal is input; a high impedance input path having a predetermined input impedance provided to the input terminal; Outputting the analog signal passing through one of the high-impedance input path and the low-impedance input path, the low-impedance input path having a lower input impedance than the high-impedance input path, provided to the terminal; An output switching unit, and the output switching unit The analog signal al outputted, the semiconductor device testing apparatus, characterized in that it comprises an AD converter for converting the digital signal. 17. The high impedance input, wherein the waveform digitizer is provided for each of the two input terminals to which two signals constituting the analog signal that is a differential signal are input, and for each of the input terminals. A low-impedance input path and the output switching unit; a differential amplifier that outputs a voltage signal based on a voltage difference between the analog signals output from the output switching unit; and 17. The semiconductor device test apparatus according to claim 16, further comprising an AD converter for performing conversion. 18. A signal input circuit for receiving at least one contact terminal, a transmission path for transmitting an electric signal input to the contact terminal, the signal input circuit receiving the electric signal transmitted by the transmission path, and the signal input. An oscilloscope including a processing unit that processes the electric signal input to a circuit, wherein the signal input circuit includes: an input terminal to which the electric signal is input; and a predetermined input provided for the input terminal. A high-impedance input path having impedance; a low-impedance input path provided for the input terminal, having a lower input impedance than the high-impedance input path; and any one of the high-impedance input path or the low-impedance input path The electric signal passing through one side,
An oscilloscope comprising: an output switching unit that outputs the signal to the processing unit.