JP3320946B2 - Test equipment for signal receivers - Google Patents

Test equipment for signal receivers

Info

Publication number
JP3320946B2
JP3320946B2 JP12702295A JP12702295A JP3320946B2 JP 3320946 B2 JP3320946 B2 JP 3320946B2 JP 12702295 A JP12702295 A JP 12702295A JP 12702295 A JP12702295 A JP 12702295A JP 3320946 B2 JP3320946 B2 JP 3320946B2
Authority
JP
Japan
Prior art keywords
signal
circuit
reference potential
signal receiving
receiving device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12702295A
Other languages
Japanese (ja)
Other versions
JPH08307171A (en
Inventor
幸成 土屋
健司 馬場
泉 滝沢
修一 島田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Totoku Electric Co Ltd
Original Assignee
Totoku Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Totoku Electric Co Ltd filed Critical Totoku Electric Co Ltd
Priority to JP12702295A priority Critical patent/JP3320946B2/en
Publication of JPH08307171A publication Critical patent/JPH08307171A/en
Application granted granted Critical
Publication of JP3320946B2 publication Critical patent/JP3320946B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Amplifiers (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、信号発生装置と情報処
理装置、情報表示装置或いは電気/光変換器等の信号受
信装置や信号再生装置との間の伝送路にされ用いら
、信号発生装置からの信号の基準電位を所要の基準電
位に変換設定して信号受信装置や信号再生装置に伝送す
る信号受信装置用試験装置に関するもので、特に信号
受信装置や信号再生装置に入力される信号の基準電位を
種々の電位に変換設定可能で、当該装置の動作確認を行
うに有用な信号受信装置用試験装置に関するものであ
る。
The present invention relates to a signal generating device and the information processing apparatus, an information display device or al used is disposed on the transmission path between the signal receiving apparatus and a signal reproducing apparatus for an electric / optical converter, etc.
It is, relates to signal receiving apparatus for testing devices to be transmitted to the conversion settings to signal receiving apparatus and a signal reproducing apparatus a required reference potential reference potential of the signal from the signal generator, particularly a signal receiving apparatus and a signal reproducing apparatus The present invention relates to a test device for a signal receiving device , which can convert and set a reference potential of a signal input to a device to various potentials, and is useful for confirming operation of the device.

【0002】[0002]

【従来の技術】通常、信号発生装置と信号受信装置或い
は信号再生装置とは各装置における信号の基準電位が同
なるよう設定され、システムが組まれている。一般
信号発生装置の基準電位はグランドレベルに設定さ
れ、それに対応して信号受信装置の基準電位もグランド
レベルに設定されている。ところが、信号発生装置によ
っては、システムを組むときに、伝送信号の基準電位を
信号発生装置に固有の特定レベル、稀には十数Vとい
った基準電位に設定るような場合もある。しかも、そ
の基準電位の可変電位幅高々1〜2V程度と極めて小
さなものある。
2. Description of the Related Art Usually, a signal generating device and a signal receiving device or a signal reproducing device are set so that the reference potential of a signal in each device is the same , and a system is assembled. Generally , the reference potential of the signal generator is set to the ground level, and the reference potential of the signal receiver is set to the ground level correspondingly. However, depending on the signal generator, the reference potential of the transmission signal may be reduced when assembling the system.
Specific particular level to the signal generator, the rare, there are also cases so that to set the reference potential such as a dozen V. Moreover, the variable potential range of the reference potential is at most extremely small as about 1 to 2 V.

【0003】従って、信号受信装置が異なる基準電位の
信号発生装置と組み合わせられ使用され場合に想定さ
れる問題点、即ち信号受信装置側でインタフェース整合
をとる必要があるかどうか、インタフェース整合をと
らなかった場合信号発生装置に設定されている基準電位
によ信号受信装置が特性上、信頼性上どのような影響
を受けるか等について、実働条件と同じ条件で試験し
ておくことが必要である。
[0003] Therefore, a problem that is assumed when the signal receiving apparatus is used in combination with signal generating device of a different reference potential, whether i.e. the need to interface matching the signal receiving apparatus, an interface matching If not taken signal generator by Ri signal receiving apparatus to a reference potential <br/> set in the on properties, whether from undergoing any influence on the reliability and the like, and tested under the same conditions as production conditions it kept the Ru need der.

【0004】しかしながら、これまで、信号発生装置
出力された信号の基準電位を伝送路中で所要の基準電
位に変換設定して信号受信装置に入力でき装置等が
かったため、種々異なった基準電位の信号が入力された
場合の信号受信装置の動作確認し、信号受信装置に
回路設計うこと事は困難であった。
[0004] However, so far, whether the signal generator
Since al the signal output required you can enter by converting set to the reference potential to the signal receiving apparatus apparatus in the transmission line in a reference potential such tinged Do <br/>, the signal of the reference potential Tsu various different to check the operation of the signal receiving apparatus when the inputted lowest <br/> optimal circuit design lines Ukoto it is difficult to the signal receiving apparatus.

【0005】[0005]

【発明が解決しようとする課題】信号発生装置から出力
される信号の基準電位と信号受信装置に入力される信号
の基準電位と異ならせたままシステムを動作させた場
には、信号発生装置と信号受信装置のインタフェー
整合により、信号受信装置での正確な信号再生が
しくなるほか、信号受信装置内の入力インタフェース回
路に過大な電流が流れて回路部品の電力容量を超過する
結果、回路部品の過熱による特性変動や焼損事故を生
るといった不測の事態を招く恐れがあった。
SUMMARY OF THE INVENTION Output from a signal generator
The case of operating the system while keeping different et a reference potential of the signal inputted to the reference potential and a signal receiving apparatus of a signal is by the interface mismatch between the signal generator and the signal receiving apparatus, the signal receiving It is difficult to accurately reproduce signals on the device
Properly composed addition, the results that exceed the power capacity of the input interface circuit CC an excessive current flows in in the signal receiving apparatus, the characteristic variations or burning accidents due to overheating of the circuit components raw Ji <br/> Rutoitta contingencies There was a danger of a situation.

【0006】そこで、本発明の目的とするところは、信
号受信装置へ入力される信号の基準電位を所要の基準電
位に変換設定すること出来る信号受信装置用試験装置
を提供し、信号受信装置の最適設計を行えるようにする
ことにある。
[0006] Accordingly, it is an object of the present invention is to provide a signal receiving apparatus for testing device capable of converting set the reference potential of the signal inputted to the signal receiving apparatus to the required reference voltage, the signal reception apparatus there is the optimum design to be so as to obtain a row.

【0007】[0007]

【課題を解決するための手段】本発明は、信号発生装置
と信号受信装置間の伝送路に配置され用いられる信
号受信装置用試験装置であって、信号発生装置からの
信号S1の波形を整合する入力インピーダンス整合回路
と、この整合された信号S3を所要のレベルに増幅する信
号補正回路と、前記信号補正回路3により増幅された
信号S4の基準電位を所要の基準電位に変換設定する基準
電位設定用調整手段VR1,VR2を具備する基準電位設定回
と、前記所要の基準電位に設定された信号S5の電力
を増幅するバッファ回路と、前記バッファ回路から
の信号S6の波形を整合する出力インピーダンス整合回路
と、前記各回路2,3,6,7電源電圧Vcc,Veeを供給する
電源回路と、をケースC内に一体に収納するととも
に、前記基準電位設定用調整手段VR1,VR2を前記ケース
C面に配設したことを特徴とする信号受信装置用試験
置にある。
SUMMARY OF THE INVENTION The present invention provides a signal generator.
S and a signal used in the transmission path between the signal receiving device T
A No. receiving apparatus for testing devices, input impedance matching circuit for matching the waveform of the signal S1 from the signal generator S 2
A signal correction circuit 3 for amplifying the matched signal S3 to a required level; and a reference for converting and setting a reference potential of the signal S4 amplified by the signal correction circuit 3 to a required reference potential.
A reference potential setting circuit 6 including potential setting adjusting means VR1 and VR2, a buffer circuit 7 for amplifying the power of the signal S5 set to the required reference potential, and a waveform of a signal S6 from the buffer circuit 7 Output impedance matching circuit to match
8 and a power supply circuit 9 for supplying a power supply voltage Vcc, Vee to each of the circuits 2, 3 , 6 , 7 are integrally housed in a case C.
The reference potential setting adjusting means VR1 and VR2 are
A test device for a signal receiving device, which is disposed on a C-plane .

【0008】[0008]

【作用】[Action] 本発明の信号受信装置用試験装置は、電源回路The test apparatus for a signal receiving apparatus according to the present invention includes a power supply circuit.
9を具備するほか、基準電位設定用調整手段VR1,VR2を9 and the reference potential setting adjusting means VR1 and VR2.
ケースC面に設けたので、信号発生装置Sと信号受信装The signal generator S and the signal receiver are provided on the surface of the case C.
置T間の伝送路に独立して配置できるとともに、信号発Can be placed independently on the transmission path between
生装置Sや信号受信装置Tを改造することなく、信号発Without modifying the raw device S or the signal receiving device T,
生装置Sから出力される信号S1の基準電位を所望の電位The reference potential of the signal S1 output from the generator S
に変換設定して信号受信装置Tに伝送することができCan be set and transmitted to the signal receiving device T.
る。You. また、信号振幅調整機能を有する信号補正回路3にIn addition, the signal correction circuit 3 having a signal amplitude adjustment function
より入力信号S1と出力信号S2の特性、品質を全く同一にThe characteristics and quality of the input signal S1 and output signal S2 are exactly the same
設定できるので、種々異なる基準電位の入力信号S1に対Since it can be set, it can respond to the input signal S1 of various reference potentials.
する信号受信装置Tの動作状態を予め確認可能なほか、In addition to confirming the operating state of the signal receiving device T
信号受信装置Tの入力インターフェイス部に流れる電流Current flowing through the input interface of the signal receiving device T
値を実測できるので、回路部品の特性変動や焼損事故等Since the measured values can be measured, the characteristics of circuit components may fluctuate,
のトラブルを未然に防止できるよう信号発生装置SからFrom the signal generator S so that troubles can be prevented beforehand.
出力される信号S1の基準電位に適応した信号受信装置TSignal receiving device T adapted to the reference potential of output signal S1
の最適設計が可能になり、信号受信装置の品質を向上さThe optimal design of the signal receiver and improve the quality of the signal receiver.
せることができる。Can be made.

【0009】[0009]

【実施例】【Example】 以下、本発明の実施例を図1,図2により詳Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS.
細に説明する。図1は本発明の信号受信装置用試験装置This will be described in detail. FIG. 1 shows a test apparatus for a signal receiving apparatus according to the present invention.
の要部回路構成を示す説明図であり、図2は本発明の信FIG. 2 is an explanatory diagram showing a circuit configuration of a main part of FIG.
号受信装置用試験装置の構成を示すブロック図である。FIG. 2 is a block diagram illustrating a configuration of a test device for a signal receiving device.
実施例では、入力信号はR,G,Bの映像コンポジット信号In the embodiment, the input signal is an R, G, B video composite signal.
で、信号レベルが1.0Vp-p、入力信号の基準電位が映像The signal level is 1.0 Vp-p and the reference potential of the input signal is
のペデスタルレベルがグランドレベルの場合について説Of the pedestal level at the ground level
明する。I will tell. なお、本発明はこの実施例に限定されるものでNote that the present invention is limited to this embodiment.
はない。There is no.

【0010】[0010] 図において、1は信号受信装置用試験装置In the figure, reference numeral 1 denotes a test device for a signal receiving device.
を構成する要部回路であり、SW1,SW2はトグルスイッチSW1 and SW2 are toggle switches.
等からなる切替えスイッチで信号発生装置Sから要部回Switch from the signal generator S to the main part
路1に入力される信号S1を信号受信装置Tに直接、あるThe signal S1 input to the path 1 is directly transmitted to the signal receiving device T.
いは要部回路1を経由して伝送するよう切替えることがOr switching to transmit via main circuit 1
できる。it can. そして、例えば、要部回路1に75Ω系同軸ケーThen, for example, a 75Ω coaxial cable is
ブルの伝送路を介して入力された信号S1は、抵抗値が75The signal S1 input via the transmission line of the
Ωの入力インピーダンス整合用の抵抗R1からなる入力イΩ input impedance matching resistor R1
ンピーダンス整合回路2で、信号S1の反射減衰を防ぎ波Impedance matching circuit 2 prevents the return loss of signal S1
形歪みが最小となるよう整合される。Matching is performed to minimize shape distortion. なお、信号S1がR,Note that the signal S1 is R,
G,Bからなる複数の伝送路による場合は、それぞれの伝When using multiple transmission lines consisting of G and B,
送路に対応して要部回路1を設ければよい。The main circuit 1 may be provided corresponding to the transmission path.

【0011】[0011] 入力インピーダンス整合回路2で整合されMatched by input impedance matching circuit 2
出力された信号S3は、オペアンプIC1と抵抗R2,トリマThe output signal S3 is composed of the operational amplifier IC1, resistor R2, and trimmer.
抵抗等からなる可変抵抗VR3とで構成した信号補正回路A signal correction circuit composed of a variable resistor VR3 consisting of a resistor, etc.
3に入力され、入力信号S1と後述する要部回路1からの3 and an input signal S1 from a main circuit 1 described later.
出力信号S2の信号レベルが特性、品質において同等となThe signal level of the output signal S2 is equal in characteristics and quality.
るよう信号レベルを補正されるとともに増幅される。The signal level is corrected and amplified as described above. What
お、信号補正回路3の入力端における信号3の信号レThe signal level of the signal 3 at the input terminal of the signal correction circuit 3
ベルは1.0Vp-pであり、基準電位は映像のペデスタルレThe bell is 1.0 Vp-p, and the reference potential is the pedestal level of the image.
ベルがグランドレベルである。Bell is at ground level. 具体的には、例えば、後Specifically, for example, after
述するバッファ回路7の出力端で75Ω系同軸ケーブル75Ω coaxial cable at the output end of buffer circuit 7
線路とインピーダンスマッチングさせるには75Ωで終端Terminate at 75Ω for impedance matching with line
させる必要がある。こNeed to be done. This の場合、出力信号S2には1.0Vp-pIn the case of, the output signal S2 is 1.0Vp-p
のレベルが必要なため、出力端における信号レベルはSignal level at the output end
2.0Vp-pになる。2.0 Vp-p. 従って、信号補正回路3の出力端にTherefore, at the output terminal of the signal correction circuit 3,
おける信号レベルも2.0Vp-pになり、信号補正回路3でSignal level becomes 2.0Vp-p.
は入力端における信号レベル1.0Vp-pを2倍に増幅すAmplifies the signal level 1.0Vp-p at the input terminal twice
る必要がある。Need to be なお、オペアンプIC1による増幅率は抵The amplification factor of the operational amplifier IC1 is
抗R2と可変抵抗VR3により設定され、出力端の信号レIt is set by the anti-R2 and the variable resistor VR3.
ベルを2.0Vp-pに設定するため、実施例では、R2を1KIn order to set the bell to 2.0Vp-p, in the embodiment, R2 is set to 1K
Ω、VR3を2KΩに選定している。Ω and VR3 are selected as 2KΩ.

【0012】[0012] 信号補正回路3で増幅され出力された信号The signal amplified and output by the signal correction circuit 3
S4は、コンデンサC1,C2からなりオペアンプIC1と後段のS4 is composed of capacitors C1 and C2 and
バッファアンプIC2とを交流結合するAC結合回路4と、An AC coupling circuit 4 for AC coupling with the buffer amplifier IC2;
抵抗R3,R4,トリマ抵抗からなる可変抵抗VR1,VR2によるVariable resistors VR1 and VR2 consisting of resistors R3 and R4 and trimmer resistors
バイアス回路5とで構成される基準電位設定回路6におThe reference potential setting circuit 6 composed of the bias circuit 5
いて所望の基準電位に変換設定される。Then, it is converted and set to a desired reference potential. なお、並列接続In addition, parallel connection
されてAC結合回路4を構成するコンデンサC1,C2の容量And the capacitance of the capacitors C1 and C2 constituting the AC coupling circuit 4.
値としては、コンポジット信号が垂直同期信号の数十HzAs a value, the composite signal is several tens of Hz of the vertical synchronization signal.
から映像信号のドットクロックの数十MHzまでの帯域をUp to tens of MHz of the dot clock of the video signal
もつため、コンデンサC2は高帯域信号を通過させる0.1Capacitor C2 is 0.1
μFに、コンデンサC1は低帯域信号を通過させる330μFμF, capacitor C1 is 330μF to pass low band signals
に選定されている。Has been selected. また、オペアンプIC1で増幅され出The output is amplified by the operational amplifier IC1.
力された信号S4は、AC結合回路4でDCレベルをカットさThe input signal S4 has its DC level cut by the AC coupling circuit 4.
れ、コンポジット信号の平均値をグランドレベルとしたThe average value of the composite signal is set to the ground level.
信号としてバイアス回路5に入力され、バイアス回路5The signal is input to the bias circuit 5 as a signal.
において直流分を重畳される。Is superimposed with a DC component. また、バイアス回路5Also, the bias circuit 5
は、信号S1の基準電位を所望の基準電位に変換設定するConverts the reference potential of the signal S1 to a desired reference potential
回路であり、抵抗R3,R4や可変抵抗VR1,VR2の抵抗値を選Select the resistance value of resistors R3 and R4 and variable resistors VR1 and VR2.
択して信号の基準電位を選定可能である。Alternatively, the reference potential of the signal can be selected. 実施例では、In the example,
抵抗R3,R4が6.8KΩ、可変抵抗VR1,VR2が10KΩに選定Select resistors R3 and R4 as 6.8KΩ and variable resistors VR1 and VR2 as 10KΩ
されており、信号S1の基準電位を+6V〜−6Vの範囲でAnd the reference potential of the signal S1 is set within a range of + 6V to -6V.
変換設定可能で、AC結合回路4とバイアス回路5からなConversion setting is possible, and the AC connection circuit 4 and the bias circuit 5
る基準電位設定回路6の出力端には基準電位が変換設A reference potential is converted at the output terminal of the reference potential setting circuit 6.
定された信号S5が出力される。The specified signal S5 is output.

【0013】[0013] そして、基準電位設定回路6から出力されThe output from the reference potential setting circuit 6
た信号S5は、信号S1が要部回路1をThe signal S5 is the signal S1 伝送中に低減する信Signals reduced during transmission
号の電力を増幅するバッファアンプIC2からなるバッフBuffer consisting of a buffer amplifier IC2 that amplifies the signal power
ァ回路7で信号電力を増幅され、信号S6として出力されThe signal power is amplified by the filter circuit 7 and output as a signal S6.
る。バッファ回路7から出力される信号S6は、出力インYou. The signal S6 output from the buffer circuit 7 is
ピーダンス整合用の抵抗で抵抗値が入力インピーダンスResistance value is input impedance with resistance for impedance matching
整合用の抵抗R1と同じ75Ωの抵抗R5からなる出力インピAn output impedance consisting of the same 75Ω resistor R5 as the matching resistor R1
ーダンス整合回路8を経由し、基準電位を所望の基準電The reference potential is passed through the inductance matching circuit 8 to the desired reference potential.
位に変換設定させた出力信号S2として受信装置Tに伝送To receiver T as output signal S2 converted to
される。Is done. なお、バッファアンプIC2については、例えFor buffer amplifier IC2,
ば、出力信号S2の基準電位が+6Vであれば、終端抵抗RIf the reference potential of the output signal S2 is + 6V, the termination resistor R
5の抵抗値が75Ωなので、バッファ回路7の出力端にSince the resistance value of 5 is 75Ω, the output terminal of the buffer circuit 7
は+12Vが必要である。Requires + 12V. 即ち、負荷150Ω(終端抵抗R5のThat is, a load of 150Ω (termination resistor R5
75Ωと負荷側の75Ω)を+12Vで駆動させる必要がある75Ω and 75Ω on the load side) need to be driven by + 12V
ため、バッファアンプIC2には最低80mA(12V/150Ω)Therefore, at least 80mA (12V / 150Ω) for buffer amplifier IC2
の電流を流さなければならない。Current must flow. そこで、負荷150Ω時Therefore, when the load is 150Ω
をも想定し、バッファアンプIC2には約±230mAの駆動Assuming that the buffer amplifier IC2 drives about ± 230mA
能力のあるアンプを選定する必要がある。It is necessary to select a capable amplifier.

【0014】[0014] 一方、信号受信装置用試験装置を構成するOn the other hand, a test device for a signal receiving device is configured.
各回路2,3,6,7に駆動用電力を供給する電源回路9からFrom a power supply circuit 9 that supplies driving power to each of the circuits 2, 3, 6, and 7
出力される電源電圧Vee,Vccは、それぞれ出力信号S2のThe output power supply voltages Vee and Vcc are
基準電位の2倍以上でなければならない。It must be at least twice the reference potential.

【0015】[0015] このような構成の信号受信装置用試験装置Test apparatus for a signal receiving device having such a configuration
は、要部回路1がケースC内に一体に収納されるとともMeans that the main circuit 1 is housed integrally in the case C
に、基準電位設定回路6の可変抵抗VR1,VR2がケースC面The variable resistors VR1 and VR2 of the reference potential setting circuit 6 are
に取り付けられたので、信号受信装置用試験装置をコンThe test equipment for the signal receiver was connected to the
パクトにできるほか、基準電位の設定が簡単に行える。In addition to being able to reduce the impact, the reference potential can be easily set.

【0016】[0016]

【発明の効果】【The invention's effect】 本発明によれば、信号発生装置と信号受According to the present invention, a signal generator and a signal receiver are provided.
信装置間の伝送路に信号受信装置用試験装置を配設し、The test equipment for the signal receiving device is installed on the transmission line between the receiving devices,
信号発生装置による信号の基準電位を所望の電位に変換Convert the reference potential of the signal by the signal generator to the desired potential
設定して信号受信装置に簡単に伝送できるので、種々異It can be easily set and transmitted to the signal receiving device.
なる基準電位の入力信号に対する信号受信装置の動作状Of signal receiving device for input signal of different reference potential
態を予め確認することができるほか、信号受信装置の入Status can be checked in advance, and the signal receiver can be turned on.
力インターフェイス部に流れる電流値の実測も可能になMeasurement of the current flowing through the force interface is also possible.
る。You. この結果、回路部品の特性変動や焼損事故等のトラAs a result, traffic fluctuations in circuit component characteristics and burnout
ブルを未然に防止できるよう、信号受信装置を構成するConfigure a signal receiving device to prevent
各回路の最適設計が可能になる。また、信号受信装置にOptimal design of each circuit becomes possible. In addition, signal receivers
DC再生回路等が必要かどうかの確認も可能なので、信号It is also possible to check whether a DC regeneration circuit or the like is necessary.
受信装置の品質を大幅に向上することができる。等そのThe quality of the receiving device can be greatly improved. Etc.
実用上の効果は極めて大きなものがある。Practical effects are extremely large.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の信号受信装置用試験装置の要部回路構
を示す説明図でる。
FIG. 1 is a main circuit diagram of a test apparatus for a signal receiving apparatus according to the present invention.
Out explanatory view showing the formation.

【図2】FIG. 2 本発明の信号受信装置用試験装置の構成を示す1 shows a configuration of a test device for a signal receiving device of the present invention.
ブロック図である。It is a block diagram.

【符号の説明】[Explanation of symbols]

要部回路 2 入力インピーダンス整合回路 3 信号補正回路 4 AC結合回路 5 バイアス回路 6 基準電位設定回路 7 バッファ回路 8 出力インピーダンス整合回路 9 電源回路 S1,S2,S3,S4,S5,S6 信号 SW1,SW2 切替えスイッチ R1,R2,R3,R4,R5, 抵抗 VR1,VR2 可変抵抗 C1,C2 コンデンサ IC1 オペアンプ IC2 バッファアンプ Vee,Vcc 電源電圧1 main circuit 2 input impedance matching circuit 3 signal correction circuit 4 AC coupling circuit 5 bias circuit 6 reference potential setting circuit 7 buffer circuit 8 output impedance matching circuit 9 power supply circuit S1, S2 , S3, S4, S5, S6 signal SW1, SW2 selector switch R1, R2, R3, R4, R5, resistor VR1, VR2 variable resistor C1, C2 capacitor IC1 operational amplifier IC2 buffer amplifier Vee, Vcc power supply voltage

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−159805(JP,A) 特開 平5−175757(JP,A) 特開 昭61−248606(JP,A) (58)調査した分野(Int.Cl.7,DB名) H03G 1/00 - 3/18 H03F 1/42 - 1/56 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-159805 (JP, A) JP-A-5-175757 (JP, A) JP-A-61-248606 (JP, A) (58) Field (Int.Cl. 7 , DB name) H03G 1/00-3/18 H03F 1/42-1/56

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 信号発生装置と信号受信装置間の伝
送路に配置され用いられる信号受信装置用試験装置であ
って、 信号発生装置からの信号S1の波形を整合する入力イン
ピーダンス整合回路と、前記 整合された信号S3を所要のレベルに増幅する信号補
正回路と、 前記信号補正回路3により増幅された信号S4の基準電位
を所要の基準電位に変換設定する基準電位設定用調整手
段VR1,VR2を具備する基準電位設定回路と、 前記所要の基準電位に設定された信号S5の電力を増幅す
るバッファ回路と、 前記バッファ回路からの信号S6の波形を整合する出力
インピーダンス整合回路と、 前記回路2,3,6,7電源電圧Vcc,Veeを供給する電源回路
と、をケースC内に一体に収納するとともに、前記基準電位
設定用調整手段VR1,VR2を前記ケースC面に配設した
とを特徴とする信号受信装置用試験装置。
1. A test apparatus for a signal receiving device which is arranged and used in a transmission path between a signal generating device S and a signal receiving device T.
I, an input impedance matching circuit 2 for matching the waveform of the signal S1 from the signal generator S, a signal correction circuit 3 for amplifying the signal S3 the matched to the required level, are amplified by the signal correction circuit 3 adjusting hand reference potential setting the reference potential of the signal S4 is converted set to a required reference potential was
A reference potential setting circuit 6 including stages VR1 and VR2; a buffer circuit 7 for amplifying the power of the signal S5 set to the required reference potential; and an output impedance for matching the waveform of the signal S6 from the buffer circuit 7 a matching circuit 8, the power supply voltage Vcc to the circuit 2, 3, 6, 7, a power supply circuit for supplying a Vee
And 9 are integrally accommodated in a case C, and the reference potential
A test apparatus for a signal receiving apparatus , wherein setting adjusting means VR1 and VR2 are disposed on the case C surface .
JP12702295A 1995-04-27 1995-04-27 Test equipment for signal receivers Expired - Fee Related JP3320946B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12702295A JP3320946B2 (en) 1995-04-27 1995-04-27 Test equipment for signal receivers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12702295A JP3320946B2 (en) 1995-04-27 1995-04-27 Test equipment for signal receivers

Publications (2)

Publication Number Publication Date
JPH08307171A JPH08307171A (en) 1996-11-22
JP3320946B2 true JP3320946B2 (en) 2002-09-03

Family

ID=14949755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12702295A Expired - Fee Related JP3320946B2 (en) 1995-04-27 1995-04-27 Test equipment for signal receivers

Country Status (1)

Country Link
JP (1) JP3320946B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100415118B1 (en) * 1999-12-29 2004-01-13 삼성전자주식회사 Apparatus for amplifying received signal and control method of receiver in mobile station
US8159312B2 (en) * 2007-06-27 2012-04-17 Medrelief Inc. Method and system for signal coupling and direct current blocking

Also Published As

Publication number Publication date
JPH08307171A (en) 1996-11-22

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