WO1999004384A1

WO1999004384A1 - Liquid crystal device, method for driving the same, and projection display and electronic equipment made using the same

Info

Publication number: WO1999004384A1
Application number: PCT/JP1997/003600
Authority: WO
Inventors: Toru Aoki
Original assignee: Seiko Epson Corporation
Priority date: 1997-07-14
Filing date: 1997-10-08
Publication date: 1999-01-28
Also published as: JP3704716B2; US6266039B1

Abstract

A liquid crystal device which can reduce the deterioration of the picture quality caused by optical crosstalk. Data signals supplied to a data signal line (Sn) change within the range of the negative data voltage amplitude between a first potential (B1) and a second potential (W2) when a negative voltage is applied across a liquid crystal layer, and change within the range of the positive data voltage amplitude between a third potential (W2) and a fourth potential (B2) when a positive voltage is applied across the liquid crystal layer. The data signal line (Sn) is precharged with a negative precharging potential (PV1) or a positive precharging potential (PV2) before the data signals are supplied to the line (Sn). The positive and the negative precharging potentials are asymmetrically set with respect to the center potential (VC) of the data voltage amplitude between the first and the fourth potentials. In addition, the negative precharging potential (PC1) is set closed to the first potential (B1) than the center potential (VC1) of the positive data voltage amplitude.

Description

Patent application title: Liquid crystal device and driving method thereof, and projection display device and electronic apparatus using the same

[Technical field] -

The present invention relates to a liquid crystal device and a driving method thereof, and a projection display device and an electronic apparatus using the same.

[Background technology]

For example, in an active matrix type liquid crystal device, an operation of writing data to a liquid crystal layer of each pixel through a switching element such as a TFT (thin film transistor) connected to one scanning signal line is performed by dot sequential driving. I have.

In addition, in order to eliminate display unevenness due to bias of the voltage applied to the liquid crystal and to prevent deterioration of the liquid crystal due to the DC current applied to the liquid crystal, a polarity inversion drive for inverting the polarity of the voltage applied to the liquid crystal at a predetermined timing is performed. Have been done.

The polarity inversion drive is a drive in which a voltage of a different polarity (positive or negative polarity) is applied to one end of the liquid crystal with reference to a potential applied to the other end of the liquid crystal. It should be noted that “polarity” in the present specification means the polarity of a voltage applied to both ends of the liquid crystal. In order to drive the polarity inversion, in an active matrix type using a TFT, the potential applied to the common electrode facing the pixel electrode with the liquid crystal interposed is changed, or the voltage amplitude of the image data signal applied to the pixel electrode The potential level of the image data signal is changed with reference to the intermediate potential of.

Here, in the polarity inversion, a so-called line-by-line inversion in which the polarity is inverted each time a scanning signal line is selected, or a so-called dot in which the polarity is inverted for each pixel connected to one scanning signal line A polarity inversion driving method in which each inversion is combined is known.

FIGS. 11 and 12 are schematic diagrams for explaining the polarity inversion driving method. In a conventional active matrix type liquid crystal device, dot-sequential driving and pixel-by-pixel In addition, a method of precharging data signal lines in a batch during the immediately preceding blanking period is adopted.

In FIGS. 11 and 12, S 1 to S 4 indicate data signal lines, and H 1 to H 4 indicate scan signal lines. "10" and "-" of each pixel indicate the voltage applied to the liquid crystal of the pixel and the polarity of the precharge potential supplied to the data signal line immediately before. FIG. 11 shows the voltage polarity of each pixel in the N field, and FIG. 12 shows the voltage polarity of each pixel in the N + 1 field. In the polarity inversion driving for each pixel and each line, different polarities are set for each adjacent pixel connected to the same data signal line (for each vertically adjacent pixel in Figs. 11 and 12). Voltage is applied. In this case, even if, for example, the same black data is written on two adjacent pixels connected to the same data signal line and connected to different scanning signal lines, each black pixel is used for polarity inversion driving. The signal levels of the data are different. At this time, since the signal line itself has a parasitic capacitance, it takes time to change the potential of the data signal line from the black level potential on the positive side to the black level potential on the negative side.

With reference to FIGS. 13 and 14, a description will be given of a change in the potential of the data signal line in an operation of writing the same black to two adjacent pixels connected to the same data signal line.

In FIG. 13, C 10 indicates a parasitic capacitance of the data signal line S 1 (that is, an equivalent capacitance of the data signal line S 1). “−” And “ten” on the left side of FIG. 13 indicate the polarity of the voltage written to the pixels 22 and 24. Note that pixels 22 and 24 both display “black”. Each pixel includes a storage capacitor and a pixel electrode to which a data signal is supplied via a switching element, and a liquid crystal layer to which a voltage is applied between the pixel electrode and the common electrode.

As shown in FIG. 14, in the horizontal scanning period T1, a black level potential B1 is applied to one end of the pixel 22 to display black, and in the next horizontal scanning period T2, black is applied to one end of the pixel 24. Similarly, black display is performed by applying the level potential B2. In this case, since the common potential set between the black level potentials Bl and B2 is applied to the other ends of the pixels 22 and 24, a negative voltage is applied to the pixel 22. A positive voltage is applied to pixel 24 Thus, even in the same black display, the polarity of the voltage applied to the liquid crystal is inverted. Moreover, in the normally white display as described above, the potential difference between the black level potentials B1 and B2 is the largest as compared with the case of other gray scale displays. Therefore, unless pre-clearing is performed, the parasitic capacitance C10 of the data signal line S1 is charged (or discharged) by the image data signal itself, and the data is discharged as shown by "R1" in the figure. The potential of the evening signal line must be changed from black level potential B1 to B2.

On the other hand, if the precharge of the same polarity as that of the data signal is performed before the supply of the data signal, the precharge is performed before the horizontal scanning period T2, and the data signal line is supplied. If S1 is held at the high second precharge potential PV2, the potential of the data signal line is changed from the second precharge potential PV2 to the black level potential as indicated by "R2" in the figure. It only needs to be changed to B2, and the amount of charge (discharge) of the parasitic capacitance C10 of the data signal line S1 can be small. Therefore, the driving speed of the liquid crystal is increased.

By the way, in the conventional liquid crystal device, the black level potentials Bl and B2 are set to 1 V and 1 IV, the white level potentials Wl and W2 are set to 5 V and 7 V, respectively, and the precharge potentials PV 1 and PV 2 are set. Each was set to 4V, 8V. That is, the precharge potentials PV 1 and PV 2 are set symmetrically with respect to the center potential (6 V) between the black level potentials B 1 and B 2 which is the video amplitude.

These 4V and 8V are voltages applied to one end of the liquid crystal via the switching element at the halftone display level, and T1 which indicates the relationship between the liquid crystal applied voltage (V) and the transmittance (T) of the liquid crystal device. This corresponds to the potential level when the V force is the steepest. In other words, 4V and 8V correspond to the potential level when the change in transmittance with respect to the change in the voltage applied to the liquid crystal is the largest. By setting the precharge potentials PV1 and PV2 in this way, the data signal line can be charged and discharged in a short time from the precharge potential to the potential for halftone display, and accurate data can be obtained even if the sampling period is short. The halftone display can be performed.

In a liquid crystal device that performs liquid crystal display using light from a light source, for example, a projection type liquid crystal device such as a projector, optical crosstalk is a problem. What is optical crosstalk? A carrier is generated by light in a switching element formed on the substrate, for example, a TFT (thin film transistor), and a charge stored in a pixel connected to the TF リーク leaks and is connected to the TF Τ. This is a phenomenon in which the charge stored in the pixel fluctuates due to the influence of the potential of the source line (data signal line). Although this problem is known per se, the present inventors have clarified the relationship between the optical crosstalk and the precharge potential. This will be described with reference to FIGS.

Fig. 15 shows a screen in which the central area Α is displayed in black and the surrounding area B is displayed in halftone. The data signal line Sn is connected to only pixels that display halftone, and the data signal line Sn + i is connected to pixels that display halftone and black. Also, of the pixels in the halftone display area B, the pixel connected to the data signal line S n is A (m, n), and the pixel connected to the data signal line S n + i is A (m , n + i). FIG. 16 is a schematic diagram for explaining charge leakage when both the pixel A (m, n) and the pixel A (m, n + i) are driven at a positive voltage. In FIG. 16, when a voltage of 8 V is supplied to one end of pixel A (m, n) and pixel A (m, n + i) via the data signal line Sn, Sn + i, each pixel is The liquid crystal layer is actually charged with a voltage lower than 8 V by AV1. The reason is that if the switching element is a Ν-channel transistor, a high voltage is applied to the gate of the transistor to turn it on, and when charging the pixel, the gate-drain of the transistor (pixel electrode side electrode) This is because, when the transistor is turned off, the charge charged in the parasitic capacitance flows into the storage capacitor and the pixel electrode side, causing a voltage drop AV1.

Another reason is that if the sampling switch connected to each data signal line Sn, Sn + i is an N-channel transistor, the gate-drain (data line side) of the transistor will be operated in the same manner as above. This is because a voltage drop AV2 occurs due to the parasitic capacitance between the electrodes.

Assuming that both the switching element and the sampling switch are N-channel type transistors, the voltage charged in the liquid crystal layer is lower than the data voltage before sampling due to the above two types of voltage drops. Voltage drop is 2 1 + Approximated by V2. However, in the following description, only the voltage drop in the switching element will be considered.

Here, the pixel A (m, n) to which a charging voltage lower than 8 V is applied via the switching element has a precharge potential lower than or higher than the charging voltage and a data signal potential of 4 V. Or, leakage occurs in the switching element under the influence of the potential of the data signal line Sn to which 8 V is applied. In pixel A (m, n + i) to which a charge voltage lower than 8 V is applied via the switching element, the black level data signal voltage 1 V or 11 V which is lower or higher than the charge voltage is applied. Is applied to the data signal line S n + i, and leakage occurs in the switching element. That is, both pixels A (m, n) and A (m, n + i) have higher and lower precharge potentials than the charge voltage when the positive halftone display voltage is charged. Or a data signal line to which a higher and lower data signal potential is applied, and the charge charged in the pixel is alternately charged and discharged through the switching element, resulting in a result. It is hardly affected by the potential of the data signal line.

FIG. 17 is a schematic diagram for explaining charge leakage when the pixel A (m, n) and the pixel A (m, n + i) are charged with a negative voltage. In FIG. 17, when it is attempted to supply a voltage of 4 V to the pixel A (m, n) and the pixel A (m, n + i) via the data signal lines Sn, Sn + i, the liquid crystal layer of each pixel is In practice, a voltage lower than 4 V by Δν 1 is applied. The reason is the same as above.

Here, the pixel A (m, n) charged to a charge voltage lower than 4 V is a data signal line to which a precharge potential higher than the charge voltage and a data signal potential of 4 V or 8 V are applied. Leakage occurs in the switching element under the influence of the potential of Sn. Therefore, in the case of the pixel A (m, n) in the case of the negative voltage driving, a leak always occurs between the pixel A (m, n) and the data signal line having a potential higher than the charge voltage, and charges are charged from the data signal line. Therefore, the charge voltage always fluctuates in the positive direction. On the other hand, the pixel A (m, n + i) charged to a charge voltage lower than 4 V receives the lower or higher black level data signal potential of 1 V or 11 V. Under the influence of the potential of the data line Sn + i, leakage occurs in the switching element. Therefore, in the pixel A (m, n + i), when the negative voltage is charged, the charged voltage fluctuates in both positive and negative directions. Less susceptible to line potential.

From the above, the present inventors have clarified that the deterioration of the image quality due to the optical crosstalk is particularly remarkable when the negative voltage described in FIG. 17 is applied. The reason is that the voltage charged to the pixel A (m, n) always changes unidirectionally to the positive polarity direction, that is, to the white side on the display when the negative polarity image voltage is applied. This is because a display gradation difference occurs between the pixel A (m, n) to be formed and the pixel A (m, n + i), and the gradation difference between the two becomes large.

When the switching element is formed of a P-channel transistor, the shift 1 caused by the parasitic capacitance of the transistor increases the charge voltage charged to the pixel by one AV. In other words, the potential relationship based on the voltage Vc in FIGS. 16 and 17 is reversed, and the potential relationship is such that the upper side of the voltage Vc is negative and the lower side is the positive polarity. At the time of voltage driving, FIG. 17 shows the case of positive voltage driving. In such a case, the pixel A (m, n) in FIG. 17 has a positive charge voltage (corresponding to the lower side in FIG. 17). Electric charge starts flowing in the evening signal line, and the charge voltage of pixel A (m, n) unilaterally fluctuates in the negative direction (corresponding to the upper side of the figure), causing optical crosstalk during positive voltage drive. It was found that the deterioration of the image quality was noticeable.

To explain another problem, in recent years, a high-definition liquid crystal display is required, and as the number of pixels on one scanning line increases, the frequency of sampling signals of data signals increases. At this time, switching noise is generated by the sampling switch driven by the high frequency sampling signal, and is superimposed on the data signal line. If the sampling period is short, the sampling ends before the influence of the switching noise is eliminated, so that the original data cannot be applied to the liquid crystal layer. An object of the present invention is to provide a liquid crystal device and a liquid crystal display method capable of reducing image quality deterioration caused by optical crosstalk, and a projection display device and an electronic device using the same. To provide.

Another object of the present invention is to improve the image quality by supplying a voltage faithful to the original data signal to the liquid crystal layer by suppressing a write failure of the data signal due to a higher frequency of the data sampling signal. It is an object of the present invention to provide a liquid crystal device, a liquid crystal display method, and a projection display device and an electronic device using the same. ―

[Disclosure of the Invention]

According to one aspect of the present invention,

A switching element electrically connected to a liquid crystal layer is arranged in each of a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines, and is applied to the liquid crystal layer. In a liquid crystal device driven by inverting the polarity of the voltage every predetermined period,

Scanning-side driving means for supplying a scanning signal for selecting at least one of the plurality of scanning signal lines to the plurality of scanning signal lines;

A data driver for supplying the data signal to each of the plurality of data signal lines;

Prior to supplying the data signal to each of the plurality of data signal lines, a positive polarity or a negative polarity having the same polarity as the polarity of the voltage applied to the liquid crystal layer of the pixel based on the data signal. A plurality of precharge switching means for precharging each of the plurality of data signal lines at a precharge potential;

When applying a negative voltage to the liquid crystal layer, the data signal changes within a range of a negative data voltage amplitude between a first potential and a second potential that is higher than the first potential. When a positive voltage is applied to the positive electrode, the voltage changes within a range of a positive data voltage amplitude between a third potential higher than the second potential and a fourth potential higher than the third potential,

The positive and negative precharge potentials are set asymmetrically with respect to a central potential of a voltage amplitude between the first and fourth potentials, and the negative precharge potential is set to The characteristic data voltage is set so as to be closer to the first potential than the center potential of the characteristic data voltage amplitude. According to the present invention, the negative signal line is precharged by the negative precharge potential set closer to the first potential than the potential for halftone display. That is, in the present invention, a precharge potential close to the first potential is periodically applied to the data signal line irrespective of the gradation level of the pixel connected to the data signal line. Therefore, even if optical crosstalk occurs in the switching element of a pixel when the pixel is charged with the negative charge voltage of the halftone display, the data signal line to which the pixel is connected is: The negative precharge potential lower than the charged charge voltage is applied periodically, and the positive precharge potential and data signal potential higher than the charge voltage are applied periodically. As described above, the potential does not unilaterally change to the positive polarity side, and the deterioration of the image quality due to the leakage of the switching element is reduced.

More specifically, the present invention can be applied to a case where each of a plurality of switching elements is formed by an N-channel transistor. For example, if the precharge potential PVI in FIG. 17 is changed to a value close to the first potential (B 1) as shown in FIG. 2, the switching elements of the pixel A (m, η) and the pixel A (m, n + i) If the pixel leaks due to light, the data signal lines S n and S n + i to which the pixel is connected are both negative polarity pre-charges having a potential close to the first potential (black level potential B 1 in FIG. 2). A charge potential and a positive precharge potential are applied periodically. Therefore, even when the voltage of the halftone display of negative polarity is applied to the pixel, both pixels A (m, n) and A (m, n + i) are different from FIG. Leakage occurs between the data line and the data line to which positive and negative voltages are alternately applied. For this reason, it is possible to reduce deterioration in image quality due to optical crosstalk.

Setting the negative polarity precharge potential as described above has an effect even when each of the plurality of sampling switching means is formed by an N-channel transistor. In this case, when the sampling switching means is turned on, switching noise is generated and is superimposed on the data signal line. Here, this switching noise has an adverse effect such as prolonging the time for discharging the potential of the data signal line in the negative direction, and in particular, the potential of the data signal line has the lowest data rate during the sampling period. Prevents discharge until the first potential, which is the evening signal potential. Therefore, the negative signal potential is brought closer to the first potential, and the potential difference from the negative precharge potential to the first potential is reduced, so that the data signal line becomes the first potential during the sampling period. Is compensated.

Here, it is preferable that the negative precharge potential is higher than the first potential. This is because when the negative precharge potential is lower than the first potential, the voltage difference between the gate and the source of the N-channel transistor disappears and leakage occurs.

Also, the positive precharge potential is preferably lower than the third potential. The above-described switching noise acts to shorten the time for charging the potential of the data signal line in the positive direction. For this reason, even if the potential of the data signal line is set to any of the third and fourth potentials after the precharge at the positive precharge potential lower than the third potential, It is only necessary to charge the signal line overnight, and this charging can be accelerated using switching noise.

According to another aspect of the present invention, the positive precharge potential can be set closer to the fourth potential than the center potential of the positive data voltage amplitude.

In this case, the data signal line is precharged by the positive precharge potential set closer to the fourth potential than the potential for halftone display. Therefore, even if optical crosstalk occurs in the pixel switching element, the pixel is affected by the potential of the data signal line that is alternately set to the positive precharge potential and the negative precharge potential close to the fourth potential. As described above, the potential does not fluctuate unilaterally to the negative polarity side as described above, and the deterioration of image quality due to leakage of the switching element is reduced.

More specifically, the present invention can be applied when each of a plurality of switching elements is formed by a P-channel transistor. For example, if the positive polarity potential PV 1 is changed to a value close to the fourth potential as shown in FIG. 7 described later, the pixel A (m, n) and the pixel A (m, n + i) are charged. Even if the voltage is affected by the potential of the data signal line due to the light leakage of the switching element, the data signal lines S n and S n + i have the fourth potential (black level potential B 2 in FIG. 7). Near positive polarity —Di potential and negative precharge potential are applied periodically. Therefore, even when a pixel is charged with a positive voltage, both pixels A (m, n) and A (m, n + i) alternately change to a positive and negative voltage with respect to that voltage. Leakage occurs between the set data line and the data line, so it is less affected by the data line. Therefore, it is possible to reduce the deterioration of the image quality due to the optical crosstalk.

When the positive precharge potential is set as described above, it is effective even when each of the plurality of sampling switching means is formed by a P-channel transistor. In this case, when the sampling switching means is turned on, switching noise is generated, which is superimposed on the data signal line. Here, the switching noise has an adverse effect such as prolonging the time for charging the potential of the data signal line in the positive direction. In particular, the potential of the data signal line becomes higher at the highest data signal potential during the sampling period. Prevents charging to a certain fourth potential. Therefore, by bringing the positive polarity precharge potential closer to the fourth potential and reducing the potential difference from the positive precharge potential to the fourth potential, the data signal line becomes the fourth potential within the sampling period. To compensate. '

Here, the positive precharge potential is preferably lower than the fourth potential. If the positive precharge potential is higher than the fourth potential, the voltage difference between the gate and the source of the P-channel transistor disappears, and leakage occurs.

Further, the negative precharge potential is preferably higher than the second rank. The above-described switching noise acts to shorten the time for discharging the potential of the data signal line in the negative direction. For this reason, even if the potential of the data signal line is set to any data signal potential between the second potential and the first potential after precharging with the negative precharge potential higher than the second potential, the data signal line is always This is because it is only necessary to discharge, and this discharge can be hastened by using switching noise.

The switching element used in the present invention is not limited to the thin film transistor described in the embodiment, but may be constituted by a MOS transistor when the element forming substrate of the liquid crystal panel substrate is formed by a single crystal silicon substrate. be able to. It can also be formed by a two-terminal nonlinear element such as MIM. The present invention is preferably applied to a projection display device using the liquid crystal device of the present invention as a light valve that modulates light from a light source, particularly from the viewpoint of reducing image quality deterioration due to optical crosstalk. In addition, the present invention is also effective for various electronic devices provided with a transmission type or reflection type liquid crystal device using light from a light source.

[Brief description of drawings]

FIG. 1 is a schematic explanatory view of an active matrix type liquid crystal device of the present invention.

FIG. 2 is a schematic explanatory diagram showing a potential of a pixel and a potential of a data signal line at a leakage destination when a liquid crystal is driven with a negative voltage according to the first embodiment of the present invention.

FIG. 3 is a schematic explanatory diagram showing a potential of a pixel and a potential of a data line at a leakage destination when a liquid crystal is driven with a positive polarity voltage in the first embodiment of the present invention.

FIG. 4 is a schematic explanatory diagram schematically showing a pixel A (m-1, n) and a pixel A (m, n).

FIG. 5 is a timing chart showing the potential change of the pixel A (m-1, n) shown in FIG. 4 and the data signal line Sn connected to the pixel A (m, n).

FIG. 6 is a timing chart of Comparative Example 1 in which the precharge potential in FIG. 5 is changed.

FIG. 5 is a schematic diagram showing the potential of the pixel and the potential of the data line at the leakage destination when the liquid crystal is driven at the negative and positive voltages, respectively, in the second embodiment of the present invention. FIG.

FIG. 8 is a schematic explanatory diagram for explaining a leak when the precharge potential in FIG. 7 is changed.

FIG. 9 is a timing chart illustrating the operation of the second embodiment of the present invention. FIG. 10 is a timing chart of Comparative Example 2 in which the precharge potential in FIG. 9 is changed.

FIG. 11 is a schematic explanatory diagram showing the polarity of the voltage applied to the liquid crystal of each pixel in N fields.

Figure 12 shows the polarity of the voltage applied to the liquid crystal of each pixel in the N + 1 field FIG.

FIG. 13 is a schematic explanatory diagram showing two pixels connected to the same data signal line.

FIG. 14 is a characteristic diagram showing a potential change of the data signal line when the same black data is written to the two pixels shown in FIG. ―

FIG. 15 is a schematic view of a liquid crystal screen for explaining optical crosstalk.

FIG. 16 is a schematic explanatory diagram of a conventional example showing the potential of a pixel when the liquid crystal is driven with a negative voltage and the potential of a leakage signal line at the leakage destination.

FIG. 17 is a schematic explanatory view of a conventional example showing a potential of a pixel when a liquid crystal is driven by a positive voltage and a potential of a data line at a leakage destination thereof.

FIG. 18 is a schematic diagram of an electronic device configured using the image display device according to the present invention.

FIG. 19 is a schematic diagram of a liquid crystal projector to which the present invention is applied.

FIG. 20 is a schematic diagram of a personal computer (PC) to which the present invention is applied.

[Best Mode for Carrying Out the Invention]

Embodiment 1>

(Schematic configuration of device)

FIG. 1 shows an overall outline of the liquid crystal device according to the first embodiment. As shown in FIG. 1, this liquid crystal device is a small liquid crystal device used as a light valve of an electronic device such as a liquid crystal projector, and includes a liquid crystal panel block 10, a timing circuit block 20, and a data processing block. It is roughly divided into 30.

The timing circuit block 20 receives the clock signal CLK and the synchronizing signal SYNC and outputs a predetermined evening timing signal such as a shift start signal, a shift clock signal, and a precharge signal.

The data processing circuit block 30 is a circuit block for processing data by amplifying and inverting data so as to be suitable for a liquid crystal display. This data processing block At 30, the data signal corresponding to each pixel is inverted with respect to the polarity-inversion reference potential for each pixel. This polarity inversion is inverted every vertical scanning period (every field or every frame).

The liquid crystal panel block 10 has liquid crystal sealed between a pair of substrates, and includes a pixel region 100, a scanning drive circuit 102, and a data drive circuit 104 on one substrate. A common electrode is provided on the other substrate facing this. A polarizing plate is arranged outside the pair of liquid crystal panel substrates. Note that these driving circuits may be configured as external ICs separately from the liquid crystal panel substrate.

On the pixel area 100, for example, a plurality of scanning signal lines 110 extending in the row direction of FIG. 1 and a plurality of data signal lines 112 extending in the column direction, for example, are provided. It is formed. In this embodiment, the total number of the scanning signal lines 110 is set to 492 and the total number of the data signal lines 112 is set to 652. The number is not particularly limited.

At each position where the scanning signal line 110 and the data signal line 112 intersect, a switching element 114 and a pixel 120 are connected in series to constitute a display element. . Each pixel 120 is formed together on one substrate, and is formed between a pixel electrode connected to the switching element 114 and a scanning signal line or a capacitor line adjacent to each pixel electrode. It is composed of a storage capacitor 117, a common electrode formed on the other opposing substrate, and a liquid crystal layer 116 sandwiched between the two electrodes.

A period during which the switching element 114 of each pixel 120 is turned on is referred to as a selection period, and a period during which the switching element 114 is turned off is referred to as a non-selection period. A storage capacitor 117 that stores the voltage supplied to the pixel 120 via the switching element 114 during the selection period during the non-selection period is connected to the pixel 120.

In the present embodiment, the switching element 114 is, for example, a three-terminal switching element, for example, a TFT (thin film transistor). However, the present invention is not limited to this. For example, a MOS transistor that is another three-terminal switching element, or a two-terminal switching element such as a MIM (metal-insulation-metal) element or an MIS (metal-insulation-semiconductor) element can be used. . Note that the image of this embodiment is The element region 100 is not limited to an active matrix type liquid crystal display panel using two-terminal or three-terminal switching, but may be various other liquid crystal panels such as a simple matrix type liquid crystal display panel. .

The scanning side driving circuit 102 outputs a scanning signal in which a selection period for sequentially selecting at least one of the plurality of scanning signal lines 110 is set. is there.

The data side driving circuit 104 is an output line of the data processing circuit block 30, for example, one signal line and a data signal line 1 1 2 a, 1 1 2 b, A sampling signal for driving the pixel area 100 in a point-sequential manner is output to the sampling switches 106 arranged between. When the data processing circuit block 30 has a known phase expansion circuit, the output lines of the data output circuit block 30 have the same number of output lines as the number of phase expansions. Here, the phase expansion circuit samples and holds the image data signal as serial data according to a sampling period set based on a reference clock, and expands the serial data for each fixed pixel. Thus, a plurality of data signals whose one data output period from the data processing circuit block 30 has been converted to an integral multiple of the reference clock are output in parallel.

The precharge switches 1 7 2 a, 1 7 2 b,... Are turned on at a predetermined timing by a precharge signal, and the first (negative) precharge power supply line 1 7 4 a Alternatively, connect the second (positive polarity) precharge power supply line 1 7 4 b to each data line 1 1 2 a, 1 1 2 b This is for practicing. The polarity of the precharge power supply voltage is based on the common electrode potential applied to the common electrode.

The first and second precharge oven power supply lines 174a and 174b are connected to a first precharge potential PV1 and a second precharge voltage via a precharge power supply switch 190, respectively. The precharge potential PV 2 is switched and supplied every time the scanning signal line 110 is selected (for each horizontal scan). The switching timing of the power supply switch 190 is set at least before the precharge switch 1Ί2 is turned on. It is.

In the present embodiment, since the polarity inversion driving is performed, for example, in the odd-numbered horizontal scanning period, the odd-numbered data signal lines 17 2 a, 17 2 c,. The supply line 174a is connected, and the even-numbered data signal lines 172b, 172d,... Are connected to the second precharge power supply line 174b. In the even-numbered horizontal scanning period, the odd-numbered data signal lines 17 2 a, 17 2 c,... Are connected to the second precharge power supply line 17 4 b, and the even-numbered data signal lines 17 2 a, 17 2 c,. Are connected to the first precharge power supply line 174b. The details of this precharge operation will be described later.

That is, in the present embodiment, the polarity inversion driving is performed for each pixel in the direction in which the scanning signal line extends, and the polarity inversion driving is performed for each line (for each scanning signal line) in the direction in which the data signal line extends. Therefore, the polarity inversion timing is determined to match this. That is, the polarity of the precharge potential and the data signal applied to each data signal line and each pixel are inverted not only for each scanning signal line or pixel, but also for each vertical scanning period. Note that the case where precharging is required is a case where polarity inversion driving is performed at least for each line, and is not limited to polarity inversion for each pixel.

Then, a shift start signal formed based on the clock CLK and the synchronization signal SYNC is input to the shift register of the data drive circuit 1G4, and the data drive circuit 104 generates a sampling signal. The sampling of the data signal is performed by sequentially turning on the sampling switches 106a to 106g based on the sampling signal.

(About precharge operation that reduces the adverse effects of optical crosstalk)

In the first embodiment, the voltage applied to the pixel based on the data signal sampled in the sampling period during the blanking period (retrace period) before each sampling period described above for each data signal line is described. The polarity is the same as that of, and each data line is precharged at the same time. The pixels are marked based on the data signal. The polarity of the applied voltage is the polarity with respect to the common electrode potential.

The relationship between the precharge potential and the data signal potential will be described with reference to FIG. FIG. 2 shows a data signal potential and a precharge potential when an N-channel TFT is used as the switching element 114 and a normally white display is performed. In FIG. 2, when the liquid crystal is driven by a voltage having a negative polarity, the potential of the first signal B1 (IV) and the second potential W1 (5 V) are changed according to the gradation value. Varies between. In the normally white display, the first potential B1 corresponds to black display, and the second potential W1 corresponds to white display. In the display of normally black, the relationship is opposite to the above.

In FIG. 2, when driving the liquid crystal with a positive voltage, the overnight signal potential is changed to a third potential W2 (7 V) and a fourth potential B 2 (11 V) according to the gradation value. It changes between. In the normally white display, the second potential W2 corresponds to white display, and the fourth potential B2 corresponds to black display. In the display of normally black, the relationship is opposite to the above.

Therefore, the amplitude center Vc of the data signal potential is 6 V. The center potential VC1 of the amplitude (B1 to W1) in the case of the negative voltage drive is 3 V, and the center potential VC2 of the amplitude (W2 to B2) in the case of the positive voltage drive is 9 V.

The above relationship is the same as in FIGS. 16 and 17, but in the present embodiment, the first precharge potential PV1 and the second precharge potential PV2 are different from those in the conventional case. I have.

In the present embodiment, the first precharge potential PV1 is set to 1.5V, and the second precharge potential PV2 is set to 6.5V. As described above, the first and second precharge potentials: P V1 and PV2 are set asymmetrically with respect to the amplitude center V c of the overnight signal potential.

Further, in the present embodiment, the first precharge potential PV 1 (1.5 V) is closer to the first potential (IV) than the amplitude center VC 1 (3 V) of the data signal potential in the negative voltage drive. Is set. The second precharge potential PV2 (6.5 V) is set to a value smaller than the third potential W2 (7 V) of the positive voltage drive. Here, a case where the liquid crystal of the pixel A (m, n) and the pixel A (m, n + i) shown in FIG. 15 are driven by a negative voltage, and one end of the pixel is provided with a voltage for halftone display. The case where (4 V) is applied will be described. In this case, as shown in Figure 2,

Δ The voltage dropped by VI is charged to the pixel. The reason is explained with reference to FIG. ―

In Fig. 4, the capacitance between the gate and drain of the switching element (TFT) 114 is CGD1, the capacitance of the liquid crystal layer 116 is CLC, the storage capacitance 117 is CSTG, and the capacitance is applied to the gate of the TFT 114. Assuming that the potential difference between the selection period and the non-selection period of the scanning signal is Vg, the voltage drop 1 occurs due to the parasitic capacitance of the TFT 114 immediately after the charge voltage is applied to the pixel in the selection period. AV1 is approximated by the following equation.

△ V l = [CGD1 / (CGD + CCL + CSTG)] xVg

That is, when the charge accumulated in the CGD during the selection period becomes a non-selection potential during the non-selection period, the charge flows into the CLC and the CSTG to lower the storage voltage of the CLC and the CSTG.

In addition, there is a voltage drop 2 due to the gate-drain parasitic capacitance of the sampling switch (TFT) 106. When the gate-drain parasitic capacitance of TFT106 is CGD2, the parasitic capacitance of the data signal line is CD2, and the potential difference between the sampling period and the non-sampling period of the sampling signal applied to the gate of TFT 106 is Vg2. The voltage drop 2 is approximated by the following equation.

△ V2 = [C GD2 / (CGD2 + CD2)] xVg2

Therefore, a voltage drop approximated by the addition of 1 and 2 occurs between the data signal potential before sampling and the potential actually applied to the liquid crystal layer of the pixel.

By the way, in the pixel A (m, n) shown in FIG. 15, since all pixels connected to the data signal line Sn perform halftone display, the precharge before negative voltage driving is performed. During this period, the data line Sn is precharged to the first precharge potential PV1 (1.5 V). FIG. 2 differs from the conventional FIG. 17 in this point. Conventional Figure 1 In the method shown in Fig. 7, the charge voltage of pixel A (m, n) fluctuates only in the positive direction due to leakage at the TFT, but in the case of Fig. 2, it is higher than the charge voltage on the data signal line. Since the potential is applied alternately to the lower potential, the charge voltage fluctuates so as to alternately shift in both positive and negative directions. Pixel A (m, n) and pixel A (m, n + i) are the same in that the charge voltage fluctuates so as to alternately shift between positive and negative. Therefore, if pixel A (m, n + i) shifts toward black on the display, pixel A (m, n) also shifts toward black on the display, and the effect of optical crosstalk is displayed. Offset above. Similarly, if pixel A (m, n + i) is shifted in the direction in which it becomes white on the display, pixel A (m, n) is similarly shifted in the direction in which it becomes white on the display, and optical crosstalk is reduced. The effects are offset on the display. In this manner, in the present embodiment, optical crosstalk can be made inconspicuous on display, and the image quality can be improved. When the liquid crystal layer is driven by a positive voltage, the result is as shown in FIG. 3, and no problem occurs as in the conventional case. The operation of the second precharge potential PV2 will be described later.

(Overall precharge operation)

Next, a description will be given of the overall precharge operation in which the adverse effect of the switching noise in the sampling switch is also reduced.

FIG. 5 shows a timing chart of the liquid crystal device of the present invention when all the sampling switches 106 and the switching elements 114 in FIG. 1 are formed by N-channel transistors. Here, FIG. 5 shows that the pixel 120 of the pixel A (m, η) shown in FIG. 4 and the pixel 120 of the pixel A (m, n) shown in FIG. 4 both display black. Of the data signal line of FIG. Also, in FIG. 5, during a period in which the precharge signal PC is high in the m-1st horizontal scanning period, the data signal line Sn is precharged with the positive potential, and the precharge in the mth horizontal scanning period is performed. In the description, it is assumed that the data signal line Sn is precharged with the negative potential during the period when the signal PC is high.

In the present embodiment, as described above, the first precharge potential PV1 is set to, for example, 1.5 V, and the second precharge potential PV2 is set to, for example, 6.5 V. I have.

m — The horizontal scanning signal (m-1) goes high when the first horizontal synchronization signal SYNC is input. Therefore, all the switching elements 114 connected to the scanning signal line Hm-1 are turned on. Thereafter, the precharge signal PC becomes high, and all the precharge switches 172 are turned on. As a result, the first precharge potential PV from the first precharge power supply 174a is applied to the odd-numbered data signal lines S1, S3, -Sn-1, Sn + 1, Sn + 3,. 1 (1.5 V) is supplied. On the other hand, the even-numbered data signal lines S2, S4, -Sn, Sn + 2, Sn + 6,... Are connected to the second precharge potential PV2 (6.5 V ) Is supplied.

Here, the potential of the data signal line Sn shown in FIG. 5 becomes black level potential B 1 (1 V) if the pixel A (m-2, n) performs black display before this precharge operation. It is near. Thereafter, since the above-described precharge operation is started, the overnight signal line Sn is precharged to the second precharge potential PV2 (6.5 V). Since the data signal line Sn has a parasitic capacitance CD2, the data signal line Sn maintains the second precharge potential PV2 even after the precharge period ends. Thereafter, sampling of the data signal is started for all the pixels connected to the scanning signal line Hm-1 in FIG. For example, if the total number of data signal lines 112 is 652, for example, the data signals are sampled sequentially from the leftmost data signal line for each data signal line according to the sampling signal. It is done by the method. Then, in order to display black on pixel A (m−1, η), the black level potential 正極 2 (1) on the positive polarity side is applied to the data signal line Sn via the sampling switch 106 during the sampling period. IV) is supplied. Then, the storage capacitor 1 17 and the liquid crystal layer 1 16 in the pixel A (m−1, n) are charged with electric charge, and black display is performed.

At this time, as shown in the timing chart of FIG. 5, when the sampling switch 106 is turned on at the rise of the sampling signal, a switching noise is generated, which is superimposed on the data signal line Sn. This sampling switch Switching noise generated when the switch 106 is on acts in a direction to temporarily increase the potential of the data signal line Sn.

As described above, when an N-channel transistor is used for the sampling switch 106, when the data line S n is charged from the second precharge potential PV 2 to the data signal potential, the switching noise causes the charging noise to increase. Acts in the direction of hastening. For this reason, even if the second precharge potential PV2 is set to 6.5 V, which is lower than the conventional 8 V, the situation that the original data signal potential is not charged before the sampling period ends is reduced.

When this sampling signal falls, the sampling switch 106 is turned off. At this time, the voltage drop 2 described above is caused by the parasitic capacitance of the sampling switch 106, and the potential of the data signal line Sn is reduced as shown in FIG. Descend. For this reason, the voltage charged in the pixel A (m-1, n) is a low voltage based on the above-described voltage drop Δν 1 with respect to the original data signal potential. Further, the above-described voltage drop AV2 also occurs in the pixel. However, if the common electrode potential applied to the common electrode formed on the opposite substrate is lowered in consideration of these voltage drops, a voltage required for black display of the pixel can be applied to the liquid crystal layer of the pixel.

If the sampling switch 106 has a CMOS transistor structure, such a voltage drop can be prevented.

Thereafter, the horizontal scanning signal (m−l) goes low and the horizontal scanning signal (m) goes high. Thereby, the scanning signal line Hm shown in FIG. 4 is selected, and all the switching elements 114 connected to the horizontal scanning line Hm are turned on.

Thereafter, the precharge operation and the overnight write operation are performed in the same manner as the scanning signal line Hm-1. However, both the precharge operation and the data write operation in the m-th horizontal scanning period are performed with a negative voltage. Therefore, the switch 190 in FIG. 1 is switched before the precharge operation. As a result, the odd-numbered signal lines S1, S3, -Sn-1, Sn + 1, Sn + 3,. Potential PV 2 (6.5 V) is supplied. On the other hand, even-numbered data signal lines S2, S4, -Sn, Sn + 2, Sn The first precharge potential PVI (1.5 V) from the second precharge power supply 174a is supplied to +4.

Consider the potential of the data signal line Sn in the m-th horizontal scanning period. The potential of the data signal line Sn is first changed to a first precharge potential PV 1 (1.5 V) from a potential for performing black display at the pixel A (m−1, η). Is done. Thereafter, as shown in the timing chart of FIG. 5, when the sampling switch 106 is turned on at the rise of the sampling signal, switching noise occurs, and is superimposed on the data signal line Sη. You. The switching noise generated when the sampling switch 106 is turned on acts in the direction of temporarily increasing the potential of the data signal line Sη, and the precharge causes the potential of the data signal line Sη to become black level. It acts in the direction opposite to the direction of discharging to the potential B l (IV).

Therefore, in the m-th horizontal scanning period, the switching noise acts to delay the operation of discharging the data signal line Sn so as to have the black level potential B1. However, in the present embodiment, the first precharge potential PV 1 is set to 1.5 V, and the difference from the black level potential Bl (1.5 V) is 0.5 V. During this time, the data signal line Sn can reach the black level potential B1.

As described above, when the sampling switch 106 is an N-channel type transistor, the switching noise has an adverse effect when the data signal line Sn is discharged. The most severe condition for discharging the data signal line Sn is when the data signal line Sn is set to the black level potential Bl (IV). Therefore, in the present embodiment, the first precharge potential PV1 is set to 1.5 V, which is close to the black level potential B1 (IV). If the first precharge potential PV1 is lower than the black level potential B1, the gate potential and the source potential of the sampling switch 106 become equal, which may cause a leak. For this reason, the first precharge potential PV 1 is preferably set to be always higher than the black level potential B 1 and to be as close as possible to the black level potential B 1 in consideration of variations in circuit constants and the like. .

In the present embodiment, the second precharge potential PV2 is a positive voltage drive. Is set to 6.5 V, which is lower than the white level potential W2 (7 V) at the time. One of the reasons is that, during the m-th horizontal scanning period in FIG. 5, the data signal line Sn is always charged from the 6.5 V second precharge voltage PV2, so that the white level potential W2 This is because any data signal potential between (7 V) and the black level potential B 2 (1 IV) can be set. At this time, the switching noise at the start of the sampling period acts to accelerate the charging. Therefore, even if the second precharge voltage PV2 is not set to 8 V as in the conventional case, the data signal line Sn can be charged to the original data signal potential within the sampling period in the present embodiment. Can be.

Note that the setting of the second precharge potential PV2 is based on the difference between the first and second precharge potentials PV1 and PV2 in the present embodiment being the same as the conventional first and second precharge potentials PV1 and PV2. Various values can be set as long as 4 V or more, which is the potential difference between PV2 and PV, can be secured. By doing so, the potential difference from the second precharge potential to the data signal potential in the range of the positive polarity data amplitude (W2 to B2) can be limited to the potential difference that can be charged and discharged during the sampling period. Because. In particular, when the image data is phase-expanded as described above, even if there is some variation in the sampling period for sampling each image data, each data line is connected to the data signal potential. Charge and discharge until As a result, it is possible to reduce the occurrence of vertical stripes on the screen due to variations in the sampling period. Note that, also during the m-th horizontal scanning period, the above-described voltage drop AV1 occurs when the sampling switch 172 is turned off, and as shown in FIG. 5, the potential of the data signal line Sn is set to a voltage lower than the black level potential B1. Is as described above.

(Description of Comparative Example 1)

FIG. 6 shows a timing chart of Comparative Example 1 when the first and second precharge potentials PV 1 and PV 2 shown in FIG. 5 are set to 4 V and 8 V, respectively, in the related art. In the m-th horizontal scanning period in FIG. 6, before the potential of the signal line Sn is discharged from the first precharge potential PV 1 (4 V) to the black level potential B 1 due to the adverse effect of switching noise. The sunring period has ended. Therefore, the potential of the data signal line Sn becomes the potential Va which is not the data signal potential corresponding to the original black, and the pixel A It can be seen that (m, n) is charged with a charge that does not reflect the original data, degrading the image quality.

Next, a second embodiment in which the switching element 114 or the sampling switch 106 shown in FIGS. 1 and 4 is formed by a P-channel transistor will be described.

First, a method for reducing the deterioration of image quality due to optical crosstalk when the switching element 114 is a P-channel transistor will be described.

In this case, as shown in FIG. 7, the first precharge potential PV 1 is set to 5.5 V, and the second precharge potential PV2 is set to 10.5 V. As described above, the first and second precharge potentials PV1 and PV2 are set asymmetrically with respect to the amplitude center Vc of the overnight signal potential.

Further, in the present embodiment, the second precharge potential PV2 is set closer to the second potential (1 IV) than the amplitude center VC2 (9 V) of the data signal potential in positive voltage driving. . The first precharge potential PV1 is set to a value larger than the second potential W1 (5 V) of the voltage drive of the negative polarity.

Here, pixel A (m, n) and pixel A (m, n + i) shown in Fig. 14 are driven by a positive voltage, and one end of the pixel has a voltage for halftone display. (8V) will be described. In this case, unlike the case where an N-channel transistor is used, when a switching element is formed by a P-channel transistor, a voltage higher than 8 V by AV3 is applied to the liquid crystal layer as shown in FIG. Will be The rising voltage AV3 is determined in the same manner as the above-described equation for determining the drop voltage AV1 in the N-channel type transistor, with the switching element 114a in FIG. 4 being a channel type transistor.

By the way, in the pixel A (m, n) shown in FIG. 15, since all pixels connected to the data signal line Sn perform halftone display, the precharge before positive voltage driving is performed. At this time, the data line Sn is precharged to the second precharge potential PV1 (10.5 V). FIG. 7 differs from the conventional FIG. 8 in this respect. In the conventional method of Fig. 8, the charge voltage of the pixel A (m, n) to which the positive polarity voltage is written is leaked to the signal line Sn by the light due to the TFT leaking by light. Under the influence of the first and second precharge potentials lower than the applied charge voltage, the voltage fluctuates unilaterally only in the negative voltage direction. However, in the case of FIG. 7, since the precharge voltage PV 2 is higher than the charge voltage, the pixel A (m, n) is affected by the potential higher and lower than the charge voltage applied to the data signal line. In response to this, it fluctuates in both positive and negative directions. For this reason, if pixel A (m, n + i) is shifted in the direction to become black on the display, pixel A (m, n) is similarly shifted in the direction to become black on the display, and optical crosstalk is reduced. The effects are offset on the display. Similarly, if pixel A (m, n + i) is shifted in the direction of whitening on the display, pixel A (m, n) is also shifted in the direction of whitening on the display, and optical crosstalk is reduced. The effects are offset on the display. In this manner, in this embodiment, the optical crosstalk can be made inconspicuous on display, and the image quality can be improved. When the liquid crystal layer is driven by a negative voltage, the result is as shown in FIG. 7, and no problem occurs as in the conventional case.

(Overall precharge operation)

FIG. 9 shows a timing chart of the liquid crystal device of the present invention in a case where all the sampling switches 106 and the switching elements 114 in FIG. 1 are all formed by P-channel transistors. Here, FIG. 9 shows, similarly to FIG. 5, the pixel 120 of the pixel A (m−1, n) shown in FIG. 4 and the pixel 120 of the pixel A (m, n) shown in FIG. , Are both displayed in black to explain the change in potential at the data signal line at that time.

In FIG. 9, unlike FIG. 5, the sampling switch 106 which is a P-channel transistor is turned on when the sampling signal is low, and the switching element 1 16 which is a P-channel transistor is turned on when the scanning signal is low. It is turned on. In the present embodiment, as described above, the first precharge potential PV1 is set to 5.5 V, for example, and the second precharge potential PV2 is set to 10.5 V, for example.

The horizontal scanning signal (m-1) becomes low by inputting the m-th horizontal synchronizing signal SYNC, so that all the switching elements 114 connected to the scanning signal line Hm are turned on. Thereafter, the precharge signal PC becomes high, and all the precharge switches 172 are turned on. As a result, the odd-numbered data signal lines S l, S 3, -S n -1, Sn + 1, S n + 3... Are supplied with the first precharge potential PV 1 ( 5.5 V) is supplied. On the other hand, the even-numbered data signal lines S2, S4, -Sn, Sn + 2, Sn + 4,... Are connected to the second precharge potential PV2 ( 10.5 V) is supplied.

Here, assuming that the pixel A (m−2, n) performs black display before the precharge operation, the potential of the data signal line Sn shown in FIG. 9 becomes black level potential B 1 (1 V). Thereafter, since the above-described precharge operation is started, the overnight signal line Sn is precharged to the second precharge potential PV2 (10.5 V).

Thereafter, sampling of the data signal is started for all the pixels connected to the scanning signal line Hm-1 in FIG. In order to display black on pixel A (m-1, n), the black level potential B 2 (1 IV) on the positive polarity side is applied to the data signal line Sn via the sampling switch 106 during the sampling period. Is supplied. Then, a voltage is charged to the pixel A (m-1, n), and a black display is performed.

At this time, as shown in the timing chart of FIG. 9, when the sampling switch 106 is turned on at the falling edge of the sampling signal, switching noise is generated and is superimposed on the data signal line Sn. The switching noise generated when the sampling switch 106 is turned on acts in a direction to temporarily reduce the potential of the data signal line Sn.

Thus, when the sampling switch 106 is a P-channel transistor, In this case, the switching noise has an adverse effect when the data signal line Sn is charged. The most severe condition for discharging the overnight signal line Sn is when the data signal line Sn is set to the black level potential B 2 (1 IV). Therefore, in the present embodiment, the second precharge potential PV2 is set to 10.5 V, which is close to the black level potential B2 (11 V). If the second precharge potential PV2 exceeds the black level potential B2, the gate potential and the source potential of the sampling switch 106 become equal, and there is a possibility that leakage occurs. For this reason, the second precharge potential PV2 may be set to be always lower than the black level potential B2 and to be as close as possible to the black level potential B2 in consideration of variations in circuit constants and the like. preferable. When this sampling signal rises, the sampling switch 106 is turned off. At this time, a voltage rise occurs contrary to the voltage drop described for the switching element 114, and the data signal line is turned off as shown in FIG. The potential of Sn rises. The rising voltage ΔV4 is obtained by the same equation as the falling voltage Δν2 described in the first embodiment. For this reason, the voltage charged in the liquid crystal layer of the pixel A (m-1, n) is higher than the original data signal potential by the above-mentioned rising voltage Δν 3 and AV 4. However, if the potential of the common electrode applied to the common electrode formed on the opposite substrate is set high in anticipation of the rising voltage, a voltage necessary for black display of the pixel can be applied to the liquid crystal layer. If the sampling switch 106 has a CMOS transistor structure, such a rise in voltage can be prevented.

Thereafter, the horizontal scanning signal (m-1) goes high and the horizontal scanning signal (m) goes low. Thereby, the scanning signal line Hm shown in FIG. 4 is selected, and all the switching elements 114 connected to the horizontal scanning line Hm are turned on.

Thereafter, the precharge operation and the data write operation are performed in the same manner as the scanning signal line Hm-1. However, both the precharge operation and the data write operation this time are performed at positive voltage. For this reason, the switch 190 in FIG. 1 is switched. As a result, the second precharge potential PV 2 from the second precharge power supply 174b is applied to the odd-numbered data signal lines S1, S3, -Sn-1, Sn + 1, Sn + 3,. (5.5 V) is supplied. On the other hand, even-numbered The first precharge potential PV1 (10.5 V) from the first precharge power supply 174a is supplied to the signal lines S2, S4, -Sn, Sn + 1, Sn + 3,. . Consider the potential of the data signal line Sn during the m-th horizontal scanning period. The potential of the data signal line Sn is precharged to a first precharge potential PV 1 (5.5 V) from a potential for performing black display at the pixel A (m-1, n). Is done. Thereafter, as shown in the timing chart of FIG. 9, when the sampling switch 106 is turned on at the falling edge of the sampling signal, switching noise occurs, and the switching noise is generated on the data signal line Sn. Superimposed. The switching noise generated when the sampling switch 106 is turned on acts in the direction of temporarily reducing the potential of the data signal line Sn, and the precharge causes the potential of the data signal line Sn to become black level potential. Acts in the same direction as the discharge direction to B l (IV).

Therefore, in the m-th horizontal scanning period, the above-described switching noise acts to accelerate the discharge at which the data signal line Sn becomes the black level potential B1. Therefore, even if the first precharge potential PV1 is higher than the conventional 4 V, the potential of the data signal line Sn is set from the first precharge potential to the data signal potential within the sampling period. can do.

In particular, the first precharge potential P V1 is set to 5.5 V, which is higher than the white level potential W 1 (5 V) during negative voltage drive. The reason is that during the m-th horizontal scanning period in Fig. 9, the white level potential Wl (5V ) And the black level potential B 1 (IV). At this time, the switching noise at the start of the sampling period acts to accelerate the discharge.

Note that, also during the m-th horizontal scanning period, when the sampling switch 172 is turned off, the above-described rising voltage △ V4 is generated, and as shown in FIG. 9, the potential of the data signal line Sn becomes higher than the black level potential B1. Is as described above.

(Description of Comparative Example 2)

FIG. 10 shows the first and second precharge potentials PV 1 and PV 2 shown in FIG. In addition, the timing chart of Comparative Example 1 when the conventional 4 V and 8 V are set is shown. In the m-th horizontal scanning period in Figure 10, the potential of the data signal line Sn is charged from the first precharge potential PV 1 (4 V) to the black level potential B 1 due to the adverse effect of switching noise. Before the sunring period has ended. As a result, the potential of the data signal line Sn becomes the potential Vb which is not the data signal potential corresponding to the original black, and the pixel A (m-1, n) is charged with a charge that does not reflect the original data. It can be seen that the image quality deteriorates.

Embodiment 3>

An electronic device including the liquid crystal device according to each of the above-described embodiments includes a display information output source 100000, a display information processing circuit 1002, a display driving circuit 1004 illustrated in FIG. It is configured to include a display panel 106 such as a liquid crystal panel, a clock generation circuit 1008, and a power supply circuit 110.10. The display information output source 100 00 includes a memory such as a ROM and a RAM, a tuning circuit that tunes and outputs a television signal, and the like, and a clock generation circuit 10 corresponding to the timing circuit block 20 described above. Outputs display information such as video signals based on the clock from 08.

The display information processing circuit 1002 corresponds to the data processing circuit block 30 in each of the above-described embodiments, and processes and outputs display information based on a clock from the clock generation circuit 1008. The display information processing circuit 102 can include a gamma correction circuit, a clamp circuit, and the like, in addition to the above-described amplification / polarity inversion circuit, phase expansion circuit, rotation circuit, and the like.

The drive circuit 104 includes the above-described scan-side drive circuit 102, data-side drive circuit 104, and precharge drive circuit 160, or data-side drive circuit 104, and includes a pixel region. 1006 is driven for display. The power supply circuit 110 supplies power to each of the circuits described above.

The electronic devices having such a configuration include a liquid crystal projector shown in FIG. 19, a personal computer (PC) and an engineering 'workstation (EWS)', a pager or a mobile phone for multimedia shown in FIG. Video processor with a processor, television, viewfinder or monitor Examples include a coder, an electronic organizer, an electronic desk calculator, a car navigation device, a POS terminal, and a device equipped with a touch panel.

The liquid crystal projector shown in FIG. 19 is a projection type projector using a transmissive liquid crystal panel as a light valve, and uses, for example, an optical system of a prism combining method. In FIG. 19, in the projector 110, the projection light emitted from the lamp unit 1102 of the white light source is provided inside the light guide 1104 by a plurality of mirrors 1106 and 2 sheets. The three dichroic mirrors 111, 108, R, G, and B separate the three primary colors, and each of the three active-matrix-type LCD panels that displays an image of each color. The light modulated by 1110B is incident on the Die-Croitsk prism 1112 from three directions.

In the dichroic prism 1 1 1 2, the light of red R and blue B is bent 90 °, and the light of green G goes straight, so that the images of each color are synthesized, and it is projected on the screen through the projection lens 1 1 1 4. A blank image is projected. In the projection type projector according to the present embodiment, since the liquid crystal device described in Embodiments 1 and 2 is applied, the first precharge potential PV1 and the second precharge potential PV Since 2 is asymmetric with respect to the intermediate potential of the voltage amplitude applied to the pixel, optical crosstalk in the projection display device can be prevented. The personal computer 1200 shown in FIG. 20 has a main body 1204 provided with a keyboard 122 and a liquid crystal display screen 1206.

Note that the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the above-mentioned various liquid crystal panels, but is also applicable to an image display device using electoran luminescence, a plasma display device, a CRT, or the like.

Claims

The scope of the claims

(1) A switching element electrically connected to a liquid crystal layer is arranged in each of a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines, and is applied to the liquid crystal layer. A liquid crystal device driven by inverting the polarity of the

Data-side driving means for supplying the data signal to each of the plurality of data signal lines;

Prior to supplying the data signal to each of the plurality of data signal lines, a positive or negative precharge having the same polarity as the polarity of the voltage applied to the liquid crystal layer of the pixel based on the data signal. A plurality of precharging switching means for precharging each of the plurality of data signal lines with a potential;

The positive and negative precharge potentials are set asymmetrically with respect to a central potential of a voltage amplitude between the first and fourth potentials, and the negative precharge potential is set to A liquid crystal device characterized in that the liquid crystal device is set closer to the first potential than to the central potential of the characteristic data voltage amplitude.

(2) In claim 1,

A liquid crystal device, wherein each of the plurality of switching elements is formed by an N-channel type transistor.

(3) In claim 1 or 2,

A plurality of sampling switching means for sampling the data signal supplied to each of the data signal lines based on a sampling signal output from the data-side driving means; The N Chang A liquid crystal device formed by a flannel transistor.

(4) In claim 2 or 3,

A liquid crystal device, wherein the N-channel transistor is a MOS transistor or a thin film transistor.

(5) In any one of claims 1 to 4,

The negative precharge potential is higher than the first potential.

(6) In any one of claims 1 to 5,

The positive precharge potential is lower than the third potential.

(7) A switching element electrically connected to a liquid crystal layer is arranged in each of a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines, and is applied to the liquid crystal layer. A liquid crystal device driven by inverting the polarity of the

Prior to supplying the data signal to each of the plurality of data signal lines, a positive polarity or the same polarity as the polarity of the voltage applied to the liquid crystal layer of the pixel based on the data signal is provided. A plurality of precharge switching means for precharging each of the plurality of data signal lines at a negative polarity precharge potential;

When the negative voltage is applied to the liquid crystal layer, the data signal changes within a range of the negative data voltage amplitude between the first potential and the second potential which is higher than the first potential. When a positive voltage is applied to the liquid crystal layer, the voltage changes within a range of a positive polarity temporary voltage amplitude between a third potential higher than the second potential and a fourth potential higher than the third potential,

The positive and negative precharge potentials are set asymmetrically with respect to the central potential of the data voltage amplitude between the first and fourth potentials, and A liquid crystal device, wherein a potential is set closer to the fourth potential than to a center potential of the positive polarity data voltage amplitude.

(8) In claim 7,

A liquid crystal device, wherein each of the plurality of switching elements is formed by a P-channel transistor.

(9) In claim 7 or 8,

A plurality of sampling switching means for sampling the data signal to be supplied to each of the data signal lines based on a sampling signal output from the data side driving means; A liquid crystal device formed by a flannel transistor.

(10) In claim 8 or 9,

A liquid crystal device, wherein the P-channel transistor is a MOS transistor or a thin film transistor.

(11) In any one of claims 7 to 10,

The liquid, wherein the negative precharge potential is lower than the fourth potential.

(12) In any one of claims 7 to 11,

The negative polarity precharge potential is higher than the second potential.

(13) In any one of claims 1 to 12,

A first precharge line connected to the precharge switching means for supplying the positive or negative precharge voltage to the odd-numbered data signal lines;

A second precharge line connected to the precharge switching means for supplying the positive or negative precharge potential to the even-numbered data line.

Each time at least one of the plurality of scanning signal lines is selected, a combination of connection between the first and second precharge lines and the positive and negative precharge potentials Is switched

A liquid crystal device characterized by the above-mentioned.

(14) A light source, the liquid crystal device according to any one of claims 1 to 13, which modulates light emitted from the light source, and projection optical means for projecting light modulated by the liquid crystal device. A projection display device comprising:

(15) An electronic apparatus comprising the liquid crystal device according to any one of claims 1 to 13.

(16) A liquid crystal device having a switching element electrically connected to a liquid crystal layer is provided in each of a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines, and the liquid crystal layer is provided in the liquid crystal layer. In a driving method of a liquid crystal device which drives by inverting the polarity of an applied voltage every predetermined period,

Supplying a scanning signal for selecting at least one of the plurality of scanning signal lines to the plurality of scanning signal lines;

Supplying the data signal to each of the plurality of data signal lines;

Prior to supplying the data signal to each of the plurality of data signal lines, a positive polarity or the same polarity as the polarity of a voltage applied to the liquid crystal layer of the pixel based on the data signal is provided. Precharging each of the plurality of data signal lines with a negative precharge potential;

The positive and negative precharge potentials are set asymmetrically with respect to the central potential of the data voltage amplitude between the first and fourth potentials, and the negative precharge potential is It is set closer to the first potential than the central potential of the negative polarity overnight voltage amplitude.

A method for driving a liquid crystal device, comprising:

(17) A plurality formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines A method of driving a liquid crystal device, which drives a liquid crystal device having a switching element electrically connected to a liquid crystal layer in each of the pixels by inverting the polarity of a voltage applied to the liquid crystal layer every predetermined period At

Supplying the data signal to each of the plurality of data signal lines;

Prior to supplying the data signal to each of the plurality of data signal lines, a positive polarity or a negative polarity having the same polarity as the polarity of the voltage applied to the liquid crystal layer of the pixel based on the data signal. At a precharge potential, each of the plurality of data signal lines is precharged,

When applying a negative voltage to the liquid crystal layer, the data signal changes within a range of a negative data voltage amplitude between a first electric potential and a second electric potential higher than the first electric potential. When a positive voltage is applied, the voltage changes within a positive data voltage amplitude range between a third potential higher than the second potential and a fourth potential higher than the third potential,

The positive and negative precharge potentials are set asymmetrically with respect to the central potential of the voltage amplitude between the first and fourth potentials, and the positive precharge potential is set to A method for driving a liquid crystal device, characterized in that the liquid crystal device is set to be closer to the fourth potential than the central potential of the voltage amplitude of the characteristic voltage.