JP2001159883A - Driving method for optoelectronic device, drive circuit therefor, and optoelectronic device as well as electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display high quality gradation by binary processing the signals impressed to data lines. SOLUTION: When respective pixels are provided with memories and are subjected to assigning of, for example, 8 intensity levels, one field(1f) is divided to seven sub-fields (Sf1, Sf2,..., Sf7) according to gray scale characteristics and data Ds instructing the on or off of the pixels is written into the memories of the corresponding pixels according to the gray scale of the pixels and the pixels are turned on or off in accordance with the written data. As a result, during one field the periods during which the pixels are turned on or off are subjected to PWM modulation, so that the assigning of the intensity levels is eventually executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electro-optical device for performing gradation display by pulse width modulation, a driving method and a driving circuit thereof, and an electronic apparatus.

[0002]

2. Description of the Related Art An electro-optical device, for example, a liquid crystal display device using liquid crystal as an electro-optical material is a cathode ray tube (CRT).
It is widely used as a display device in place of a display unit of various information processing devices and a wall-mounted television.
Here, in the conventional electro-optical device, for example, an element substrate provided with pixel electrodes arranged in a matrix or a switching element connected to the pixel electrodes, and a counter electrode facing the pixel electrodes are formed. It is composed of an opposing substrate and a liquid crystal as an electro-optical material filled between the two substrates. In such a configuration, when a scanning signal is applied to the switching element via the scanning line, the switching element is turned on. When an image signal of a voltage corresponding to the gradation is applied to the pixel electrode via the data line in the conductive state, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Stored. After the charge storage, even if the switching element is turned off, the charge storage in the liquid crystal layer is maintained by the capacitance of the liquid crystal layer itself, the storage capacitance, and the like. As described above, when the switching elements are driven and the amount of charge to be stored is controlled according to the gradation, the alignment state of the liquid crystal changes for each pixel, so that the density changes for each pixel. Therefore, it is possible to perform gradation display.

At this time, since it is sufficient to accumulate charges in the liquid crystal layer of each pixel during a part of the period, first, each scanning line is sequentially selected by a scanning line driving circuit, and secondly,
In the scanning line selection period, the data lines are sequentially selected by the data line driving circuit, and thirdly, the selected data lines are sampled with an image signal of a voltage corresponding to a gray scale. Time-division multiplex driving in which a line is shared by a plurality of pixels becomes possible.

[0004]

However, the image signal applied to the data line is a voltage corresponding to the gradation, that is, an analog signal. For this reason, a peripheral circuit of the electro-optical device requires a D / A conversion circuit, an operational amplifier, and the like, thereby increasing the cost of the entire device. Further, display unevenness occurs due to the characteristics of the D / A conversion circuit and the operational amplifier and the non-uniformity of various wiring resistances, so that high-quality display is extremely difficult.
In particular, there is a problem that it becomes remarkable when performing high-definition display.

The present invention has been made in view of the above circumstances, and has as its object to provide an electro-optical device capable of high-quality and high-definition gradation display, a driving method thereof, a driving circuit thereof, Another object of the present invention is to provide an electronic apparatus using the electro-optical device.

[0006]

In order to achieve the above object, a first aspect of the present invention comprises a memory, a pixel electrode provided corresponding to the memory, and a counter electrode facing the pixel electrode. A method for driving an electro-optical device that causes each of a plurality of pixels to display a gradation, wherein one field is divided into a plurality of subfields, and in each of the subfields, ON or OFF according to the gradation of the pixel is performed. Instructed data is written in the memory of each of the pixels, and the plurality of pixels are turned on or off simultaneously based on the written data.

According to this configuration, in one field, the ON or OFF period of the pixel is pulse width modulated in accordance with the gradation of the pixel, so that gradation display by effective value control is performed. . At this time, in each subfield, since the pixel is only turned on or off, the instruction signal to the pixel can be data (that is, a digital signal that can take only the H level or the L level). No processing circuit is required. As a result,
According to the first aspect, a D / A conversion circuit, an operational amplifier, and the like become unnecessary, and display unevenness caused by non-uniformity of these circuit characteristics and various wiring resistances is suppressed.

Further, according to the first invention, the pixels are turned on or off all at once after data is written to each memory, so that the period during which the pixels are turned on or off in each subfield extends over each pixel. Become equal. For this reason, in the first invention, high-quality and high-definition gradation display is possible.

In the present invention, one field is a period required to form one raster image by performing horizontal scanning and vertical scanning in synchronization with a horizontal scanning signal and a vertical scanning signal. It is used in a meaning. Therefore, it should be noted that one frame in the non-interlace system or the like also corresponds to one field in the present invention.

[0010] The scanning signal is transmitted from a memory to a DRAM (Dy).
In the case of a destructive readout configuration such as a dynamic random access memory, it is only necessary to supply the data sequentially to each of the scanning lines during the period of each subfield.
Non-destructive readout (self-holding) configuration such as (Static Random Access Memory) requires only scanning lines including pixels that display intermediate gradations or scanning lines that include pixels that change display contents. It may be configured to supply the data sequentially or randomly.

According to a second aspect of the present invention, there is provided an electro-optical device for gradation-displaying a plurality of pixels each including a memory, a pixel electrode provided corresponding to the memory, and a counter electrode facing the pixel electrode. The driving method of the above, one field is divided into a plurality of sub-fields, in each of the sub-fields, data for instructing on or off in accordance with the gradation of the pixel, respectively, is written to the memory of the pixel, For each pixel for which data has been written to the memory,
The pixel is sequentially turned on or off.

According to the second aspect, the same effect as that of the first aspect can be obtained. Furthermore, according to the present invention, there is no need to perform control for simultaneously turning on or off the pixels after writing data in the memory for the signal applied to the pixel electrode as in the above invention. As compared with the first aspect, there is an advantage that the configuration of the drive circuit can be simplified.

In the first and second aspects of the present invention, a reference signal that repeats level inversion at predetermined time intervals is applied to the counter electrode, and a case where the pixel is turned on is applied to the pixel electrode. When applying an ON signal at a level different from the reference signal and turning off the pixel,
An off signal having the same level as the reference signal may be applied.

For example, when a liquid crystal is used as the electro-optical material, the situation in which a DC component is applied to the liquid crystal layer can be avoided by inverting the level of the reference signal at predetermined time intervals as in the above invention. Degradation can be prevented.

Further, the period of the level inversion of the reference signal may be different from the time length of the field.

By doing so, the period of the level inversion of the reference signal can be set arbitrarily.
The cycle of the level inversion of the reference signal can be set to the cycle in which flicker is reduced most.

Next, in order to achieve the above object, the present third
The invention is arranged corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and when a scanning signal is supplied to the scanning line, indicates on or off supplied to the data line. A memory for writing data to be written, a pixel electrode provided corresponding to the memory, and based on data indicating on or off written in the memory, select one of an on signal and an off signal, A drive circuit of an electro-optical device that drives a plurality of pixels including a first switching element applied to the pixel electrode and a counter electrode facing the pixel electrode, the drive circuit including a plurality of subfields obtained by dividing one field. A scanning line driving circuit that supplies the scanning signal to the scanning line, and a scanning line that is supplied to a scanning line corresponding to each pixel in each of the subfields. A data line driving circuit that supplies data for instructing ON or OFF according to the gradation of the pixel to a data line corresponding to the pixel, and data written in a memory of the pixel. A control circuit for controlling signals applied to the pixel electrode and the counter electrode so as to turn on or off the plurality of pixels simultaneously.

The third aspect of the present invention embodies the first aspect of the present invention as a driving circuit for an electro-optical device, and has the same advantages as the first aspect of the present invention.

Further, according to a fourth aspect of the present invention, when a scanning signal is supplied to the scanning line, the data line is supplied to the data line when the scanning signal is supplied to the scanning line. A memory for writing data for instructing on or off, a pixel electrode provided corresponding to the memory,
A first switching element for selecting one of an on signal and an off signal based on data indicating on or off written in the memory and applying the selected signal to the pixel electrode, and opposing the first switching element; A driving circuit of an electro-optical device that drives a plurality of pixels including a counter electrode, and in each of a plurality of subfields obtained by dividing one field, a scanning line driving circuit that supplies the scanning signal to the scanning line; In each of the sub-fields, during a period in which the scanning signal is supplied to a scanning line corresponding to each pixel, data for instructing ON or OFF according to the gradation of the pixel is applied to a data line corresponding to the pixel. A data line drive circuit to be supplied, and for each pixel for which data has been written to the memory, such that the pixel is sequentially turned on or off,
A control circuit for controlling signals applied to the pixel electrode and the counter electrode.

In the fourth aspect, the second aspect is embodied as a driving circuit for an electro-optical device, and the same effects as those of the second aspect can be obtained.

The data line driving circuit according to the third or fourth aspect of the present invention includes: a shift register for sequentially shifting and outputting a latch pulse signal supplied at the beginning of a horizontal scanning period according to a clock signal; And a latch circuit for simultaneously latching the data distributed to a plurality of systems by a signal shifted by the shift register.

Since one field is divided into a plurality of subfields, in a configuration in which data is supplied in a dot-sequential manner in each subfield, a situation in which writing time to pixels is not sufficient is expected. Therefore, if the configuration is such that the data distributed to a plurality of systems is simultaneously latched as in the present invention, the number of stages of the shift register is reduced and the time required for the latch circuit to latch the data is also reduced. Becomes possible.

Further, the data line drive circuit sequentially shifts and outputs a latch pulse signal supplied at the beginning of a horizontal scanning period in accordance with a clock signal, and the data is shifted by the shift register. A first latch circuit for sequentially latching the data, and the data latched by the first latch circuit;
While latching based on the latch pulse signal,
It is also desirable to have a configuration including a second latch circuit that simultaneously outputs the data signal to a corresponding data line.

As described above, before the data is supplied to the data line, the data is temporarily latched by the first latch circuit in a dot-sequential manner, and the latched signal is supplied to the second latch circuit.
Latch circuit is simultaneously latched by a latch pulse signal supplied at the beginning of the horizontal scanning period, and supplied to the data line, it is possible to secure a relatively long time of one horizontal scanning period as a pixel writing time. It becomes possible.

Now, in such a configuration, the first
Is desirably configured to simultaneously latch the data distributed to a plurality of systems by a signal shifted by the shift register.

According to this configuration, the number of stages of the shift register can be reduced, and the time required for the first latch circuit to latch data can be reduced.

In a configuration in which the data line driving circuit includes a shift register, in one subfield, after the scanning line driving circuit supplies the scanning signal to the scanning line, the clock signal is supplied to the shift register. It is preferable to provide a clock signal supply control circuit for stopping the supply and restarting the supply of the clock signal when the next subfield starts.

In general, a shift register is provided with a very large number of clocked inverters for inputting a clock signal at a gate, and therefore, when viewed from a clock signal supply source,
The shift register becomes a capacitive load. On the other hand, during the period from “after the scanning line driving circuit supplies a scanning signal to all of the scanning lines in one subfield” to “the next subfield starts”, the shift register on the data line side operates. You don't have to. Therefore, by stopping the supply of the clock signal to the shift register by the clock signal supply control circuit only during the above period, the power consumed due to the capacitive load of the shift register can be reduced.

Next, in order to achieve the above object, a fifth aspect of the present invention is directed to a plurality of scanning lines, a plurality of data lines, and a plurality of scanning lines and a plurality of data lines provided corresponding to respective intersections of the data lines. An electro-optical device comprising: a pixel, when a scanning signal is supplied to a scanning line corresponding to the intersection, the pixel supplies data for instructing ON or OFF of the pixel supplied to the data line. A writing memory, a pixel electrode provided corresponding to the memory, and selecting one of an on signal and an off signal based on data indicating on or off written in the memory; , And a counter electrode facing the pixel electrode.

When liquid crystal is used as the electro-optical material, it is necessary to periodically invert the polarity of the voltage applied to the pixel electrode and the counter electrode in order to avoid a situation in which a DC component is applied to the liquid crystal layer. According to the present invention, if either the ON signal or the OFF signal is selected by the first switching element, the level of the data for instructing ON or OFF is inverted according to the polarity inversion timing. Since there is no need, there is an advantage that the configuration of the electro-optical device can be simplified.

In the fifth aspect, in each of a plurality of subfields obtained by dividing one field, a scanning line driving circuit for supplying the scanning signal to the scanning line, and a pixel in each of the subfields In a period in which the scanning signal is supplied to the corresponding scanning line, the data according to the gradation of the pixel is written to the data line driving circuit that supplies the data line corresponding to the pixel to the memory of the pixel. A control circuit for controlling signals applied to the pixel electrode and the counter electrode so as to simultaneously turn on or off the plurality of pixels based on the obtained data.

According to the present invention, the first invention is embodied as an electro-optical device, and the same effects as those of the first invention can be obtained.

Further, in the fifth invention, in each of a plurality of subfields obtained by dividing one field, a scanning line driving circuit for supplying the scanning signal to the scanning line, and in each of the subfields, A data line driving circuit that supplies the data corresponding to the gray scale of the pixel to a data line corresponding to the pixel during a period in which the scanning signal is supplied to the scanning line corresponding to the pixel; A control circuit for controlling a signal applied to the pixel electrode and the counter electrode so as to turn on or off the pixel sequentially for each written pixel may be provided.

The present invention embodies the second invention as an electro-optical device, and provides the same effects as the second invention.

The memory in each of the above inventions is:
A second switching element that is turned on by the scanning signal; and, when the second switching element is turned on, writes data on a corresponding data line to the second switching element.
And a capacitor for holding the written data when the switching element is turned off.

In this configuration, since it is a DRAM, simplification is easy.

Here, the second switching element is
It is desirable that the P-channel type transistor and the N-channel type transistor be configured in a complementary manner.

When the second switching element is a one-channel transistor, it is necessary to set the data voltage in consideration of the threshold voltage. No need to consider.

On the other hand, the memory includes a second switching element that is turned on by the scanning signal, and a second switching element.
When the second switching element is turned off, the output of one of the inverters holding the written data is connected to the input of the other inverter when the second switching element is turned off. Is also desirable.

In this configuration, since the data is self-stored to be an SRAM, the operation margin can be expanded.

In each of the above inventions, the first switching element includes a first switch for selecting one of signals applied to the pixel electrodes according to data written to the memory, and a first switch for selecting the other signal. And a second switch to be selected. It is preferable that the first and second switches have a configuration in which a P-channel type transistor and an N-channel type transistor are complementarily combined, respectively.

When the first and second switches are single-channel transistors, it is necessary to set the voltage level of the signal applied to the pixel electrode in consideration of the threshold voltage. According to the aspect, it is not necessary to consider the threshold voltage. In particular, if the second switching element is of a complementary type, it is possible to use only two levels corresponding to H and L.

According to one aspect of the invention, it is preferable that the plurality of pixels, the scanning line driving circuit, and the data line driving circuit are formed on a semiconductor substrate, and the pixel electrode has reflectivity.

Since the electron mobility of the semiconductor substrate is high, it is possible to reduce the size of the switching elements formed on the substrate and the constituent elements of the drive circuit as well as the high-speed response.

Further, in order to achieve the above object, the electronic apparatus according to the sixth aspect of the present invention includes the above-mentioned electro-optical device, so that a D / A conversion circuit and an operational amplifier are not required. Furthermore, these D / A conversion circuits,
It is not affected by the characteristics of operational amplifiers and non-uniformities such as various wiring resistances. Therefore, according to this electronic device,
The cost can be reduced, and high-quality and high-definition gradation display can be performed.

[0046]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Theoretical Assumption> First, before describing an electro-optical device according to an embodiment of the present invention, a theoretical assumption of a gray scale display according to the present invention will be briefly described. In general, in a liquid crystal device using liquid crystal as an electro-optical material, the relationship between the effective voltage value applied to the liquid crystal layer and the relative transmittance (or reflectance) is a normally black mode in which black display is performed in the absence of a voltage. For example, the relationship is as shown in FIG. That is, as the effective voltage value applied to the liquid crystal layer increases,
The transmittance increases nonlinearly and saturates. Here, the relative transmittance is a value obtained by normalizing the minimum value and the maximum value of the transmitted light amount as 0% and 100%, respectively.

Here, it is assumed that the electro-optical device according to the present embodiment performs 8-gradation display, and that gradation (shading) data represented by 3 bits indicates the transmittance shown in FIG. I do. At this time, the transmittance is 0% and the transmittance is 100
%, And the effective values of the voltages applied to the liquid crystal layer at the intermediate transmittance excluding% are V1, V2,..., And V6, respectively, conventionally, these voltages are applied to the liquid crystal layer via the data lines. The configuration was applied. For this reason, as described in the related art, the voltages V1 and
V2,..., And V6 are easily affected by the characteristics of analog circuits such as a D / A conversion circuit and an operational amplifier, and variations in various wiring resistances. It has been difficult to display high quality and high definition gradation.

Therefore, in the electro-optical device according to the present embodiment, first, the voltage instantaneously applied to the liquid crystal layer corresponds to, for example, the voltage VL (= 0) corresponding to the L level and the H level. A configuration in which one of the voltages VH is used is adopted.
On the other hand, in this configuration, if the voltage VL is applied to the liquid crystal layer over the entire period of one field (1f), the display is turned off during the entire period, so that the transmittance becomes 0%.
Further, in one field period, the ratio of the period during which the voltage VL is applied to the liquid crystal layer to the period during which the voltage VH is applied is controlled so that the effective voltage applied to the liquid crystal layer is V1, V2,.
.., V6, gradation display corresponding to the voltage is possible. Even when the effective voltage value applied to the liquid crystal layer exceeds V7, the transmittance is 100% because of the saturation.

Therefore, in the electro-optical device according to the present embodiment, second, FIG. 4B shows the period for applying the voltage VL to the liquid crystal layer and the period for applying the voltage VH. Thus, one field (1f) period is divided into seven periods. The seven divided periods are referred to as subfields Sf1, Sf2,..., Sf7 for convenience.

On the other hand, the electro-optical device according to the present embodiment
For example, in the case of a first driving method described later, a memory is provided for each pixel, while the subfields Sf1, Sf2,.
In each of Sf7, after sequentially writing data indicating which of the voltage VL and the voltage VH is to be applied to the liquid crystal layer of the corresponding pixel to each memory, the data written to all the pixels Is turned on or off all at once based on the Therefore, for example, in a first driving method described later, the sub-fields Sf1 and Sf
2,..., Sf7, a period for writing data to the memory is a writing period Va as shown in FIG. 4B, and a period for applying a voltage according to the data to the liquid crystal layer is as follows. As shown in the figure, the application period Sf1b,
Sf2b,..., Sf7b.

For example, when the gradation data of a certain pixel is (001) (ie, when performing gradation display with the transmittance of the pixel being 14.3%), one field (1f) period During the application period Sf1b of the subfield Sf1, the voltage VH is applied to the liquid crystal layer of the pixel, and the voltage VL (= 0) is applied in other periods. Here, the effective voltage value is 2 of the instantaneous voltage value.
The application period Sf1b in the subfield Sf1 is determined by the square root obtained by averaging the power to one period (one field) with respect to one field (1f).
1 / VH) Set to ² time length. As a result, the effective value of the voltage applied to the liquid crystal layer during the period of one field (1f) becomes the voltage V1, so that the transmittance of the pixel becomes 1
Intermediate gradation display of 4.3% becomes possible.

Further, for example, when the gradation data is (010) (ie, when performing gradation display with the transmittance of the pixel being 28.6%), the subfield of one field (1f) period In the application period Sf1b of Sf1 and the application period Sf2b of the subfield Sf2, the voltage VH is applied to the liquid crystal layer of the pixel, and the voltage VL is applied in other periods. Here, the accumulation period of the application periods Sf1b and Sf2b is set to a time length of (V2 / VH) ² for one field (1f). Thus, the effective value of the voltage applied to the liquid crystal layer in one field (1f) period becomes the voltage V2, so that a halftone display in which the transmittance of the pixel is 28.6% becomes possible. At this time, since the application period Sf1b is set to a time length of (V1 / VH) ² for one field (1f), the application period Sf2b is set to (V2 / VH) for one field (1f). ² - (V1 / VH) ² of may be set to a time length.

Similarly, for example, when the gradation data is (011) (that is, when performing gradation display with the transmittance of the pixel being 42.9%), the sub-field in one field (1f) period An application period Sf1b of the field Sf1,
In the application period Sf2b of the subfield Sf2 and the application period Sf3b of the subfield Sf3, the voltage VH is applied to the liquid crystal layer of the pixel, and the voltage VL is applied in other periods. Here, the application period Sf
The accumulation period of 1b, Sf2b and Sf3b is set to a time length of (V3 / VH) ² for one field (1f). Thereby, the effective voltage value applied to the liquid crystal layer in one field (1f) period becomes the voltage V3,
Intermediate gradation display in which the transmittance of the pixel is 42.9% becomes possible. At this time, the cumulative period of the application periods Sf1b and Sf2b is (V2 / V
H) Since the time length is set to ² , the application period Sf3b is (V3 / V
H) ² − (V2 / VH) ² may be set as the time length.

Hereinafter, similarly, the subfield Sf4
Is set to a time length of (V4 / VH) ^2- (V3 / VH) ² for one field (1f), and the application period Sf5b of the subfield Sf5 is set to ( V5 / VH) ^2- (V4 / V
H) The time length is set to ² and the application period Sf6b of the subfield Sf6 is set to (V6
/ VH) ² − (V5 / VH) ² .

On the other hand, the write period Va is desirably the same period in each subfield in consideration of the configuration and performance of the drive circuit. Therefore, one field (1
In the period f), the application period Sf7b of the subfield Sf7 is a period excluding the application periods Sf1b, Sf2b,..., Sf6b determined as described above, and the writing period Va of each subfield. It will be determined as. However, the application periods Sf1b, Sf2b,.
It is necessary that the accumulation period of Sf7b is longer than the time length of (V7 / VH) ² for one field (1f). The reason is that, when the gradation data is (111), the liquid crystal layer of the pixel has the respective application periods Sf1b, Sf
2b,..., Sf7b, the voltage VH is applied. If the accumulation period is longer than the time length of (V7 / VH) ² for one field (1f), 1 This is because the effective value of the voltage applied to the liquid crystal layer of the pixel in the field period (1f) exceeds V7 and the transmittance of the pixel becomes 100%.

As described above, one field is divided into seven subfields Sf1, Sf2,..., Sf7, and the application periods Sf1b, Sf2b,.
b, and writing is performed according to the gradation data, the voltages applied to the liquid crystal layer are VL and V
Despite the two values of H, gradation display corresponding to each transmittance is possible. Therefore, the configuration for this will be described below with reference to the drawings.

<Embodiment> First, an electro-optical device according to an embodiment of the present invention is a liquid crystal device using liquid crystal as an electro-optical material. As will be described later, an element substrate and an opposing substrate have a fixed gap therebetween. And a liquid crystal as an electro-optical material is sandwiched in the gap. Further, in the electro-optical device according to the present embodiment, a semiconductor substrate is used as an element substrate, in which a peripheral driving circuit and the like are formed together with transistors for driving pixels.

<Electrical Configuration> FIG. 1 is a block diagram showing an electrical configuration of the electro-optical device. In the figure, a timing signal generation circuit 200 includes a vertical scanning signal Vs and a horizontal scanning signal Hs supplied from a higher-level device (not shown).
In accordance with the dot clock signal DCLK, various timing signals and clock signals described below are generated to function as a kind of control circuit. First,
First, the AC drive signal FR is a signal which is applied to a counter electrode of a counter substrate with its level inverted every field (one frame) as shown in FIGS. 6 and 7, for example.
Second, the start pulse DY is a pulse signal output first at each of the subfields Sf1, Sf2,..., Sf7 obtained by dividing one field, as shown in FIGS. Third, the clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side) as shown in FIG. Fourth, the latch pulse LP is
As shown in (1), the pulse signal is output at the beginning of the horizontal scanning period, and is output at the time of the level transition (that is, rising and falling) of the clock signal CLY. Fifth, the clock signal CLX is a signal that defines a so-called dot clock. Sixth, the signal V
Off is the same signal as the AC drive signal FR as shown in FIGS. 6 and 7, for example, and is a signal applied to the pixel electrode 118 shown in FIG. 2 when the pixel is to be turned off. . Seventh, the signal Von is a signal applied to the pixel electrode 118 when the pixel is to be turned on. The mode of the signal Von will be described later in detail in the description of the driving method.

On the other hand, the display area 101 on the element substrate
In a, a plurality of scanning lines 112 are indicated by X (row) in the figure.
And a plurality of data lines 11
4 are formed extending along the Y (column) direction.
Pixels 110 (described later) are provided at intersections of the scanning lines 112 and the data lines 114, and are arranged in a matrix. Here, for convenience of explanation, in the present embodiment, the total number of the scanning lines 112 is m and the data lines 11
While the total number of 4 is n (m and n are each an integer of 2 or more), a matrix-type display device of m rows × n columns will be described, but the present invention is not limited thereto.

Next, the scanning line driving circuit 130 is a so-called Y shift register, which transfers a start pulse DY supplied at the beginning of each subfield in accordance with a clock signal CLY, and scans each of the scanning lines 112. The signals G1, G2, G3,..., Gm are sequentially and exclusively supplied.

The data line driving circuit 140 converts the data Ds into data signals d1, d2, d during a certain horizontal scanning period.
,... Dn are sequentially supplied to the respective data lines 114. FIG. 3 shows the data line driving circuit 1
It is a block diagram which shows the specific structure of 40. As shown in the figure, the data line driving circuit 140 includes an X shift register 1410 and a latch circuit 1420. The X shift register 1410 outputs the latch pulse LP supplied at the beginning of the horizontal scanning period to the clock signal CL.
X, and latch signals S1, S2, S3,.
, And Sn are sequentially output. Latch circuit 1
420 latches the data Ds output from the data conversion circuit 300 at the falling edges of the latch signals S1, S2, S3,.
.. Dn are sequentially output to the corresponding data lines 114.

Returning to the description of FIG. 1, the data conversion circuit 300 determines whether the subfields Sf1, Sf2,.
For each f7, gradation data D0, D indicating the display gradation of the pixel
1, D2 is converted into data Ds for instructing ON or OFF of the pixel. Specifically, the data conversion circuit 300 is supplied in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK, and furthermore, 3-bit gradation data D0, D corresponding to each pixel.
1, D2 are defined as subfields Sf1, Sf2,.
The data is converted into data Ds for each Sf7, and the details of the conversion are as shown in FIG. To explain with reference to this figure, if the gradation data D0, D1, and D2 corresponding to a certain pixel are, for example, (010), the data conversion circuit 300 sets the H at the writing timing of the pixel in the subfields Sf1 and Sf2. Level D
s, while subfields Sf3, Sf
4,..., Sf7, the L level is output as data Ds at the write timing of the pixel.

Here, the data conversion circuit 300 needs to have a configuration for recognizing which subfield is one of the fields. For this configuration, for example,
The following method can be used. That is, in the present embodiment, the data conversion circuit 300 may have a configuration in which a clock signal CLY is used as a clock, a start pulse DY is enabled, and a 3-bit counter that presets an initial value “1” is provided. In short, by providing a 7-ary counter for counting the start pulse DY and referring to the count result, the current subfield can be recognized.

In this embodiment, since the potential of the counter electrode 108 is inverted for each field by the AC drive signal FR for AC drive, the start pulse DY is supplied inside the data conversion circuit 300. In a configuration in which a counter for counting and resetting the counter result at the level transition (rising and falling) of the AC drive signal FR is provided, and the count result is referred to,
The current subfield can be recognized.

Since the data Ds needs to be output in synchronization with the operations of the scanning line driving circuit 130 and the data line driving circuit 140, the data conversion circuit 300 supplies the start pulse DY and the horizontal scanning A synchronized clock signal CLY, a latch pulse LP defining the beginning of a horizontal scanning period, and a clock signal CLX corresponding to a dot clock signal are supplied. If the counter result is reset by the level transition of the AC drive signal FR in order to recognize the current subfield, the AC drive signal FR is also converted to the data conversion circuit 300 as shown by the broken line. Is supplied to the system.

The scanning line driving circuit 130, data line driving circuit 140, timing signal generation circuit 200, and data conversion circuit 300 use a single power supply circuit (not shown) as a power supply. Therefore, the H level and L level of the output signal from each section of the circuit correspond to the higher voltage VD of this power supply circuit.
D and the lower voltage VSS.

<Configuration of Pixel> Here, a detailed configuration of the pixel 110 will be described. FIG. 2 is a diagram illustrating an example of the pixel 110 in the electro-optical device. In FIG. 1, for generalization, in FIG. 1, an i-th (i is an integer satisfying 1 ≦ i ≦ m) scanning line 112 counted from the top and a j (j Indicates an pixel 110 corresponding to the intersection with the (the integer satisfying 1 ≦ j ≦ n) th data line 114.

As shown in this figure, the pixel 110
A kind of DRAM including a transistor (MOS type FET) Ta1 and a capacitor 117 is provided. That is, the gate of the transistor Ta1 is connected to the scanning line 112, the source is connected to the data line 114, and the drain is connected to the capacitor 117.
Is connected to one end.

Next, one end of the capacitor 117 is connected to the signal V
between the P-type transistors Tb1 and Nb connected in series between
It is connected to the gate of the channel type transistor Tb2. That is, the transistors Tb1, Tb2
Functions as an analog multiplexer that selects the signal Von or the signal Voff. Note that a signal line to which the signal Von and the signal Voff are supplied is common to each pixel 110.

On the other hand, a counter electrode 108 is formed on the counter substrate so as to face the pixel electrode 118. Further, a liquid crystal 105 serving as an electro-optical material is sandwiched between the pixel electrode 118 and the counter electrode 108 to form a liquid crystal layer. Here, as described later, the opposite electrode 108
A transparent electrode formed on the entire surface of the opposing substrate.
Common over ten. The potential of the counter electrode 108 is maintained at a constant value in a normal electro-optical device, but in the electro-optical device according to the present embodiment, the AC drive signal FR described above is applied to the potential of 1 The level is inverted for each field.

With the above configuration, when the scanning signal Gi is supplied to the scanning line 112 and becomes H level during the writing period Va, the data signal dj (data Ds) supplied to the data line 114 is supplied to the capacitor 117. Written. On the other hand, each application period Sf1b, Sf2b,.
In f7b, the capacitor 1 in the immediately preceding writing period Va
If the H-level data signal dj is written to the transistor 17, the signal Voff is generated by the transistors Tb1 and Tb2.
Is selected and applied to the pixel electrode 118, and if the L-level data signal dj has been written to the capacitor 117 in the immediately preceding writing period Va, the transistors Tb1 and Tb2 The signal Voff is selected and applied to the pixel electrode 118.

In the conventional electro-optical device, in order to convert the voltage applied to the liquid crystal layer of each pixel into AC, a data signal supplied to each data line is predetermined according to a table stored in advance. It was necessary to invert the level in the cycle of. On the other hand, in the case where the pixel is configured as described above, it is possible to realize the alternating voltage applied to the liquid crystal layer by changing the level of the power supply voltage applied to the transistors Tb1 and Tb2. Therefore, an advantage is obtained that the table required in the above-described conventional electro-optical device is not required.

<First Driving Method> Next, a first driving method which is one mode of the driving method of the electro-optical device according to the above-described embodiment will be described. FIG. 6 is a timing chart for explaining the operation of the electro-optical device. Note that, as shown in the figure, the signal Von used in the present driving method includes subfields Sf1, Sf2,.
In the writing period Va in Sf7, the level is the same as the AC drive signal FR, while the application period Sf1b,
Sf2b,..., Sf7b are signals having an inversion level with respect to the AC drive signal FR.

As shown in this figure, the AC drive signal FR is applied to the counter electrode 108 after the level is inverted every field (1f). On the other hand, the start pulse DY
Is supplied at the start of each subfield obtained by dividing one field (1f) as described above.

Here, in one field (1f) in which the AC drive signal FR becomes H level, the sub-field S
When a start pulse DY defining the start of f1 is supplied, the scanning line drive circuit 130 (see FIG. 1) transfers the start pulse DY in accordance with the clock signal CLY. As a result, the scanning signal G1 is written within the writing period Va. , G2, G3,
.., Gm are sequentially output. The scanning signals G1, G2, G3,..., Gm each have a pulse width corresponding to a half cycle of the clock signal CLY. Here, first, the scanning signal G1 is applied to the scanning line driving circuit 1
Let us consider the case of output from 30.

When the scanning signal G1 is output, the first scanning line 112 counted from the top in FIG. 1 is selected. As a result, all the transistors Ta1 of the pixel 110 corresponding to the intersection with the scanning line 112 are turned on. Becomes On the other hand, a latch pulse LP is output at the falling edge of the clock signal CLY. The X shift register 1410 in the data line driving circuit 140 transfers the latch pulse LP according to the clock signal CLX. As a result, the latch signals S1, S2, S3,.
H). Note that the latch signals S1, S2,
Each of S3,..., Sn has a pulse width corresponding to a half cycle of the clock signal CLX.

Then, the latch circuit 1420 in FIG.
Is the data D to the pixel 110 corresponding to the intersection of the first scanning line 112 counted from the top and the first data line 114 counted from the left at the falling of the latch signal S1.
s is latched and output as a data signal d1 to the first data line 114 counted from the left. Next, the latch signal S2
At the falling edge of the first scanning line 112 counted from the top
Then, the data Ds to the pixel 110 corresponding to the intersection with the second data line 114 counted from the left is latched and output as the data signal d2 to the second data line 114 counted from the left. Thereafter, similarly, the first scanning line 11 counted from the top
2 and j counted from the left (j is an integer satisfying 1 ≦ j ≦ n)
The data Ds to the pixel 110 corresponding to the intersection with the first data line 114 is sequentially latched and output to the data line 114 as a data signal dj. The same operation is repeated until the data signal dn is supplied to the n-th data line 114 counted from the left. The data conversion circuit 300
It goes without saying that the grayscale data of each pixel 110 is converted into data Ds and output in accordance with the latch timing of the latch circuit 1420.

As a result, in the writing period Va of the sub-field Sf1, the capacitors 117 of all the pixels 110 have the data signals D instructing ON or OFF of the pixels.
s will be written respectively.

Here, in the writing period Va, each pixel electrode 118 has a signal Von having the same level as the signal Voff having the same level as the AC drive signal as described above.
Is applied to the counter electrode 108, however, the alternating drive signal FR itself is applied to the counter electrode 108, so that the effective voltage value applied to each liquid crystal layer is zero.

Next, when the operation shifts to the application period Sf1b, the signal Von has an inverted level with the signal Voff. Therefore, in all the pixels 110, either the signal Voff or the signal Von is selected according to the level of the data Ds written in the capacitor 117, and the pixel electrode 11
8 are applied simultaneously. Specifically, in the immediately preceding writing period Va, the capacitor 1 of a certain pixel 110
When the data Ds at the L level is written in the signal 17, the signal Voff is selected by the transistors Tb 1 and Tb 2 and applied to the pixel electrode 118. On the other hand, when the data Ds at the H level is written, the signal Von is output. The selected pixel is applied to the pixel electrode 118.

At this time, the signal Vof is applied to the opposite electrode 108.
Since the same AC drive signal FR as f is applied,
In the pixel 110 in which the L level data Ds is written to the capacitor 117, the effective voltage value applied to the liquid crystal layer is zero, whereas in the pixel 110 in which the H level data Ds is written, the voltage is applied to the liquid crystal layer. The effective voltage value is a square root obtained by averaging the square of (the absolute value of) the difference voltage between the signal Von and the AC drive signal FR over one cycle (one field). Here, signals Von, Voff
The voltage VDD corresponding to the H level and the voltage VSS (= 0) corresponding to the L level are respectively converted to voltages VH and VH.
When L (= 0) is set, the difference voltage between the signal Von and the signal Voff becomes the voltage VH. Strictly speaking, the voltage applied to the pixel electrode 118 must take into account the threshold voltages of the transistors Ta1, Tb1, and Tb2. ) Is not the voltage VH, but is described here as equal for convenience of explanation, and the case where the threshold voltage of the transistor is considered will be described later.

The same operation is repeated every time a start pulse DY defining the start of a subfield is supplied. That is, the subfields Sf2, Sf3,.
.., Sf7, first, data Ds is written to the capacitor 117 of each pixel during the writing period, and secondly, AC driving applied to the counter electrode 108 during the application period. The same signal Voff as the signal FR or the signal Von whose level is inverted is applied to the pixel electrode 118 according to the written data Ds. On this occasion,
The data conversion circuit 300 (see FIG. 1)
Regarding the conversion from 0, D1, D2 to data Ds, the item of the corresponding subfield among the subfields Sf1 to Sf7 is referred to. Furthermore, one field (1
f) After the elapse, even when the AC drive signal FR is inverted to the L level, the same operation is repeated in each subfield.

When such an operation is repeatedly performed, the voltage waveform applied to the pixel electrode 118 corresponds to each combination of the gradation data D0, D1, and D2, as shown in FIG.

For example, when the gradation data D0, D1, and D2 of a certain pixel are indicated by (000) during one field (1f) when the AC drive signal FR is at the H level, the data conversion circuit 300 converts the data. Data Ds
Is at the L level in any of the subfields Sf1, Sf2,..., Sf7. Therefore, the H-level signal Voff is applied to the pixel electrode 118 of the pixel over the entire period of the field. That is, the voltage levels applied to the counter electrode 108 and the pixel electrode 118 are the same. Therefore, the one field (1
In the period f), the effective value of the voltage applied to the liquid crystal layer of the pixel becomes zero, so that the transmittance becomes 0% corresponding to the gradation data (000).

Next, when the grayscale data D0, D1, and D2 of a certain pixel are represented by (001) in one field period in which the AC drive signal FR is at the H level, the data Ds includes only the subfield Sf1. It becomes H level, and becomes L level in the other subfields Sf2, Sf3,..., Sf7. Therefore, the pixel electrode 118 of the pixel
, The L-level signal Von is applied only in the application period Sf1b of the subfield Sf1, and the H-level signal Voff is applied in other periods. Here, the ratio of the period of the application period Sf1b in one field (1f) is (V1 /
VH) ² so that the one field (1
In the period f), the effective value of the voltage applied to the liquid crystal layer of the pixel is V1. Therefore, the transmittance of the pixel is
14.3% corresponding to the gradation data (001).

Similarly, when the gradation data D0, D1, and D2 of a certain pixel are represented by (010) in one field period when the AC drive signal FR is at the H level, the converted data Ds is Only the fields Sf1 and Sf2 become H level, and the other Sf3, Sf4,.
7 is at L level. For this reason, the signal Von of the L level is applied to the pixel electrode 118 of the pixel only in the application periods Sf1b and Sf2b of the subfields Sf1 and Sf2.
Is applied, and in other periods, the H-level signal Vof is
f will be applied. Here, the application period Sf1
As described above, the ratio of the accumulation period of Sb2b and Sf2b in one field (1f) is set to (V2 / VH) ² , so that the liquid crystal layer of the pixel in the one field (1f) period The effective value of the voltage applied to
Becomes Therefore, the transmittance of the pixel is determined by the gradation data (0
It becomes 28.6% corresponding to 10).

Hereinafter, the gradation data D0, D1,.
D2 is (011), (100), (101), (11
Also in the case of 0), the same operation causes the effective voltage values applied to the liquid crystal layer of the pixel to be V3, V4, V5, and V6 in the period of the one field (1f). The transmittance is obtained. When the gradation data D0, D1, and D2 are represented by (111),
The data Ds includes subfields Sf1, Sf2,.
.., Sf7, the level becomes H level, so that the application period Sf1 of each subfield is
An L-level signal Von is applied at b, Sf2b,..., Sf7b. Here, the application period Sf1b, S
The ratio of the accumulation period of f2b,..., Sfb7 in one field (1f) is (V7 /
VH) Since it is set to ² or more, the effective voltage value applied to the liquid crystal layer of the pixel becomes V7 or more in the period of the one field (1f). Therefore, the transmittance of the pixel is 100% corresponding to the gradation data (111).

On the other hand, during the period of one field (1f) when the AC drive signal FR is at the L level, the signal Vo is applied to the field where the AC drive signal FR is at the H level.
Since both n and Voff are level-inverted, the magnitude of the effective voltage value applied to the liquid crystal layer of each pixel does not change, but only its polarity is inverted. Therefore, a situation in which a DC component is applied to the liquid crystal layer is avoided, and as a result, the liquid crystal 10
5 can be prevented from deteriorating.

As described above, in the electro-optical device according to the embodiment, one field (1f) is used for the subfield Sf1.
To Sf7, and first, in the writing period Va of each subfield, H-level or L-level data Ds is written into the capacitor 117 of the pixel,
In addition, according to the data Ds written during the application period, the signal Voff or Von is simultaneously applied to the pixel electrode 118 over each pixel. Here, the AC drive signal FR is applied to the counter electrode 108, the signal Voff is the same as the AC drive signal FR, and the signal Von is applied to the counter electrode 10 during the application period.
8 is applied to the liquid crystal layer of each pixel, a difference voltage between the signal Von and the signal Voff or a zero voltage is applied to the liquid crystal layer of each pixel for each application period. As a result, the effective voltage value in one field is controlled, and gradation display is performed.

At this time, the data signal d is applied to the data line 114.
Data Ds supplied as 1, d2,..., Dn
In this embodiment, 2 of only H level or L level
Since a value is sufficient, peripheral circuits such as a drive circuit do not require a circuit for processing an analog signal, such as a high-precision D / A conversion circuit or an operational amplifier. Therefore, the circuit configuration is greatly simplified, and the cost of the entire device can be reduced. Furthermore, since the data Ds supplied to the data line 114 is binary, it is not affected by element characteristics, wiring resistance, and the like. Therefore, display unevenness due to non-uniformity does not occur, so that high-quality and high-definition gradation display can be performed.

Further, the electro-optical device according to the present embodiment immediately outputs the signal Vof according to the written data Ds.
f, the data Vs is once written to the capacitors 117 of all the pixels during the writing period Va, and the signal Voff or Von is applied to the pixel electrode 118 in accordance with the written data Ds without employing the configuration of applying the signal Von to the pixel electrode 118. 118 is applied simultaneously. For this reason, in the present embodiment, the period in which the voltage is applied to the liquid crystal layer can be aligned in each pixel regardless of the order in which the data Ds is written in the writing period Va.
The details are as follows.

Here, as a method for turning on or off a pixel in a unit of a subfield, the following method may be used. That is, the pixel is changed to the state shown in FIG.
And a voltage applied to the data line 114 while the scanning signal Gi is supplied to the scanning line 112 and the transistor 116 is turned on. This is immediately applied to the pixel electrode 118 regardless of the writing period Va. Here, in a subfield in which the pixel 110 is to be turned off, a voltage having the same level as the AC drive signal FR is applied to the data line as a data signal, while in a subfield in which the pixel is to be turned off, the AC drive The signal FR and the voltage of the inverted level are applied to the data line as a data signal. With such a configuration, there is an advantage that the configuration of each pixel can be simplified, but the following problem occurs.

FIG. 8B shows a case where the pixel 110 has the configuration shown in FIG.
6 is a timing chart illustrating a voltage waveform applied to an example 18;

In FIG. 1, pixels connected to the first scanning line counted from the top (hereinafter, referred to as “pixels in the first row”)
And the gradation data of a pixel connected to the m-th scanning line counted from the top (hereinafter, referred to as “m-th row pixel”) are both at the beginning of a certain field, for example (111) ) Is changed to (001). In this case, as shown in FIG. 8B, the AC drive signal applied in the previous field is applied to the pixel electrode 118 of the pixel in the first row until the timing t1 when the scanning signal G1 is supplied. A signal at the same level as FR is applied, but from timing t1, timing t1 when the scanning signal G1 is supplied in the next subfield Sf2
Until 1 ′, a signal of an inverted level from the AC drive signal FR is applied. On the other hand, until the timing tm when the scanning signal Gm is supplied to the pixel electrode 118 of the pixel in the m-th row,
A signal having the same level as the AC drive signal FR is applied. However, from the timing tm to the timing tm ′ at which the scanning signal Gm is supplied in the next subfield Sf2, a signal having an inverted level from the AC drive signal FR. Is applied. Therefore, the pixels in the first row and the pixels in the m-th row are:
As a result, the effective voltage value applied to the liquid crystal layer during the one field period is the same.

However, it is assumed that both the gradation data of the pixels in the first row and the gradation data of the pixels in the m-th row are changed from (000) to (001) at the beginning of a certain field. Assuming this, the following inconveniences occur. That is, in this case, as shown in FIG. 8B, the alternating current is applied to the pixel electrode 118 of the pixel in the first row until the timing t1 ′ when the scanning signal G1 is supplied in the next subfield Sf2. The drive signal FR and the signal of the inverted level are applied, and the AC drive signal FR and the signal of the inverted level are applied to the pixel electrode 118 of the pixel in the m-th row until timing tm ′. The effective value of the voltage applied to the liquid crystal layer during the one field period differs between the pixel in the m-th row and the pixel in the m-th row. For this reason,
Although both pixels are originally of the same gradation, there is a difference in their densities. Although not shown, this inconvenience occurs even when the gradation data of the pixels in the first row and the gradation data of the pixels in the m-th row are both fixed at (000). I have. However, as shown in FIG. 4 (a), the transmittance is maintained at 0% unless a certain effective voltage value is applied, so that there is no substantial difference in density.

On the other hand, in the electro-optical device according to the present embodiment, as described above, the pixel electrode 118 is
In the writing period Va, the same signal as the AC driving signal FR is applied. In the immediately subsequent application period, a signal having the same level as the AC driving signal FR in accordance with the data Ds written in the capacitor 117 in the writing period. Alternatively, the configuration is such that signals of the inversion level are applied all at once. For this reason,
As shown in FIGS. 9A and 9B, the gradation data Ds
Even if is changed, in the pixels having the same gradation, the period in which the difference voltage is applied to the liquid crystal layer is uniform,
As a result of eliminating the above-mentioned inconvenience, uniform gradation display can be achieved.

In the above-described embodiment, the level of the AC drive signal FR is inverted at a cycle of one field. However, the present invention is not limited to this.
The configuration may be such that the level is inverted at a cycle longer than the field.

<Second Driving Method> Next, a second driving method of the electro-optical device according to the present embodiment will be described. Also in this driving method, one field is divided into a plurality of subfields Sf1, Sf2,..., Sf7, and in each of these subfields, the pixel electrode 1 of each pixel is
The point that the signal Von or Voff is applied to 18 is the same as in the first driving method. However, in the first driving method, the data Ds is written to the memories of all the pixels during the writing period Va in each subfield,
Although the signal Von or Voff is applied to the pixel electrodes of all the pixels at the same time after the elapse of the writing period Va, in the present driving method, when the data Ds is written to the memory of each pixel, Regardless of whether the writing period Va has elapsed, one of the signals Von and Voff is immediately applied to the pixel electrode 118 of the pixel. Specifically, unlike the signal Von in the first driving method, the signal Von used in the present driving method is different from the signal Von in the writing period or the application period in the level of the AC driving signal FR. It is a signal that changes in level opposite to the change (see FIG. 10). That is, in the field where the AC drive signal FR is at the H level, the signal Von is at the L level, while in the field where the AC drive signal FR is at the L level, the signal Von is at the H level. in this way,
Since the signal Von in the present embodiment has an inverted level of the AC drive signal FR regardless of the writing period and the application period, the H level data Ds is written to the memory of each pixel 110 and the pixel 110 at the same time. The signal Von is applied to the pixel electrode 118, and as a result, the pixel 110 is immediately turned on.

Further, when such a driving method is employed, the time length of each subfield is set as follows. That is, in the first driving method, the application period Sf1b in the subfield Sf1 is set to one field (1
relative to f) (V1 / VH) was set to be ² times the length, in this driving method, comprising the sub-fields Sf1 to one field (1f) and (V1 / VH) ² time length Set as follows. As a result, gradation data (001) is given to a certain pixel, and one field (1
f) In the subfield Sf1 of the f), the voltage VH is applied to the liquid crystal layer of the pixel while the voltage VL (= 0) is applied in the other period (subfields Sf2 to Sf7). Since the effective value of the voltage applied to the liquid crystal layer during the period is V1, the transmittance of the pixel is 14.3%.

Similarly, in the first driving method,
The application period Sf2b in the subfield Sf2 is set to (V2 / VH) ² − (V1 / V) for one field (1f).
Although the time length is set to H) ² , in the present driving method, the subfield Sf2 is set to have a time length of (V2 / VH) ² − (V1 / VH) ² for one field (1f). Set to. Other subfields Sf3, Sf
4, Sf5 and Sf6. That is, the subfield Sf3 is set to have a time length of (V3 / VH) ^2- (V2 / VH) ² for one field (1f), and the subfield Sf4 is set to ( (V4 / VH) ^2- (V3 / VH) ² , and the subfield Sf5 is set to (V5 / VH) ^2- (V
4 / VH) ² , and the subfield Sf6 is set to have a time length of (V6 / VH) ² − (V5 / VH) ² for one field (1f). Is done. As for the subfield Sf7, finally, the subfields Sf1 to Sf6 from one field
Is set to the period excluding. However, as mentioned above,
The accumulation period of each of the subfields Sf1 to Sf7 needs to be secured for one field (1f) longer than the time length of (V7 / VH) ² . However, even if the accumulation period of the subfields Sf1 to Sf7 is longer than the time length of (V7 / VH) ² for one field,
That is, the effective voltage value applied to the liquid crystal layer is as shown in FIG.
Even when the value exceeds V7, the transmittance is 100% because of saturation. The above is the time length of each subfield in the present driving method.

In the present driving method, similarly to the first driving method described with reference to FIG. 6, the scanning signal Gi is sequentially and exclusively transmitted from the scanning line driving circuit 130 to each scanning line 112. While being supplied, the data line driving circuit 140
, Dn are supplied to each data line 114 at the same time. As a result, in the first period (writing period Va) of each subfield, data Ds instructing ON or OFF of the pixel is written into the capacitors 117 of all the pixels 110, respectively. As a result of this operation, the voltage waveform applied to the pixel electrode 118 of each pixel in the present driving method becomes the gradation data D0, D0 as shown in FIG.
1, corresponding to each combination of D2. In addition,
FIG. 10 illustrates the waveform of the voltage applied to the pixel connected to the first scanning line 112 counted from the top in FIG.

For example, during the period of one field (1f) when the AC drive signal FR is at the H level, when the gradation data D0, D1, D2 of a certain pixel is indicated by (000), the data is converted by the data conversion circuit 300. Data Ds
Is at the L level in any of the subfields Sf1, Sf2,..., Sf7. Therefore, the H-level signal Voff is applied to the pixel electrode 118 of the pixel over the entire period of the field. That is, the voltage levels applied to the counter electrode 108 and the pixel electrode 118 are the same. Therefore, the one field (1
In the period f), the effective value of the voltage applied to the liquid crystal layer of the pixel becomes zero, so that the transmittance becomes 0% corresponding to the gradation data (000).

Next, in the period of one field (1f) when the AC drive signal FR is at the H level, when the gradation data D0, D1, D2 of a certain pixel is indicated by (001), the data Ds is Only the field Sf1 becomes H level, and the other subfields Sf2, Sf3,.
At Sf7, the level becomes L level. For this reason, the pixel electrode 118 of the pixel has L level only in the subfield Sf1.
Level signal Von is applied, and in other periods, H
The level signal Voff is applied. However, unlike the first driving method, the signal Von in the present driving method is a signal having an inversion level of the AC driving signal FR irrespective of whether or not it is during the writing period. Therefore, when H-level data Ds is written to the capacitor 117 of the pixel in the subfield Sf1,
The signal Von of the inverted level with respect to the H level AC drive signal FR is applied to the pixel electrode 118 of the pixel without waiting for the writing period Va to elapse. Here, the ratio of the period of the subfield Sf1 in one field (1f) in the present driving method is set to (V1 / VH) ² as described above, so that in the period of the one field (1f), The effective value of the voltage applied to the liquid crystal layer of the pixel is V1. Therefore, the transmittance of the pixel is 14.3 corresponding to the gradation data (001).
%.

Similarly, in the period of one field (1f) when the AC drive signal FR is at the H level, when the gradation data D0, D1, D2 of a certain pixel is indicated by (010), the data Ds is Only the fields Sf1 and Sf2 become H level, and the other subfields Sf3, Sf4,
.., Sf7 is at L level. For this reason, the subfields Sf1 and Sf
2, the L-level signal Von is applied, and the H-level signal Voff is applied in other periods. Also in this case, in the subfields Sf1 and Sf2, H
Immediately after the level data Ds is written, a signal Von of an inverted level with respect to the AC drive signal FR of the H level is applied to the pixel electrode 118 of the pixel. Here, the ratio of the accumulation period of the subfields Sf1 and Sf2 in one field (1f) is set to (V2 / VH) ² as described above.
In the period of the field (1f), the effective voltage value applied to the liquid crystal layer of the pixel is V2. Therefore, the transmittance of the pixel is set at 28.degree. Corresponding to the gradation data (010).
6%.

Hereinafter, the gradation data D0, D1,.
D2 is (011), (100), (101), (11
0), the effective operation of the voltage applied to the liquid crystal layer of the pixel in the period of the one field (1f) is V3, V4, V5, and V6 by the same operation. The transmittance is obtained. When the gradation data D0, D1, and D2 are represented by (111),
The data Ds includes subfields Sf1, Sf2,.
, Sf7 is at H level, so that the H level signal Von is applied to the pixel electrode 118 of the pixel over one field. Here, the accumulation period of the subfields Sf1 to Sf7 is one field (1
The ratio occupied in f) is, as described above, (V7 / V
H) Since it is set to ² or more, the effective value of the voltage applied to the liquid crystal layer of the pixel becomes V7 or more in the period of the one field (1f). Therefore, the transmittance of the pixel is 100% corresponding to the gradation data (111).

On the other hand, during the period of one field (1f) when the AC drive signal FR is at the L level, the signal Vo is applied to the field where the AC drive signal FR is at the H level.
Since n and Voff are inverted in level, the magnitude of the effective voltage value applied to the liquid crystal layer of each pixel does not change.
Only its polarity is reversed. Therefore, as a result of avoiding a situation in which a DC component is applied to the liquid crystal layer, deterioration of the liquid crystal 105 can be prevented.

According to this driving method, as in the case of using the first driving method, it is possible to reduce the cost of the entire apparatus and to realize high-quality and high-definition gradation display. Furthermore, according to the present driving method, the voltage applied to the liquid crystal layer of the pixel can be made uniform over all pixels irrespective of the position of each pixel by a simple configuration as compared with the first driving method. There is an advantage that can be. The details are as follows.

FIG. 11 is a timing chart showing the state of the voltage applied to each pixel in the present embodiment.

Hereinafter, the pixels connected to the first scanning line counted from the top in FIG. 1 (hereinafter referred to as “pixels of the first row”)
The following description will be given by taking as an example a case where pixels connected to the m-th scanning line counted from the top (hereinafter, referred to as “pixels in the m-th row”) are displayed at the same gradation. Specifically, FIG.
As shown in the figure, when the gradation data (001) is given in the field f1, that is, in the subfield Sf1, the H level data Ds is written into the memory of the pixel, while the subfields Sf2 and Sf are written.
3,..., Sf7 exemplify the case where the L level data Ds is written to the memory of the pixel.
In the field f2, the gradation data (010)
Is provided, that is, in the subfields Sf1 and Sf2, the H-level data Ds is written into the memory of the pixel, while the subfields Sf3 and Sf2 are written.
f4,..., Sf7, L level data Ds
Is written in the memory of each pixel.

As shown in FIG. 11A, the L-level data Ds written in the immediately preceding field is held in the memory of the pixels in the first row until time t11. Then, the time t11 of the subfield Sf1
The H level data Ds is written into the memory of the pixel at and the data is held until the L level data Ds is newly written at time t12 of the next subfield Sf2. The L-level data Ds written to the memory of the pixel at time t12 is stored in the next field f2.
At time t21, the data Ds is held until the H-level data Ds is newly written.

On the other hand, as shown in FIG. 11B, the memory of the pixels in the m-th row is stored in the writing period Va from the time t11.
Until the time t11 ′, which has elapsed, L-level data Ds written in the immediately preceding field is held. Then, the time t1 of the subfield Sf1
1 ', the H level data Ds is stored in the memory of the pixel.
At the time t1 of the next subfield Sf2.
At 2 ', the data is held until L-level data Ds is newly written. The time t12 'is also a time when the writing period Va has elapsed from the time t12. Time t12 '
The L-level data Ds written in the memory of the pixel is held until the H-level data Ds is newly written at time t21 ′ of the next field f2.

Next, as a result of writing the data Ds into the memory of each pixel in this way, the pixel electrode 11
Consider the voltage applied to 8.

First, in the field f1, the memory of the pixel in the first row is set to H for a period from time t11 to time t12.
Since the level data Ds is held, during this period, as shown in FIG. 11C, the pixel electrode 118 of the pixel receives the AC drive signal FR applied to the counter electrode 108. L level signal V which is the inverted level
on is applied. On the other hand, during the period from time t12 to time t21, the memory of the pixels in the first row stores the L level data D
Since s is held, an H-level signal Voff having the same level as the AC drive signal FR applied to the counter electrode 108 is applied to the pixel electrode 118 of the pixel. Eventually, as shown in FIG.
Within the data Ds written in the memory of the pixel
Accordingly, the pixel is in an on state during a period from time t11 to t12, while the pixel is in an off state during a period from time t12 to t21.

On the other hand, the memory of the pixel in the m-th row contains the time t
H level data Ds during a period from 11 ′ to t12 ′
Are held in this period, FIG.
As shown in (e) and (f), an L-level signal Von is applied to the pixel electrode 118 of the pixel, and the pixel is turned on. On the other hand, at time t1 when L-level data Ds is written to the memory of the pixel.
In the period from 2 ′ to t21 ′, during the period from time t12 ′ to t21, the voltage applied to the pixel electrode 118 is the H-level signal Voff, and in this period, the AC drive signal FR is also H Because of the level, the pixel is turned off. Next, from time t21 to t2
In the period up to 1 ′, the AC drive signal FR switches to the L level, but the signal Voff applied to the pixel electrode 118 of the pixel also switches to the L level. Becomes

As described above, the period in which the pixels in the first row are in the ON state and the period in which the pixels in the m-th row are in the ON state are shifted by the writing time Va. Are equal. Similarly, the period in which the pixels in the first row are in the off state and the period in which the pixels in the mth row are in the off state are periods shifted by the writing period Va, but have the same time length. . Therefore, the effective voltage value applied to the pixels in the first row is equal to the effective voltage value applied to the pixels in the mth row.

Similarly, in the field f2, the pixels in the first row are in the on state during the period from time t21 to t23, and are in the off state during the period from time t23 to t31, while the pixel in the mth row is at the time t21. It is on during the period from '23 to t23 ', and is off during the period from time t23' to t31 '. As is clear from FIG.
The time length of the period in which the pixels in the first row are in the on state is equal to the time length of the period in which the pixels in the m-th row are in the on state, and the time length of the period in which the pixels in the first row are in the off state is equal to m. The length of time during which the pixels in the row are in the off state is equal to the length of time. Therefore,
The effective voltage value applied to the pixels in the first row is equal to the effective voltage value applied to the pixels in the m-th row.

As described above, in the present driving method, the signal Von that repeats the level inversion irrespective of the data Ds based on the data Ds written in the memory of the pixel.
And Voff are selected and applied to the pixel electrode 118. Therefore, regardless of the timing of writing the data Ds to the memory, the pixel 110 is turned on while the H level data Ds is written to the memory of the pixel 110, while the pixel 11
The pixel 110 is in an off state during a period in which the L-level data Ds is written to the 0 memory. As a result, when the pixels in the first row and the pixels in the m-th row are displayed at the same gradation, the period in which the pixels in the m-th row are in the on state is compared with the period in which the pixels in the first row are in the on state. Thus, only the writing period Va is delayed, and the lengths of the periods are equal. That is, the effective voltage value applied to the pixel does not change according to the position of the pixel, that is, the writing timing of the data Ds.

In the first driving method, the signal Von is supplied during the writing period Va.
Although it is necessary to set the same voltage level as R (or the signal Voff) and to set the inverted level for these signals during the application period, in the present driving method,
Regarding the signal Von, the AC drive signal FR (or the signal Voff) regardless of the writing period or the application period.
Since a signal having an inversion level can be used, there is an advantage that the configuration can be simplified as compared with the first driving method.

In the second driving method, as shown in FIG. 11, the cycle of the AC drive signal FR and the like are made equal to the field cycle. However,
As is clear from the above, the AC drive signal FR, the signal Von, and the signal Voff make a level transition at the same timing, and the signal Von has an inverted level with the AC drive signal FR, and the signal Voff is As long as the AC drive signal FR is at the same level, the cycle of each of these signals may be a cycle unrelated to the field or subfield. FIG. 12 is a timing chart illustrating a case where the cycle of the AC drive signal FR and the like is shorter than one field. Note that FIG. 12 illustrates a case where the cycle of the AC drive signal FR and the like is shorter than that shown in FIG.
Are the same as those shown in FIG.

As shown in FIG. 12, the AC drive signal FR
Even when the cycle of the above is shorter than one field, the period in which the pixels in the first row are in the ON state is a period in which the H-level data Ds is written in the memory of the pixels in the first row. The period in which the pixels in the m-th row are in the ON state is a period in which the H-level data Ds is written in the memory of the pixels in the m-th row. Specifically, the AC drive signal FR
Is shorter than that shown in FIG. 11, the period during which the pixels in the first row are in the ON state in the field f1 is the period from time t11 to time t12, and
The period when the pixels in the row are in the ON state is from time t11 ′ to t1.
The period is 2 '. These periods are periods shifted by the writing period Va, and since the time lengths are equal, the effective voltage value applied to the pixels in the first row and the effective voltage value applied to the pixels in the m-th row Is uniform.

As described above, according to the present embodiment, the period of the AC drive signal FR or the like can be set independently of the time length of the field or subfield. It is also possible to set the cycle to a cycle that minimizes flicker.

<Applications of Each Driving Method> (1) First Application (Random Writing) In each of the above-described driving methods, the scanning signal is selected by selecting the scanning lines 112 one by one. In addition, the data Ds is written into the memory via the corresponding data line 114 to the pixel located on the scanning line via the corresponding data line 114, that is, a sequential write configuration. However, the present invention is not limited to this, and may have a configuration in which an address decoder is used to specify a pixel using a row address and a column address to write data Ds, that is, a random write configuration, similarly to a normal DRAM. . That is, in the above-described embodiment, the scanning line 112 is a word line and the data line 1 is
Using the bit line 14 as a bit line, writing similar to that of a normal DRAM may be performed.

Here, according to each of the above-described driving methods, when a display with a transmittance of 100% or 0% is performed in one pixel, the data Ds corresponding to the pixel is H
Since the data Ds is fixed to the level or the L level, once the data Ds is written, there is no need to rewrite the data Ds thereafter. Even in the case where halftone display is performed in a certain pixel, the data Ds corresponding to the pixel is reset to the H level at the beginning of one field, and thereafter, in a subfield corresponding to the halftone. Since it is only set to L level, the data Ds is changed only twice in one field. That is, in the above-described embodiment, the frequency of rewriting the data Ds for one pixel is not so high.

Therefore, if a configuration of random write using an address decoder and a configuration in which data Ds is rewritten only for necessary pixels can be used, the rewriting time can be shortened. The frequency of the clock signal can be reduced with the increase in power consumption, so that power consumption can be reduced.

On the other hand, in a pixel that cannot be rewritten,
Transistors Ta1, Tb1, and Tb as constituent elements
2 does not switch. For this reason, charge / discharge caused by rewriting, for example, charge / discharge due to a capacitive load of these elements or a load of wiring capacitance does not occur, so that the power consumption can be suppressed also in this regard.

However, in order to avoid rewriting the data Ds for a long period of time, the memory needs to be rewritten in FIG.
9. It is necessary to configure the SRAM as shown in FIG. 22 or FIG. Note that even if the data Ds is not rewritten, the signals Von and Voff and the AC drive signal FR
Since the level is inverted every field, no DC component is applied to the liquid crystal layer.

(2) Second Application In the first and second driving methods described above, data Ds is written to the capacitor 117 during the writing period Va of each subfield. When the period is constant, the writing period Va acts in a direction to shorten the application period in which the voltage contributing to the gradation display is applied to the liquid crystal layer. Therefore, the shorter the writing period, the better. On the other hand, in the above-described embodiment, eight gradations are displayed.
In order to increase the gray scale display frequency such as 6 gray scale display, 64 gray scale display,. It needs to be completed.

However, the driving circuit, particularly the X shift register 1410 in the data line driving circuit 140,
Actually, since it operates at the operating frequency near the upper limit, the gradation display frequency cannot be increased without any change. Therefore, an application form in which this point is improved will be described.

FIG. 13A is a block diagram showing the configuration of a data line drive circuit in an electro-optical device according to this application. In this figure, the X shift register 141
2 is similar to X shift register 1410 shown in FIG. 3 in that latch pulse LP is transferred according to clock signal CLX, but differs from X shift register 1410 in that the number of stages is half. ing. That is, assuming an integer p satisfying n = 2p,
The X shift register 1412 outputs the latch signals S1, S2,
.., Sp are sequentially output.

In this application, the data is the data Ds1 to the odd-numbered data line 114 counted from the left.
And data Ds2 to the even-numbered data line 114
Supplied in separate systems. Further, the latch circuit 14
In No. 22, a pair of latching the data Ds1 corresponding to the odd-numbered data line 114 and a pair latching the data Ds2 corresponding to the subsequent even-numbered data line 114 form the same latch. The configuration is such that the latch is performed at the same time as the falling of the signal.

Therefore, such a data line driving circuit 14
According to FIG. 14, data Ds1 and Ds2 for two pixels are simultaneously latched by the same latch signals S1, S2,..., Sp as shown in FIG. The required horizontal scanning period can be reduced by half while maintaining the same as the embodiment. Further, the number of stages of the unit circuits constituting the X shift register 1412 is reduced from “n” corresponding to the total number of the data lines 114 to “p” which is half thereof. Therefore, the configuration of the X shift register 1412 can be simplified as compared with the X shift register 1410 (see FIG. 3).

On the other hand, the fact that the number of unit circuits constituting the X shift register 1412 is reduced to half means that if the required horizontal scanning period is the same, the clock signal CL is required.
This means that X can be reduced by half. Therefore, if the horizontal scanning period is the same, the power consumed due to the operating frequency can be suppressed.

In this application, the first latch circuit 1 that performs simultaneous latching by a latch signal is used.
Although the number of 422 is “2”, it is needless to say that it may be “3” or more. In this case, the data is supplied after being divided into systems corresponding to the number, and the number of stages of the X shift register 1412 can be reduced to the number obtained by dividing the number of data lines by the number.

(3) Third Application In the above embodiment, the dot sequential driving in which the data signal is written in a dot sequential manner to the pixels of one row selected in one horizontal scanning period is adopted. The invention is not limited to this, and line-sequential driving in which a data signal is simultaneously written to one row of pixels in one horizontal scanning period can be employed. FIG. 13B illustrates a data line driving circuit 14 according to the present modification.
2 is a block diagram showing a configuration of FIG.

The data line drive circuit 142 sequentially latches n data Ds corresponding to the number of the data lines 114 in a certain horizontal scanning period, and then stores the n data Ds in the next horizontal scanning period. The data signals d1, d2, d3,.
, Dn are supplied all at once. More specifically, as shown in FIG. 13B, the data line driving circuit 142 includes an X shift register 1410, a first latch circuit 1430, and a second latch circuit 1431. The X shift register 1410 is similar to that in the above embodiment.

The first latch circuit 1430 sequentially latches the data Ds at the falling edges of the latch signals S1, S2, S3,..., Sn. The second latch circuit 1431 simultaneously latches each of the data Ds latched by the first latch circuit 1430 at the falling edge of the latch pulse LP, and simultaneously supplies the data signals d1, d2, d3,. ., Dn.

Here, an outline of the operation of the data line driving circuit 142 during a certain horizontal scanning period will be described. First, one horizontal scanning period (1) in which a certain scanning signal Gi is output.
In (H), the second latch circuit 1431 simultaneously sends the data signals d1, d2, d3,... To each of the n data lines 114 in accordance with the latch pulse LP supplied at the rising timing of the scanning signal Gi.・, Dn
Is output. These data signals are written to the capacitor 117 via the transistor Ta1 of each pixel which is turned on by the supply of the scanning signal Gi. On the other hand, in parallel with this write operation, the first latch circuit 143
0 is the latch signal S1, S2, output from the X shift register 1410 by the transfer of the latch pulse LP.
According to S3,..., Sn, the (i + 1) th scanning line 1
In this case, data is sequentially latched for pixels corresponding to one row corresponding to No. 12.

By performing such an operation in parallel for each horizontal scanning period, line-sequential driving is realized.
In this modification, as in Modification 2, the number of latch circuits 1422 that simultaneously perform a latch operation in response to a latch signal may be set to “2” or more.

(3) Fourth Application In the first and second driving methods described above, the writing of the data Ds into the capacitor 117 is completed in the writing period Va of each subfield. (E.g., application periods Sf1b, Sf2b,..., Sf7b in the first driving method) after elapse of the scanning period Va.
Now, the scanning line driving circuit 130 and the data line driving circuit 1
There is no need to operate 40.

On the other hand, the frequency of the clock signal CLX supplied to the driving circuit in the above embodiment, particularly, the data line driving circuit 140 is very high. In general, a shift register is provided with an extremely large number of clocked inverters (or transmission gates) for inputting a clock signal at a gate. Therefore, when viewed from the timing signal generation circuit 200 which is a supply source of the clock signal CLX, the X shift register 1410 Is a capacitive load.

Accordingly, the period after the above-described writing period Va has elapsed (for example, the application periods Sf1b, Sf2b,..., Sf
7b), in the configuration for supplying the clock signal CLX, power is wasted by the capacitive load,
This leads to an increase in power consumption. Therefore, an application form in which this point is improved will be described.

In this application, the clock signal C
The clock signal supply control circuit 400 shown in FIG. 15 is interposed between LX and the X shift register 1410 from the timing signal generation circuit 200. Here, the clock signal supply control circuit 400
An RS flip-flop 402 and an AND circuit 404 are provided. Among them, RS flip-flop 402
Is for inputting the start pulse DY to the set input terminal S and inputting the scanning signal Gm to the reset input terminal R. Further, the AND circuit 404 includes a clock signal CLX supplied from the timing signal generation circuit 200,
An AND signal with the signal Enb output from the output terminal Q of the RS flip-flop 402 is obtained and supplied as a clock signal CLX to the X shift register 1410 in the data line driving circuit 140.

Here, the clock signal supply control circuit 400
, When the start pulse DY is supplied at the beginning of a certain subfield, the RS flip-flop 40
Since 2 is set, the signal Enb output from the output terminal Q goes high as shown in FIG.
Therefore, the AND circuit 404 is opened, and the supply of the clock signal CLX to the X shift register 1410 is started. Then, in the data line driving circuit 140, the latch circuit 1420 performs point-sequential latching of data by the latch pulse LP supplied immediately thereafter.

On the other hand, after the supply of the clock signal CLX is started by the start pulse DY, the last (m-th scanning line 112 from the top) in the subfield is started.
Is supplied, the RS flip-flop 402 is reset, and the signal Enb output from the output terminal Q becomes L as shown in FIG.
Level. As a result, the AND circuit 404 closes, so that the clock signal CLX to the X shift register 1410 is
Supply is shut off. Here, before the scan signal Gm is supplied, the data of one row of pixels corresponding to the intersection with the m-th scan line 112 should have been latched by the latch circuit 1420. There is no problem even if the clock signal CLX is cut off until the start of the field.

Such a clock signal supply control circuit 40
When 0 is provided, X is used only when the clock signal CLX is required.
Since the power is supplied to the shift register 1410, the power consumed by the capacitive load can be suppressed accordingly. A similar clock signal supply control circuit may be provided for the Y-side clock signal CLY, but the clock signal CLY has an overwhelmingly lower frequency than the X-side clock signal CLX. Therefore, the power consumed by the capacitive load on the Y side is less problematic than on the X side.

<Configuration of Other Pixels> In each of the above embodiments, the configuration of the pixel 110 is the configuration shown in FIG.
In this configuration, strictly speaking, the power supply voltage is
There is a problem that the setting must be made in consideration of the characteristics of 1, Tb1, and Tb2. That is, the scanning signal supplied to the scanning line 112, the data Ds supplied to the data line 114, and the H level and L level of the signals Von and Voff
When the levels are respectively set to the higher voltage VDD and the lower voltage VSS of the power supply voltage, the H level voltage applied to the pixel electrode 118 is set to VH, and the L level voltage is set to VL
In order to achieve the above, the voltage VDD and the voltage VSS must be set in consideration of the threshold voltages of the transistors Ta1, Tb1, and Tb2. In detail, FIG.
, The holding voltage of the capacitor 117 needs to be set to be offset with respect to the voltage VH in consideration of the threshold voltage of the transistor Tb1 or Tb2. Ta
It is necessary to take the threshold voltage of 1 into consideration and set the offset with respect to the holding voltage. After all, the higher voltage VD
D must be set in consideration of the threshold voltages of the transistors Ta1, Tb1, and Tb2. On the other hand, the voltage VSS needs to be set offset from the voltage VL in consideration of the threshold voltage of the transistor Tb1 or Tb2.

First, as shown in FIG. 17, if the transistor Ta1 has a structure in which a P-channel transistor and an N-channel transistor are complementarily combined, the offset voltage in the transistor Ta1 can be canceled. it can. Therefore, FIG.
As shown in FIG. 5 (b), only the threshold voltages of the transistors Tb1 and Tb2 need to be considered for the voltages VH and VL. However, in this configuration, it is necessary to supply mutually exclusive levels as scanning signals, so that 1
The scanning lines 112a and 112b of the pixels 110 in the row
You need a book.

In FIG. 2 or FIG. 17, the memory for storing data Ds has a DRAM configuration.
As shown in FIG. 8, the transistors Ta1 and Ta2 are used as transfer gates, and
3, an inverter composed of Ta4 and a transistor Ta
5 and Ta6, the data D is applied to a flip-flop having one output as the other input.
An SRAM configuration for writing s may be used. According to such a configuration, the data Ds written to the flip-flop is fixed (self-held) to the power supply voltage (VDD, VSS), so that the threshold voltage of the transistor Ta1 (Ta2) need not be considered. I'm done. Therefore, as shown in FIG. 25B, only the threshold voltages of the transistors Tb1 and Tb2 need to be considered for the voltages VH and VL. Further, since it is not necessary to consider the leakage in the capacitor 117 in the DRAM configuration, the operation margin can be increased. However, in this SRAM configuration, it is necessary to supply mutually exclusive levels as data Ds.
14a and 114b are required.

Further, since one SRAM requires six transistors Ta1 to Ta6, the configuration is complicated. In order to eliminate the complication of the configuration, FIG.
As shown in (1), a configuration in which the transistors Ta3 and Ta5 are replaced with load resistors Ta7 and Ta8, respectively, can be considered.

On the other hand, a configuration as shown in FIG. 20 can be considered so as not to consider the threshold voltages of the transistors Tb1 and Tb2. That is, if the transistors Tb1 and Tb2 are configured to complementarily combine a P-channel transistor and an N-channel transistor, the offset voltage in the transistors Tb1 and Tb2 can be canceled. Therefore, as shown in FIG.
As for the voltage VL, only the threshold voltage of the transistor Ta1 needs to be considered, and the lower voltage VSS of the power supply can be used as the voltage VL. However, in this configuration, it is necessary to supply mutually exclusive levels as the data Ds. Therefore, two data lines 114a and 114b are required for one column of pixels 110, and capacitors 117a and 117b are provided. , A configuration for holding exclusive-level data Ds is required.

Next, as shown in FIG. 21, a configuration is conceivable in which the transistors Ta1 and Ta2 are complementary and the transistors Tb1 and Tb2 are complementary.
According to this configuration, each of the transistors Ta1, Ta2, T
Since the offset voltages at b1 and Tb2 can be canceled, as shown in FIG. 25 (d), the voltages VH and VL are respectively set to the higher voltage VDD of the power supply.
In addition, the lower voltage VSS can be used as it is.

As shown in FIG. 22, the memory has an SRAM configuration, and transistors Tb1 and Tb1 have the same structure.
A configuration in which b2 is the complementary side is conceivable. According to this configuration, the data Ds written to the flip-flop of the SRAM is the higher voltage VDD or the lower voltage VS of the power supply.
S, the transistor Ta
1 and the threshold voltages of the transistors Tb1 and Tb2 because they are complementary, so that the voltages VH and VL are set as shown in FIG. , The higher voltage VDD of the power supply, respectively.
In addition, the lower voltage VSS can be used as it is. At this time, as shown in FIG.
By replacing a3 and Ta5 with load resistors Ta7 and Ta8, respectively, it is possible to avoid complication of the configuration.

The specific configuration of the load resistors Ta7 and Ta8 shown in FIG. 19 and FIG.
As shown in FIG. 3A, an enhancement type transistor, a depletion type transistor as shown in FIG. 3B, and poly (polycrystalline) silicon as a resistor as shown in FIG. Shape and the like.

<Overall Structure of Liquid Crystal Device> Next, with respect to the structure of the electro-optical device according to the above-described embodiments and applied embodiments,
This will be described with reference to FIGS. 26 and 27. Here, FIG.
6 is a plan view showing the configuration of the electro-optical device 100,
FIG. 27 is a sectional view taken along line AA ′ in FIG.

As shown in these figures, the electro-optical device 100 includes an element substrate 101 on which a pixel electrode 118 and the like are formed, and a counter substrate 1 on which a counter electrode 108 and the like are formed.
02 are bonded to each other with a certain gap therebetween by a sealant 104, and a liquid crystal 105 as an electro-optical material is sandwiched in this gap. Actually, the sealing material 104 has a cutout portion, and after the liquid crystal 105 is sealed through the cutout portion, it is sealed with a sealing material, but is omitted in these drawings.

Here, the element substrate 101 is opaque because it is a semiconductor substrate. For this reason, the pixel electrode 118
The electro-optical device 100 formed of a reflective metal such as aluminum is used as a reflective type.
On the other hand, the counter substrate 102 is transparent because it is made of glass or the like.

On the element substrate 101, a light-shielding film 106 is provided inside the sealant 104 and outside the display area 101a. In the region where the light-shielding film 106 is formed, the scanning line driving circuit 130 is formed in the region 130a, and the data line driving circuit 140 is formed in the region 140a. That is, the light shielding film 10
Numeral 6 prevents light from entering a drive circuit formed in this region. This light-shielding film 106 has a counter electrode 10
8 together with the AC drive signal FR. For this reason, in the region where the light-shielding film 106 is formed, the voltage applied to the liquid crystal layer becomes substantially zero, and the display state is the same as the state where no voltage is applied to the liquid crystal layer.

In the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line driving circuit 140 is formed and separated from the sealing material 104 by external control. It is configured to input signals and power.

On the other hand, the opposite electrode 108 of the opposite substrate 102
Is electrically connected to the light-shielding film 106 and the connection terminals on the element substrate 101 by a conductive material (not shown) provided at least at one of four corners of the substrate bonding portion. That is, the AC drive signal FR
Are connected to the light-shielding film 106 via connection terminals provided on the element substrate 101 and further to the counter electrode 108 via a conductive material.
, Respectively.

In addition, depending on the application of the electro-optical device 100, for example, first, in the case of a direct-view type, first, color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like are provided on the counter substrate 102. Second, a light-shielding film (black matrix) made of, for example, a metal material or a resin is provided. In the case of color light modulation,
For example, when used as a light valve of a projector described later, no color filter is formed. In the case of a direct-view type, a front light for irradiating the electro-optical device 100 with light from the counter substrate 102 side is provided as necessary.
In addition, an alignment film (not shown) rubbed in a predetermined direction or the like is provided on each of the electrode forming surfaces of the element substrate 101 and the counter substrate 102 to regulate the alignment direction of the liquid crystal molecules in the state where no voltage is applied. On the other hand, on the side of the counter substrate 102, a polarizer (not shown) corresponding to the alignment direction is provided.
Is provided. However, if a polymer-dispersed liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 105,
As a result of eliminating the need for the above-described alignment film and polarizer, the light use efficiency is increased, which is advantageous in terms of high luminance and low power consumption.

<Others> In the embodiment, the element substrate 101 constituting the electro-optical device is used as a semiconductor substrate, and the transistors of the pixels 110, the components of the driving circuit, and the like are formed by MOS FETs. Although the configuration is adopted, the present invention is not limited to this. For example, SOI (Si
A silicon single crystal film may be formed on an element substrate 101 made of an insulating substrate such as sapphire by applying the technique of “icon on insulator”, and various elements may be formed here. Further, for example, the element substrate 101 may be a transparent insulating substrate such as glass or quartz, and a semiconductor thin film may be deposited thereon to form a TFT (Thin Film Transistor). When a transparent substrate is used as the element substrate 101, the electro-optical device 100 can be used as a transmission type.

Further, as an electro-optical material, in addition to liquid crystal, the present invention can be applied to a device that uses electroluminescence, fluorescence, or the like to perform display by the electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described configuration, and particularly to all electro-optical devices that perform gradation display using pixels that perform on- or off-state binary display. It is.

<Electronic Equipment> Next, some examples in which the above-described liquid crystal device is used for specific electronic equipment will be described.

<Part 1: Projector> First, a projector using the electro-optical device according to the embodiment as a light valve will be described. FIG. 28 is a plan view showing the configuration of this projector. As shown in this figure,
Inside the projector 1100, a polarized light illumination device 1110 is provided.
Are arranged along the system optical axis PL. In the polarized light illuminating device 1110, the light emitted from the lamp 1112 becomes a substantially parallel light beam due to reflection by the reflector 1114, and enters the first integrator lens 1120. As a result, the light emitted from the lamp 1112 is split into a plurality of intermediate light beams. This split intermediate beam is
The polarization conversion element 1130 having the second integrator lens on the light incident side converts the light into one type of polarized light beam (s-polarized light beam) having a substantially uniform polarization direction, and emits it from the polarized light illuminating device 1110.

Now, the s-polarized light beam emitted from the polarized light illuminating device 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarizing beam splitter 1140. Of this reflected light beam, the light beam of blue light (B) is reflected by the blue light reflecting layer of the dichroic mirror 1151, and is modulated by the reflection-type electro-optical device 100B. Further, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of red light (R) is
The light is reflected by the red light reflection layer 52 and is modulated by the reflection type liquid electro-optical device 100R. On the other hand, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of green light (G) is
The light passes through the 52 red light reflecting layer and is modulated by the reflection-type electro-optical device 100G.

As described above, the electro-optical device 100R,
The red, green, and blue lights, each of which has been color-modulated by 100G and 100B, are output to a dichroic mirror 115.
2, 1151, and are sequentially synthesized by the polarizing beam splitter 1140, and then projected on the screen 1170 by the projection optical system 1160. In addition, the dichroic mirrors 1151 and 1152 attach the R, G, and
Since a light beam corresponding to each primary color of B enters, no color filter is required.

<Part 2: Mobile Computer> Next, an example in which the above-described electro-optical device is applied to a mobile personal computer will be described. FIG. 29 is a perspective view showing the configuration of this personal computer.
In the figure, a computer 1200 includes a keyboard 12
The main unit 1204 includes a main unit 1202 and an electro-optical device 100 used as a display unit. Note that, as described above, the electro-optical device 100 is used in principle as a reflection type, and furthermore, in this configuration, it is used as a direct-view type, so that in the pixel electrode 118, reflected light is scattered in various directions. In addition, a configuration in which unevenness is formed is desirable. In addition, if the amount of external light is small, visibility deteriorates. Therefore, a configuration in which an auxiliary light is provided on the front surface of the electro-optical device 100 is preferable.

<Part 3: Mobile Phone> Further, an example in which the electro-optical device 100 is applied to a mobile phone will be described. FIG. 30 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 includes the above-described electro-optical device 100 in addition to a plurality of operation buttons 1302, an earpiece 1304, and a mouthpiece 1306. Also in this configuration, it is desirable that the pixel electrode 118 be formed with irregularities and that an auxiliary light be provided on the front surface of the electro-optical device 100.

Further, in the electro-optical device 100, the memory in the pixel 110 is the SRAM shown in FIG. 18, FIG. 19, FIG. 22, or FIG. 23, and the above-described random write configuration is employed. Is desirable. The reason is that if the memory is an SRAM, the data Ds
Is self-held, and if a random write configuration is used, the data Ds only needs to be written to the necessary pixels, and power consumption can be reduced. For example, in standby mode, necessary information such as electric field strength and numbers / characters are displayed as characters using the minimum area of the display screen, and if the remaining area is hidden, the characters are displayed. As long as there is no power, almost no power is consumed, so that the continuous standby time can be lengthened.

FIGS. 28 to 30 show examples of electronic equipment.
In addition to those described with reference to the above, a liquid crystal television, a viewfinder type, a video tape recorder of a monitor direct-view type, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a PO
An S terminal, a device equipped with a touch panel, and the like are included. Needless to say, the electro-optical device according to the embodiment or the applied form can be applied to these various electronic devices.

[0171]

As described above, according to the present invention, the signal applied to the data line becomes binarized data and each pixel is simultaneously turned on or off in each subfield. High quality gradation display is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the invention.

FIG. 2 is a circuit diagram showing one mode of a pixel of the electro-optical device.

FIG. 3 is a block diagram showing a configuration of a data line driving circuit in the same electro-optical device.

FIG. 4A is a diagram illustrating a voltage-transmittance characteristic in the same electro-optical device, and FIG. 4B is a diagram for explaining a concept of a subfield in the same electro-optical device.

FIG. 5 is a table showing conversion contents of gradation data of a data conversion circuit in the same electro-optical device.

FIG. 6 is a timing chart showing a first driving method in the electro-optical device.

FIG. 7 is a timing chart showing a voltage waveform applied to a liquid crystal layer corresponding to each gradation data in the same electro-optical device.

FIG. 8A is a circuit diagram illustrating a mode of a pixel used in a conventional electro-optical device, and FIG. 8B is a diagram assumed when data writing and voltage application to a liquid crystal layer are performed simultaneously. 5 is a timing chart for explaining a malfunction that is performed.

FIG. 9 is a timing chart for explaining the superiority of the electro-optical device.

FIG. 10 is a timing chart showing a second driving method in the electro-optical device.

FIG. 11 is a timing chart for explaining the superiority of the electro-optical device.

FIG. 12 is a timing chart showing a modification of the second driving method in the same electro-optical device.

FIGS. 13A and 13B are block diagrams showing application forms of a data line driving circuit in the same electro-optical device.

FIG. 14 is a timing chart showing the operation of the data line drive circuit according to the application.

FIG. 15 is a block diagram showing a configuration of a clock signal supply control circuit in an application form of the electro-optical device.

FIG. 16 is a timing chart showing the operation of the clock signal supply control circuit.

FIG. 17 is a circuit diagram showing another mode of the pixel in the same electro-optical device.

FIG. 18 is a circuit diagram showing another mode of the pixel in the same electro-optical device.

FIG. 19 is a circuit diagram showing another mode of the pixel in the same electro-optical device.

FIG. 20 is a circuit diagram showing another mode of the pixel in the same electro-optical device.

FIG. 21 is a circuit diagram showing another mode of the pixel in the same electro-optical device.

FIG. 22 is a circuit diagram showing another mode of the pixel in the same electro-optical device.

FIG. 23 is a circuit diagram showing another mode of the pixel in the same electro-optical device.

FIGS. 24A, 24B, and 24C are diagrams each showing a specific configuration of load resistance.

FIG. 25 (a), (b), (c) and (d)
FIG. 3 is a diagram showing voltage levels used in each pixel mode.

FIG. 26 is a plan view showing the structure of the electro-optical device.

FIG. 27 is a sectional view showing the structure of the electro-optical device.

FIG. 28 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 29 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 30 is a perspective view showing a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device is applied.

[Explanation of symbols]

100 electro-optical device 101 element substrate 101a display area 102 counter substrate 105 liquid crystal (electro-optical material) 108 counter electrode 112 scanning line 114 data line 118 pixel electrode 130 scanning line driving circuit 140 ... Data line drive circuit 1410... X shift register 1420... Latch circuit 200... Timing signal generation circuit 300... Data conversion circuit 400. ..... Clock signal supply control circuit Ta1-Ta6, Tb1, Tb2 ... Transistors

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 641 G09G 3/20 641A F term (Reference) 2H093 NA56 NC10 NC16 NC22 NC24 NC26 NC28 NC34 NC35 ND06 ND10 ND33 ND34 ND35 ND39 ND49 NE06 NG02 5C006 AA14 AA15 AC26 AF44 AF51 BB16 BB28 BC03 BC12 BC20 BF03 BF04 BF06 BF15 BF26 BF27 EC01 EC11 FA56 5C080 AA06 AA10 BB05 DD03 EE29 FF05 KK04 JJ04 KK05 JJ02 KK03

Claims (19)

[Claims] 1. A method for driving an electro-optical device, wherein a plurality of pixels each including a memory, a pixel electrode provided corresponding to the memory, and a counter electrode facing the pixel electrode are displayed in gradations. One field is divided into a plurality of sub-fields, and in each of the sub-fields, data for instructing ON or OFF according to the gradation of the pixel is written to the memory of the pixel, and based on the written data, And turning on or off the plurality of pixels at the same time. 2. A method for driving an electro-optical device, wherein a plurality of pixels each including a memory, a pixel electrode provided corresponding to the memory, and a counter electrode facing the pixel electrode are displayed in gradations. 1 field is divided into a plurality of subfields, and in each of the subfields, data for instructing ON or OFF according to the gradation of the pixel is written to the memory of the pixel, and data is written to the memory. A driving method for the electro-optical device, wherein the pixels are sequentially turned on or off for each of the selected pixels. 3. A reference signal that repeats level inversion at predetermined time intervals is applied to the counter electrode, and an on signal having a different level from the reference signal is applied to the pixel electrode when the pixel is turned on. 3. The method of driving an electro-optical device according to claim 1, wherein when the pixel is turned off, an off signal having the same level as the reference signal is applied. 4. The method according to claim 1, wherein a period of the level inversion of the reference signal is different from a time length of the field. 5. A semiconductor device according to claim 1, wherein said plurality of scanning lines and said plurality of data lines are arranged corresponding to respective intersections thereof. When a scanning signal is supplied to said scanning lines, an on or off supplied to said data lines is turned on or off. A memory for writing data to be instructed, a pixel electrode provided corresponding to the memory, and selecting one of an on signal and an off signal based on data for instructing on or off written in the memory. A driving circuit of an electro-optical device that drives a plurality of pixels each including a first switching element applied to the pixel electrode and a counter electrode facing the pixel electrode, wherein a plurality of sub-fields obtained by dividing one field A scanning line driving circuit that supplies the scanning signal to the scanning line, and a scanning signal that is supplied to a scanning line corresponding to each pixel in each of the subfields. And a data line driving circuit that supplies data indicating on or off in accordance with the gradation of the pixel to a data line corresponding to the pixel, And a control circuit for controlling signals applied to the pixel electrode and the counter electrode so that the plurality of pixels are simultaneously turned on or off. 6. A system according to claim 1, wherein said plurality of scanning lines and said plurality of data lines are provided corresponding to respective intersections, and when a scanning signal is supplied to said scanning line, an on or off supplied to said data line is turned on or off. A memory for writing data to be instructed, a pixel electrode provided corresponding to the memory, and selecting one of an on signal and an off signal based on data for instructing on or off written in the memory. A driving circuit of an electro-optical device that drives a plurality of pixels each including a first switching element applied to the pixel electrode and a counter electrode facing the pixel electrode, wherein a plurality of sub-fields obtained by dividing one field A scanning line driving circuit that supplies the scanning signal to the scanning line, and a scanning signal that is supplied to a scanning line corresponding to each pixel in each of the subfields. A data line driving circuit for supplying data for instructing ON or OFF according to the gradation of the pixel to a data line corresponding to the pixel during the supplied period, and for each pixel for which data has been written to the memory. A control circuit for controlling signals applied to the pixel electrode and the counter electrode so that the pixel is sequentially turned on or off. 7. The data line driving circuit, comprising: a shift register that sequentially shifts and outputs a latch pulse signal supplied at the beginning of a horizontal scanning period in accordance with a clock signal; and wherein the data is shifted by the shift register. 7. The driving circuit for an electro-optical device according to claim 5, further comprising: a latch circuit for simultaneously latching the data distributed to a plurality of systems by a signal. 8. A shift register for sequentially shifting and outputting a latch pulse signal supplied at the beginning of a horizontal scanning period according to a clock signal, wherein the data line driving circuit shifts the data by the shift register. A first latch circuit that sequentially latches by a signal, latches the data latched by the first latch circuit based on the latch pulse signal, and simultaneously outputs the data signal to a corresponding data line as the data signal; 7. The driving circuit according to claim 5, further comprising a second latch circuit. 9. The electro-optical device according to claim 8, wherein the first latch circuit simultaneously latches the data distributed to a plurality of systems by a signal shifted by the shift register. Drive circuit. 10. In one subfield, after the scanning line driving circuit supplies the scanning signal to the scanning line, the supply of the clock signal to the shift register is stopped, and the next subfield starts. 10. The driving circuit for an electro-optical device according to claim 5, further comprising a clock signal supply control circuit that restarts the supply of the clock signal. 11. A plurality of scanning lines, a plurality of data lines,
An electro-optical device having a plurality of pixels arranged corresponding to each intersection of a scanning line and a data line, wherein the pixel is provided with a scanning signal on a scanning line corresponding to the intersection.
A memory for writing data for instructing ON or OFF of a pixel supplied to the data line; a pixel electrode provided corresponding to the memory; and a data for instructing ON or OFF written in the memory. An electro-optical device comprising: a first switching element that selects one of an on signal and an off signal and applies the selected signal to the pixel electrode; and a counter electrode facing the pixel electrode. 12. In each of a plurality of subfields obtained by dividing one field, a scanning line driving circuit that supplies the scanning signal to the scanning line, and a scanning line corresponding to each pixel in each of the subfields. A data line driving circuit for supplying the data corresponding to the gradation of the pixel to a data line corresponding to the pixel during a period in which the scanning signal is supplied; and 12. The electro-optical device according to claim 11, further comprising: a control circuit for controlling signals applied to the pixel electrode and the counter electrode so that the plurality of pixels are simultaneously turned on or off. 13. A scanning line driving circuit for supplying the scanning signal to the scanning line in each of a plurality of subfields obtained by dividing one field, and a scanning line corresponding to each pixel in each of the subfields. A data line driving circuit for supplying the data corresponding to the gradation of the pixel to a data line corresponding to the pixel during a period in which the scanning signal is supplied; and The electro-optical device according to claim 11, further comprising: a control circuit that controls a signal applied to the pixel electrode and the counter electrode so as to turn the pixel on or off. 14. The memory, further comprising: a second switching element that is turned on by the scanning signal; and, when the second switching element is turned on, writes data on a corresponding data line, and writes the second switching element. 14. The electro-optical device according to claim 11, further comprising: a capacitor for holding written data when the element is turned off. 15. The electro-optical device according to claim 14, wherein the second switching element is a combination of a P-channel type transistor and an N-channel type transistor in a complementary manner. 16. The memory, wherein the second switching element that is turned on by the scanning signal is written into the memory, and when the second switching element is turned on, data is written to a corresponding data line, and the second switching element is turned on. 14. An inverter according to claim 11, further comprising two inverters each having an output of one of the inverters for holding written data and having an output of the other inverter when the element is in a non-conductive state. Electro-optical device. 17. The first switching element, comprising: a first switch for selecting one of signals applied to the pixel electrode according to data written to the memory; and a second switch for selecting the other signal. 17. The device according to claim 11, wherein the first switch and the second switch are each a combination of a P-channel transistor and an N-channel transistor in a complementary manner. An electro-optical device according to claim 1. 18. The semiconductor device according to claim 11, wherein the plurality of pixels, the scanning line driving circuit, and the data line driving circuit are formed on a semiconductor substrate, and the pixel electrode has reflectivity. An electro-optical device according to claim 1. 19. An electronic apparatus comprising the electro-optical device according to claim 11.