JP2002162944A - Driving method of optoelectronic device, driving circuit, optoelectronic device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase display capacity and to increase the number of gray scales reducing the transfer speed of display elements in the case of conducting gray shades display by subfield driving. SOLUTION: Plural pixels 110 are arranged at intersections of pural data lines 114 and plural scanning lines 112. The pixels 110 are provided with pixel electrodes and electrooptical elements which are held in the intersection regions of the lines 114 and 112. Driving circuits (130 and 140) of an optoelectronic device conduct the gray shades display by driving the pixels 110 to on and off states in accordance with gray scale data. Each field is divided into plural subfields. A subfield, which becomes the minimum period among the plural subfields, is approximately made equal to the threshold period when optoelectronic material that constitutes the pixels is pulsewidth-modulated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method, a driving circuit, an electro-optical device, and an electronic apparatus for an electro-optical device which performs gradation display control by pulse width modulation.

[0002]

2. Description of the Related Art An electro-optical device, for example, a liquid crystal display device using liquid crystal as an electro-optical material is a cathode ray tube (CRT).
It has been widely used as a display device to replace the display unit of various information processing devices and wall-mounted televisions.

Here, a conventional electro-optical device is, for example,
It is configured as follows. That is, the conventional electro-optical device includes a pixel electrode arranged in a matrix, an element substrate provided with a switching element such as a TFT (Thin Film Transistor) connected to the pixel electrode, and a pixel electrode. It is composed of an opposing substrate on which opposing opposing electrodes are formed, and a liquid crystal as an electro-optical material filled between the opposing substrates.

In such a configuration, when a scanning signal is applied to a switching element via a scanning line, the switching element becomes conductive. In this conductive state, when an image signal of a voltage corresponding to the gradation is applied to the pixel electrode via the data line, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Stored. After the charge storage, even if the switching element is turned off, the charge storage in the liquid crystal layer is maintained by the capacitance of the liquid crystal layer itself, the storage capacitance, and the like. As described above, when each switching element is driven and the amount of charge to be stored is controlled in accordance with the gradation, the alignment state of the liquid crystal changes for each pixel, so that the density changes for each pixel. Therefore, it is possible to perform gradation display.

At this time, it is only necessary to accumulate charges in the liquid crystal layer of each pixel for a part of the period. First, each scanning line is sequentially selected by a scanning line driving circuit, and secondly,
In the scanning line selection period, the data lines are sequentially selected by the data line driving circuit, and thirdly, the selected data lines are sampled with an image signal of a voltage corresponding to a gray scale. Time-division multiplex driving in which a line is shared by a plurality of pixels becomes possible.

[0006]

However, the image signal applied to the data line is a voltage corresponding to the gradation, that is, an analog signal. For this reason, a peripheral circuit of the electro-optical device requires a D / A conversion circuit, an operational amplifier, and the like, thereby increasing the cost of the entire device. Furthermore, display unevenness occurs due to the characteristics of the D / A conversion circuit and the operational amplifier, and the non-uniformity of various wiring resistances, so that high-quality display is extremely difficult.
This problem is particularly noticeable when performing high-definition display.

In order to solve the above problem, a digital drive system for driving a liquid crystal in an electro-optical device, for example, a liquid crystal device, divides one field into a plurality of subfields and divides each pixel in each subfield. There has been proposed a sub-field driving method for controlling an on state or an off state according to a gray scale.

In this subfield driving method, the voltage applied to the liquid crystal is changed not by the voltage level but by the application time of the voltage pulse. It controls the rate (or reflectivity), and the voltage level is only the ON level and the OFF level.

By the way, in the subfield driving method,
The transfer speed is increased by rewriting the entire screen for each subfield a plurality of times in one field. In the case of a liquid crystal device, the time required to write a voltage to a selected pixel (selection time) is very long. There is a problem that it becomes shorter.

The selection time for selecting a certain line on the display screen is, for example, 10 scan lines per screen with 6-bit gradation.
In the case of the normal voltage modulation in which the selection is performed only once in one field in the case of the 00 line, it is 1F / 1000.
0 × 26), which is 1/64 of the selection time in the case of normal voltage modulation. In this case, a sufficient writing time cannot be secured, and the ratio of the period during which the ON / OFF voltage is output for each pixel in one field does not reach the ratio for performing a desired gradation display, thereby causing display unevenness. There was a problem.

The present invention has been made in view of such circumstances, and when performing gray scale display by subfield driving, the transfer speed of the display element is reduced to increase the display capacity and increase the number of gray scales. It is an object of the present invention to provide an electro-optical device that can be implemented, a driving method thereof, a driving circuit thereof, and an electronic apparatus using the electro-optical device.

[0012]

In order to achieve the above object, a first aspect of the present invention is to provide a liquid crystal display device, which is provided corresponding to the intersection of a plurality of data lines and a plurality of scanning lines, and includes a pixel electrode and the plurality of scanning lines. A driving method of an electro-optical device for driving a plurality of pixels each including a data line and an electro-optical element sandwiched between intersection regions of a plurality of scanning lines in an on state or an off state in accordance with gradation data to perform gradation display. And each field is 1
The field is divided into a plurality of sub-fields, and the sub-field which is the minimum period among the plurality of sub-fields is substantially equal to a threshold period when the electro-optical material forming the pixel is pulse width modulated. It is characterized by.

[0013] In one embodiment of the first invention, 1
The period of each subfield obtained by dividing the field is a period in which a different effective voltage can be applied to the pixel for each subfield.

In the present invention, one field is a period required for forming one raster image by performing horizontal scanning and vertical scanning in synchronization with a horizontal scanning signal and a vertical scanning signal. Means
Therefore, one frame in the non-interlace system or the like also corresponds to one field in the present invention.

According to the first aspect of the present invention, the pixel electrode is provided corresponding to the intersection of the plurality of data lines and the plurality of scanning lines,
A plurality of pixels each including the plurality of data lines and the electro-optical element sandwiched between the intersections of the plurality of scanning lines are driven in an on state or an off state in accordance with the gradation data to perform gradation display. In this case, each field is 1
The field is divided into a plurality of sub-fields, and the sub-field which is the minimum period of the plurality of sub-fields is substantially the same as the threshold period when the electro-optical material forming the pixel is pulse width modulated. .
This makes it possible to drastically increase the transfer speed of the display element and the pixel selection time when performing gradation display by subfield driving, and to minimize the period of the subfield even if the number of gradations is increased. Almost no need to shorten. Therefore, the display capacity can be increased and the number of gradations can be increased. Further, a second invention is a pixel electrode arranged corresponding to each intersection of a plurality of scanning lines and a plurality of data lines,
A switching element that controls a voltage applied to each of the pixel electrodes, an electro-optic material sandwiched between intersections of the plurality of data lines and a plurality of scanning lines, and a counter electrode disposed to face the pixel electrodes. A driving circuit of an electro-optical device for driving a pixel, comprising: dividing each field into a plurality of sub-fields per one field; Scanning line driving for supplying a scanning signal for turning on the switching element to each of the scanning lines in each of the plurality of sub-fields, while maintaining the threshold period when the electro-optical material to be subjected to pulse width modulation is substantially equal to the threshold period. A circuit and a data signal indicating an ON state or an OFF state of each pixel are sent to a scanning line corresponding to the pixel. And a data line driving circuit for supplying data to a data line corresponding to the pixel during a period in which the pixel is supplied, wherein the data signal includes a time for turning on each pixel in one field and a time for turning off each pixel in one field. The signal is a signal instructing the ON state or the OFF state of each pixel so that the ratio of the time to the corresponding time corresponds to the gradation of the pixel. In one aspect of the second invention, the period of each subfield obtained by dividing one field is a period in which a different effective voltage can be applied to the pixel for each subfield.

According to the second aspect, a pixel electrode provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and a switching element for controlling a voltage applied to each pixel electrode are provided. A pixel including an electro-optical material sandwiched in the intersection region of the plurality of data lines and the plurality of scanning lines, and a counter electrode disposed to face the pixel electrode, each field having a plurality of In each of the subfields divided into subfields, driving is performed in an on state or an off state in accordance with the gradation data, and gradation display is performed. In this case, in each of the plurality of subfields, a scanning signal for turning on the switching element is:
A period in which a data signal supplied to each of the scanning lines by the scanning line driving circuit and indicating an ON state or an OFF state of each pixel is supplied to the scanning line corresponding to the pixel by the data line driving circuit. Is supplied to the data line corresponding to the pixel.

Here, each field is divided into a plurality of subfields, and a subfield having a minimum period is substantially the same as a threshold period when pulse width modulation is performed on the electro-optical material constituting the pixel. Degree. This makes it possible to dramatically increase the transfer speed of the display element and the pixel selection time when performing gradation display by subfield driving, and to minimize the subfield period even if the number of gradations is increased. Need not be almost shortened. Therefore, the display capacity can be increased and the number of gradations can be increased.

Further, the data signal is set so that the ratio of the time for turning on each pixel to the time for turning off each pixel in one field is a ratio corresponding to the gradation of the pixel. This is a signal that indicates the ON state or the OFF state of the pixel. As a result, since the signal applied to the pixel consists only of the on and off levels, display unevenness due to non-uniformity of element characteristics and wiring resistance is suppressed, and high-quality and high-definition gradation display is possible. Becomes According to a third aspect of the present invention, there is provided a pixel electrode disposed corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, a switching element for controlling a voltage applied to each pixel electrode, and the pixel electrode. Each field is divided into a plurality of subfields per field, and a subfield which is a minimum period among the plurality of subfields constitutes the pixel. A scanning line driving circuit that supplies a scanning signal for turning on the switching element to each of the scanning lines, in each of the plurality of subfields, to be approximately the same as the threshold period when the pulse width modulation of the electro-optical material is performed. A data signal indicating an ON state or an OFF state of each pixel is supplied to a scanning line corresponding to the pixel during a period in which the scanning signal is supplied. A data line driving circuit for supplying data to a data line corresponding to the pixel, and the data signal is such that the ratio of the time for turning on each pixel to the time for turning off each pixel in one field is equal to The signal is a signal for instructing an ON state or an OFF state of each pixel so as to have a ratio corresponding to the gradation of the pixel. In one embodiment of the third invention, the period of each subfield obtained by dividing one field is a period in which a different effective voltage can be applied to the pixel for each subfield.

According to the third aspect, a pixel electrode provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines,
A switching element for controlling a voltage applied to each of the pixel electrodes, an electro-optical material sandwiched between intersections of the plurality of data lines and the plurality of scanning lines, and a pixel having a counter electrode disposed to face the pixel electrode But each field
In each of the subfields obtained by dividing one field into a plurality of subfields, the subfield is driven to an on state or an off state according to the gradation data, and gradation display is performed. In this case, in each of the plurality of subfields, a scanning signal for turning on the switching element is supplied to each of the scanning lines by a scanning line driving circuit, and a data signal indicating an ON state or an OFF state of each pixel is provided. During a period in which the scanning signal is supplied to the scanning line corresponding to the pixel, the data is supplied to the data line corresponding to the pixel by the data line driving circuit.

Here, in each field, a sub-field having a minimum period among a plurality of sub-fields obtained by dividing one field is substantially the same as a threshold period when pulse width modulation is performed on the electro-optical material constituting the pixel. Degree. This makes it possible to dramatically increase the transfer speed of the display element and the pixel selection time when performing gradation display by subfield driving, and to minimize the subfield period even if the number of gradations is increased. Need not be almost shortened. Therefore, the display capacity can be increased and the number of gradations can be increased. The data signal is 1
A signal instructing the ON state or OFF state of each pixel so that the ratio of the time for turning each pixel on in the field and the time for turning each pixel off is a ratio according to the gradation of the pixel. It is said. As a result, since the signal applied to the pixel consists only of the ON and OFF levels, display unevenness due to non-uniformity in element characteristics, wiring resistance, etc. is suppressed, and high-quality and high-definition gradation display is possible. Becomes

In the electronic device according to the fourth aspect of the present invention, since the above-described electro-optical device is provided, the transfer speed of the display element and the selection time of the pixel can be significantly increased, and the number of gradations can be increased. It is not necessary to shorten the period of the minimum sub-field even if is increased. Therefore, the display capacity can be increased and the number of gradations can be increased.

Further, since the signals applied to the pixels consist only of ON and OFF levels, display unevenness due to non-uniformity of element characteristics, wiring resistance, etc. is suppressed, resulting in high quality and high definition gray scale display. Becomes possible.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, the electro-optical device according to the present embodiment is a liquid crystal device using liquid crystal as an electro-optical material, and an element substrate and a counter substrate are adhered to each other with a constant gap therebetween, as described later, The liquid crystal as the electro-optical material is sandwiched. Further, in the electro-optical device according to the present embodiment, a semiconductor substrate is used as an element substrate, and a peripheral driving circuit and the like are formed here together with a transistor for driving a pixel. Prior to the description of the electrical configuration of the electro-optical device according to the embodiment of the present invention, a sub-field driving method applied to the electro-optical device will be described.

According to the sub-field driving method of the present invention, the sub-field driving method is provided so as to correspond to the intersection of a plurality of data lines and a plurality of scanning lines, and is provided in a pixel electrode and an intersection area of the plurality of data lines and a plurality of scanning lines. A plurality of pixels including an electro-optical material to be sandwiched between the pixels and driving the pixels in an on state or an off state in accordance with the gradation data to display gradations. Each field is divided into a plurality of subfields per field. In addition, a subfield having a minimum period among the plurality of subfields is substantially equal to a threshold period when pulse width modulation is performed on the electro-optical material forming the pixel.

Ordinary liquid crystals such as TN type liquid crystals perform gradation display by changing the transmittance (or reflectance) of the liquid crystal device by changing the applied effective voltage.

In a liquid crystal device as an electro-optical device,
The relationship between the effective voltage applied to the liquid crystal and the transmittance (or reflectance) of the liquid crystal device is as shown in FIG. 7 in the case of a normally black mode in which black display is performed when no voltage is applied. As shown in the figure, gradation display is realized by applying an effective voltage corresponding to each gradation to the liquid crystal. In addition, a normal liquid crystal has a so-called threshold value in which the transmittance does not change unless the effective voltage, which is the applied voltage, increases to some extent, as shown in FIG.

FIG. 8 shows the relative transmittance (reflectance) with respect to the writing pulse width of the liquid crystal when the time width of 1000 clocks corresponds to one field. If one field is 1/60 second, one clock (clk)
Becomes 16.7 μs. This characteristic is obtained by plotting measured data of relative transmittance (reflectance) when the liquid crystal having the characteristic shown in FIG. 7 is subjected to pulse width modulation at a voltage of 3.2 V. As is clear from FIG. 8, it can be seen that gradation display is possible even when the liquid crystal having the threshold characteristic is driven by pulse width modulation.

Also, even when the liquid crystal is driven by pulse width modulation, the response is close to the effective voltage response, and unlike a ferroelectric liquid crystal (FLC) or the like, it does not have linear gradation characteristics and has a threshold. You can see that. FIG. 9 shows the characteristics of the gradation data with respect to the write pulse width applied to the liquid crystal. In FIG. 9, the gradation data has 64 equally divided gradations. FIG. 10 is an enlarged view of a portion where the gradation data is small in FIG. FIG. 12 shows the relationship between the write pulse width (PW) corresponding to each gradation and the relationship obtained from FIG. 9 and FIG. In order to realize the pulse width (PW) corresponding to each gradation shown in FIG. 12 by combining periods corresponding to each subfield when one field is divided into a plurality of subfields, SF0 shown in FIG.
One field is composed of eight subfields of SF7. The total number of clocks of all subfields SF0 to SF7 is set to 1000 clocks corresponding to one field time.

The write pulse width assigned to each subfield shown in FIG. 15 used in the subfield driving method applied to the present invention is the write pulse width near the threshold at which the transmittance (reflectance) starts to change. It is characterized by being composed of Specifically, each field is set to 1
The point is that a subfield which is a minimum period among a plurality of subfields obtained by dividing a field is substantially equal to a threshold period when pulse width modulation is performed on the electro-optical material forming the pixel. This makes it possible to dramatically increase the transfer speed of the display element and the pixel selection time when performing gradation display by subfield driving, and to minimize the subfield period even if the number of gradations is increased. Need not be almost shortened. Therefore, the display capacity can be increased and the number of gradations can be increased.

As can be seen from FIG. 8, the threshold value of this liquid crystal is 80
It is around ~ 100 clocks.

The period (the number of clocks) of the subfield SF7 to which the maximum write pulse width is assigned is
The period (the number of clocks) of the subfield SF0 to which the minimum write pulse width is allocated is set to be smaller than the sum of the period (the number of clocks) of the subfield SF1 to which the next smaller write pulse width is allocated. I have. Further, the period (the number of clocks) of the subfield SF7 to which the maximum write pulse width is assigned is set to be 2.5 times or less the threshold write pulse width.

FIG. 17 shows the subfield S shown in FIG.
FIG. 11 is a diagram illustrating a relationship between converted data obtained by combining the number of clocks corresponding to the write pulse width assigned to each of F0 to SF7 and the write pulse width. In the figure, the conversion data is represented by an 8-bit binary number, the LSB corresponds to the subfield SF0, and the MSB corresponds to the subfield SF7. Since one field is composed of eight subfields, there are a total of 256 conversion data, that is, gradation data. In FIG. 17, for example, in the conversion data “00000010”, the bit corresponding to the subfield SF1 is “1”, and the writing pulse width (PW) of this conversion data is assigned to the subfield SF1 from FIG. Since the number of clocks of the write pulse width is 100, the conversion data "00
The write pulse width for “000010” is “100”
Becomes

In the converted data "00000101", the bits corresponding to the subfields SF0 and SF2 are "1", and the converted data has a write pulse width (PW) from the subfields SF0 and SF shown in FIG.
Since the number of clocks of the write pulse width assigned to 2 is 81 and 109, respectively, the converted data “000”
The write pulse width for “00101” is “190”
(81 + 109 = 190). By comparing FIG. 17 with FIG. 12, a write pulse width closest to the write pulse width corresponding to each gray scale in FIG. 12 is selected from FIG. 17 and assigned from gray scale 0 to gray scale 63 as in FIG. FIG. 13 shows the relationship between the gradation and the write pulse width. FIG. 14 shows the difference between the write pulse widths at each gradation in FIGS. 12 and 13. FIG.
The write pulse width of each gradation shown in FIGS. 13 and 14 to 12 is set to eight subfields SF0 to SF shown in FIG.
It can be seen that the combination of 7 can be reproduced almost faithfully. In this case, it is necessary to use eight subfields SF0 to SF7 in order to express image data of 6-bit gradation, but the length of one subfield is gradation display by a power of two. The time is greatly increased as compared with the case. Specifically, taking the subfield SF0 as an example, the period, that is, the number of clocks indicating the write pulse width allocated to the subfield SF0 is 81, and 1000 clocks are allocated to one field. The time corresponding to the field SF0 is (81/100
0) × 1 field period = 0.081 × 1 field period.

On the other hand, when gradation display is performed by a power of 2, (1/64) × 1 field period = 0.015
6 × 1 field period, 8 subfields S
The length of one subfield when gradation is displayed by a combination of F0 to SF7 is five times or more as compared with the case where gradation is displayed by a power of two. As described above, this effect in a liquid crystal panel that performs gradation display by subfield driving becomes more prominent as the number of gradations increases.

As shown in FIG. 11, there is a gradation data (transmittance) characteristic with respect to the write pulse width, that is, a threshold value, and the change in the transmittance is linear with respect to the write pulse width in the transmittance change region. Even in the case of performing gradation display by subfield driving of the present invention using an electro-optical material having characteristics, the data transfer speed can be greatly increased, and the display capacity can be increased and the number of gradations can be increased.

If a display element having the characteristics shown in FIG. 11 is to be displayed in a gray scale by the conventional sub-field driving method, the sub-field is formed in a period obtained by subtracting the threshold value. The subfield period becomes shorter.

On the other hand, when a display element having the characteristics shown in FIG. 11 is driven by the sub-field driving method of the present invention, if the sub-field configuration shown in FIG. Is possible, and the minimum subfield period can be increased by 5 times or more.

FIG. 18 is a diagram showing the contents of a look-up table used in a drive circuit of an electro-optical device described later.

Next, FIG. 1 shows the electrical configuration of the electro-optical device according to the embodiment of the present invention. 1, the electro-optical device includes a scanning line driving circuit 130, a data line driving circuit 140, a timing signal generating circuit 200, a data converting circuit 300, and a driving voltage generating circuit 400.

The timing signal generation circuit 200 generates various timing signals and clock signals described below in accordance with a vertical scanning signal Vs, a horizontal scanning signal Hs, and a dot clock signal DCLK supplied from a higher-level device (not shown). Circuit.

As a signal generated by the timing signal generation circuit 200, first, a field start signal F
S is a pulse signal output at the beginning of the field. Second, the start pulse DY is a pulse signal output first in each subfield obtained by dividing one field as described later. Third, the clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side). Fourth, the latch pulse LP is a pulse signal output at the beginning of the horizontal scanning period, and is output when the level of the clock signal CLY changes (that is, rises and falls). Fifth, the clock signal CLX is a signal that defines a so-called dot clock. Sixth, the AC drive signal FR is a signal used for AC driving the liquid crystal element by inverting the level for each field (one frame).

The drive voltage generation circuit 400 outputs voltages VG1 and VG2 for generating a scanning signal, voltages VS1, VS2 and VC for generating a data signal, and a common electrode voltage VLCCOM applied to the common electrode. The voltage VG1 is a voltage defining a high-level voltage level in the scanning signal;
VG2 is a voltage defining a low level voltage level in the scanning signal.

The voltage VS1 is the voltage level of a data signal output as a positive ON voltage signal with reference to the voltage VC to the liquid crystal layer when the AC drive signal FR is at a high level, and the voltage VS2 is the AC drive signal FR. When the drive signal FR is at a low level, this is the voltage level of the data signal output to the liquid crystal layer as a negative on-voltage with reference to the voltage VC. Voltage VC is the voltage level of the data signal output as the off voltage regardless of the state of AC drive signal FR.

On the other hand, in the display area 101a on the element substrate 101, a plurality of scanning lines 112 are shown in FIG.
It is formed to extend in the (row) direction, and a plurality of data lines 114 are formed to extend in the Y (column) direction. The pixels 110 are provided corresponding to the intersections of the scanning lines 112 and the data lines 114, and are arranged in a matrix. Here, for convenience of explanation, in the present embodiment, the total number of the scanning lines 112 is m and the data lines 114
Is described as a matrix type display device of m rows × n columns, where n is the total number (m and n are each an integer of 2 or more), but the present invention is not limited thereto.

As a specific configuration of the pixel 110, for example, a configuration shown in FIG.
In this configuration, the transistor (MOS FET) 116
The gate of the scan line 112 and the source of the data line 114
In addition, a drain is connected to the pixel electrode 118, and a liquid crystal 105 as an electro-optical material is interposed between the pixel electrode 118 and the counter electrode 108 to form a liquid crystal layer. Here, as described later, the opposite electrode 108
Actually, it is a transparent electrode formed on one surface of the opposing substrate so as to oppose the pixel electrode 118.

The potential of the common electrode 108 is set to the common electrode voltage VLCCO generated by the drive voltage generation circuit of FIG.
M is given. Further, the pixel electrode 118 and the ground potential GN
A storage capacitor 119 is formed between D and D to prevent leakage of charges stored in the liquid crystal layer.

Here, in the configuration shown in FIG.
Since only one channel type is used as the transistor 116, the pixel electrode 118 is formed by a parasitic capacitance formed between the gate and the drain of the transistor 116.
It is necessary to consider an offset voltage for compensating for a drop in the voltage applied to the P-channel and N-channel transistors, as shown in FIG. 2B. The effect of such an offset voltage can be canceled, and the common electrode potential VLCCOM can be set to the same voltage level as the off potential VC applied to the signal line, so that the circuit configuration can be further simplified. Become.

However, in this complementary configuration, it is necessary to supply voltage levels having mutually opposite phases as scanning signals, so that the scanning lines 112a, 112
2b is required.

The structure of the pixel is not limited to those shown in FIGS. 2A and 2B. For example,
In each pixel, a memory cell such as an SRAM may be configured using a transistor, a resistor, or the like, and each pixel may be turned on / off in accordance with H-level or L-level data written in each memory cell. . In such a case, there is an advantage that it is not necessary to address all the pixels for each subfield as described later. That is, the scanning signal need not be supplied to all the scanning lines, but needs to be applied only to the scanning lines connected to the pixels for rewriting the data recorded in the memory.

The description returns to FIG. Scan line drive circuit 1
Reference numeral 30 denotes a so-called Y shift register, which transfers a start pulse DY supplied at the beginning of a subfield in accordance with a clock signal CLY, and supplies a scan signal G1, G2, G3,. Circuit.

The data line driving circuit 140 outputs the driving data signal Ds during a certain horizontal scanning period to the data line 11.
After sequentially latching n pieces of data corresponding to the number of four, the voltage level determined from the relationship between the latched data and the alternating signal FR is applied to the corresponding data line 114 in the next horizontal scanning period. d2, d3, ..., d
n is a circuit that supplies all at once. Here, a specific configuration of the data line driving circuit 140 is as shown in FIG.

That is, the data line driving circuit 140
Shift register 1410 and first latch circuit 1420
And a second latch circuit 1430.
The X shift register 1410 outputs the latch pulse LP supplied at the beginning of the horizontal scanning period to the clock signal C.
LX, and latch signals S1, S2, S
,..., Sn are sequentially supplied. Next, the first latch circuit 1420 is a circuit that sequentially latches the drive data signal Ds at the falling edges of the latch signals S1, S2, S3,..., Sn.

Then, the second latch circuit 1430 simultaneously latches each of the drive data signals Ds latched by the first latch circuit 1420 at the falling edge of the latch pulse LP, and outputs the signals L1 and L2 to the multiplexer circuit 1440. , L3,..., Ln.

The multiplexer circuit 1440 receives the voltages Vs1, Vs2, and Vc from the drive voltage generation circuit, the AC drive signal FR from the timing signal generation circuit 200, and the second
The signals L1, L2, L3,.
, Ln are each supplied. The multiplexer circuit 1440 outputs one of the voltages Vs1, Vs2, and Vc based on the AC drive signal FR and the output signal Lj (j is an integer satisfying 0 ≦ j ≦ n) of the second latch circuit 1430. A voltage is selected, and a data signal dj of the selected voltage level is supplied to the data line 114. FIG. 3 (b)
Is a truth table indicating the function of the multiplexer circuit 1440. As shown in FIG.
0 is the L-level signal Lj from the second latch circuit 1430
Is supplied, the data signal dj of the voltage Vc is supplied to the data line regardless of the level of the AC drive signal FR.

In the electro-optical device according to this embodiment, the voltage applied to the liquid crystal layer is changed to VH (corresponding to the voltage VS1 or VS2) for turning on the pixel or VL (corresponding to voltage VC) for turning off the pixel. Only). One field (1f) is divided into eight periods to separate a period during which the voltage VH is applied to the liquid crystal layer from a period during which the voltage VL is applied. The eight divided periods will be referred to as subfields SF0 to SF7.

As described above with reference to FIGS. 7 to 17, by setting the periods of the subfields Sf1 to Sf7,
When writing is performed in accordance with the grayscale data, the voltage applied to the liquid crystal layer is VH (H (high) level) and VL (L (low) level). The gradation display corresponding to the transmittance can be performed.

Now, as described above, the subfields SF0 to SF0
In order to write the H level or the L level according to the gradation for each SF 7, it is necessary to convert the gradation data corresponding to the pixel in some form. The one that performs this conversion is shown in FIG.
In the data conversion circuit 300. Here, a specific configuration of the data conversion circuit 300 is as shown in FIG. That is, the data conversion circuit 300 supplies the 6-bit grayscale data D0 to D5, which are supplied in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK, and correspond to each pixel, to the subfield S.
The drive data signal Ds is converted into the drive data signal Ds for each of F0 to SF7.

The data conversion circuit 300 has a write control circuit 3010, a read control circuit 3020, a look-up table 3030, and a frame memory 3040.

The look-up table 3030 is shown in FIG.
And a table indicating the correspondence between the gradation and the conversion data shown in FIG.
0 to Di5 are converted to 8-bit conversion data Dm0 to Dm7 with reference to the above table.

FIG. 18 is a table showing the relationship between each of the 64 gradations from 0 gradation to 63 gradation and the corresponding write pulse width. 18 is a table obtained from the table showing the relationship between the conversion data and the write pulse width shown in FIG. 17 and summarized. The gradation is shown in decimal notation in the table for convenience, but is specified by 6-bit gradation data Di0 to Di5 as described above.

The write pulse control circuit 3010 has a built-in counter and the like, and has a vertical scanning signal Vs and a horizontal scanning signal Hs.
In addition, based on the dot clock signal DCLK, a write address and a write clock necessary for writing conversion data to the frame memory 3040 are generated and output to the frame memory 3040. Specifically, the counter is operated by using the horizontal synchronization signal Hs as a reset signal and the dot clock signal DCLK as a clock signal, and outputs the output to X
Address. Further, the counter is operated by using the vertical scanning signal Vs as a reset signal and the horizontal synchronization signal Hs as a clock signal, and the output thereof is set as a Y address. Where X,
Y is X (row) in the display area 101a in FIG. 1,
This is synonymous with X and Y in the Y (column) direction, and the X address and the Y address specify a memory area in which conversion data corresponding to gradation data of a specific pixel is stored. For each pixel, the conversion data is sequentially written to a predetermined memory area.

The read control circuit 3020 has a built-in counter and the like, and is necessary when reading conversion data from the frame memory 3040 based on the field start signal FS, start pulse DY, clock signals CLX and CLY, and latch pulse LP. A read address and a read clock are generated and output to the frame memory 3040. Specifically, the counter is operated using the field start signal FS as a reset signal and the start pulse DY as a clock signal, and the number of the subfield in one field is specified by the count value.

The start pulse DY is used as a reset signal, and the latch pulse LP (or the clock signal CLY) is used as the reset signal.
Is used as a clock signal to operate the counter, and the scanning value 112 is specified by the count value.

Further, the counter is operated with the latch pulse LP as a reset signal and the clock signal CLX as a clock signal, and the data line 114 to which the data line 114 corresponds is specified by the count value. As described above, the driving data signal Ds is sequentially read from a predetermined memory area and output for each pixel in each subfield.

The driving data signal Ds is supplied to the scanning line driving circuit 130 and the data line driving circuit 14.
0, the data conversion circuit 300 needs to output the field start signal FS.
, A start pulse DY, a clock signal CLY synchronized with horizontal scanning, a latch pulse LP defining the beginning of a horizontal scanning period, and a clock signal CLX corresponding to a dot clock signal.

As described above, in the data line driving circuit 140, after the first latch circuit 1420 latches the driving data signal Ds in a certain horizontal scanning period in a dot-sequential manner, in the next horizontal scanning period, The second latch circuit 1430 simultaneously latches the data held in the first latch circuit 1420 in response to the latch pulse LP,
Since the voltage level determined by the logical state with R is supplied to the data lines 114 at the same time as the data signals d1, d2, d3,..., Dn, the data conversion circuit 300 includes a scanning line driving circuit. Compared with the operation of the data line driving circuit 130 and the data line driving circuit 140, the driving data signal Ds is output at a timing preceding by one horizontal scanning period.

In the above embodiment, the scanning line driving circuit 130 and the data line driving circuit 140 (or one of them) are provided with the pixel 110 on the element substrate.
It is preferable to be constituted by a transistor formed together with the transistor 116 inside. When the element substrate is a semiconductor substrate, the transistor is formed as a MOS transistor, and when an insulating substrate such as glass is used, the transistor is formed as a thin film transistor.

Next, the operation of the electro-optical device according to the above embodiment will be described. FIG. 5 is a timing chart for explaining the operation of the electro-optical device.

First, the level of the AC drive signal FR is inverted every field (1f). On the other hand, the start pulse DY includes one field (1f) as described above,
It is supplied at the start of a subfield divided into intervals according to the write pulse width shown in FIG.

When the start pulse DY defining the start of the subfield Sf1 is supplied, the scanning line driving circuit 13
0 (see FIG. 1), the scan signals G1, G2, G3,.
Are sequentially output during the period (1 Va). Note that the period (1V
a) is set to a period substantially equal to the period of SF0 which is the shortest subfield.

Now, the scanning signals G1, G2, G3,.
m has a pulse width corresponding to a half cycle of the clock signal CLY, and the first scanning line 1 counted from the top.
The scanning signal G1 corresponding to 12 is configured to be output with a delay of at least a half cycle of the clock signal CLY after the clock signal CLY first rises after the start pulse DY is supplied. Therefore, after the start pulse DY is supplied at the beginning of the subfield and before the scan signal G1 is output, the latch pulse L
One shot (G0) of P is supplied to the data line driving circuit 140.

The case where one shot (G0) of the latch pulse LP is supplied will be examined. First, when one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140, the data lines driving circuit 140 (see FIG. 3) transfers the latch signals S1, S2, S3,
.., Sn are sequentially output during the horizontal scanning period (1H). Note that each of the latch signals S1, S2, S3,..., Sn has a pulse width corresponding to a half cycle of the clock signal CLX.

At this time, the first latch circuit 1 shown in FIG.
420 latches the drive data signal Ds to the pixel 110 corresponding to the intersection of the first scanning line 112 counted from the top and the first data line 114 counted from the left at the falling of the latch signal S1. Next, at the falling of the latch signal S2, the first scanning line 11 counted from the top
2 and the driving data signal Ds to the pixel 110 corresponding to the intersection of the second data line 114 counted from the left is latched. Similarly, the first scanning line 112 counted from the top is
Then, the drive data signal Ds to the pixel 110 corresponding to the intersection with the n-th data line 114 counted from the left is latched.

As a result, first, in FIG.
The driving data signal Ds for one row of pixels corresponding to the intersection with the actual scanning line 112 is latched by the first latch circuit 1420 in a dot-sequential manner. Note that the data conversion circuit 300 adjusts the grayscale data Di0 to Di0 of each pixel in accordance with the latch timing by the first latch circuit 1420.
It goes without saying that Di5 is converted into the drive data signal Ds and output.

Next, when the clock signal CLY falls and the scanning signal G1 is output, the first scanning line 112 counted from the top in FIG. All the transistors 116 of the corresponding pixel 110 are turned on. On the other hand, the falling edge of the clock signal CLY outputs the latch pulse LP. Then, at the falling timing of the latch pulse LP, the second latch circuit 1430 latches the drive data signal Ds, which is point-sequentially latched by the first latch circuit 1420, and sets the logical state with the AC signal FR. Are simultaneously supplied to each of the data lines 114 as data signals d1, d2, d3,..., Dn. Therefore, the pixels 11 in the first row counted from the top
0, the data signals d1, d2, d3,..., Dn
Are simultaneously written.

In parallel with this writing, the driving data signal Ds for one row of pixels corresponding to the intersection with the second scanning line 112 from the top in FIG. Is done.

Then, the same operation is repeated until the scanning signal Gm corresponding to the m-th scanning line 112 is output. That is, a certain scanning signal Gi (i is 1 ≦ i
≦ m) is output in one horizontal scanning period (1
In (H), writing of the data signals d1 to dn for one row of the pixel 110 corresponding to the i-th scanning line 112 and the pixel 11 corresponding to the (i + 1) -th scanning line 112 are performed.
Point-sequential latching of the drive data signal Ds for one row of 0 is performed in parallel. The pixel 11
The data signal written in the next subfield S
It is held until writing in F1.

Hereinafter, the same operation is repeated every time the start pulse DY defining the start of the subfield is supplied. However, the data conversion circuit 300 (see FIG. 1)
For conversion from the gradation data Di0 to Di5 to the drive data signal Ds, a look-up table 3030 having the contents of FIG. 18 is referred to.

Further, even if AC drive signal FR is inverted to the H level after one field has elapsed, the same operation is repeated in each subfield.

FIG. 6 shows a specific example of the timing when the conversion data corresponding to the specified 6-bit gradation data Di0 to Di5 is written in a certain pixel 110. For example,
The gradation data of the pixel at the i-th row and the j-th column in the display area 101a in FIG. 1 is “000101” (5 in decimal).
And As shown in this figure, the 6-bit grayscale data “000101” (10
When 5) is input in hexadecimal, the lookup table 303
0, that is, referring to the table of FIG. 18, the gradation data “000101” is converted into 8-bit conversion data “000”.
01100 "and written to the memory area of the frame memory 3040 at the designated address.

Here, the LSB of the 8-bit conversion data
Is the subfield SF0 and the MSB is the subfield SF
Equivalent to 7. Therefore, when the 8-bit conversion data corresponding to the gradation data of the pixel in the i-th row and the j-th column is read from the frame memory 3040, each subfield, that is, SF0, SF1, SF2, SF3, S
Data line 1 corresponding to F4, SF5, SF6, SF7
The drive data signal Ds, which is the drive data of No. 14, is
"0", "0", "1", "1", "0", "0",
It is output in the order of “0” and “0”. Thus, i
A voltage indicated by Vij is applied to the pixels in the row j column, and gradation is displayed in one field period (1f) so that the gradation becomes "5" in FIG. In the next field, since the alternating signal FR is low, the polarity is inverted and driving is performed.

In FIG. 6, 1Va is a period during which image data for one subfield is transferred and written on the screen.
In the present embodiment, since subfield SF0 is a subfield having a minimum period, subfield SF0
In the case of, image data for one screen may be written in a period corresponding to the subfield SF0. Similarly, in each of the subfields SF1 to SF7, image data for one screen is written in each subfield within the period of 1 Va.

The driving data signal Ds is set so that the ratio of the time for turning on each pixel to the time for turning off each pixel in one field becomes a ratio corresponding to the gradation of the pixel. Is a signal instructing the ON state or the OFF state of the. As a result, since the applied signal to the pixel is only turned on or off, display unevenness due to non-uniformity such as element characteristics and wiring resistance is suppressed. As a result, high-quality and high-definition gradation display can be performed. Become. According to the electro-optical device according to the present embodiment, each field is divided into a plurality of sub-fields, and a sub-field which is a minimum period is a pulse width-modulated electro-optical material forming the pixel. In the case where gradation display is performed by sub-field driving, the transfer speed of the display element and the selection time of pixels can be drastically increased, and the number of gradations can be increased. Even if this is done, it is not necessary to almost shorten the period of the minimum subfield. Therefore, the display capacity can be increased and the number of gradations can be increased.

Further, according to the electro-optical device of this embodiment, one field (1f) is divided into subfields Sf0 to Sf7 according to the voltage ratio of the gradation characteristic, and each subfield has a pixel. By writing the H level or the L level, the effective voltage value in one field is controlled. For this reason, the data signals d1 to dn supplied to the data lines 114 are only the H level or the L level in this embodiment, and are binary, so that the peripheral circuits such as the driving circuit have high precision. A circuit for processing an analog signal, such as a D / A conversion circuit or an operational amplifier, becomes unnecessary. Therefore, the circuit configuration is greatly simplified, and the cost of the entire device can be reduced. Further, the data signal d supplied to the data line 114
Since 1 to dn are binary, display unevenness due to non-uniformity such as element characteristics and wiring resistance does not occur in principle.
Therefore, according to the electro-optical device according to the present embodiment, high-quality and high-definition gradation display can be performed.

In the above-described embodiment, the level of the AC drive signal FR is inverted at a cycle of one field. However, the present invention is not limited to this. A configuration in which the level is inverted or the level is inverted for each subfield may be adopted.

<Overall Configuration of Liquid Crystal Device> Next, the structure of the electro-optical device according to the above-described embodiment and application will be described with reference to FIG.
9 and FIG. Here, FIG.
20 is a plan view showing a configuration of the electro-optical device 100, and FIG. 20 is a cross-sectional view taken along line AA ′ in FIG.

As shown in these figures, the electro-optical device 100 includes an element substrate 101 on which a pixel electrode 118 and the like are formed, and a counter substrate 1 on which a counter electrode 108 and the like are formed.
02 are bonded to each other with a certain gap therebetween by a sealant 104, and a liquid crystal 105 as an electro-optical material is sandwiched in this gap. Actually, the sealing material 104 has a cutout portion, and after the liquid crystal 105 is sealed through the cutout portion, it is sealed with a sealing material, but is omitted in these drawings.

Here, when the element substrate 101 is a semiconductor substrate as described above, the substrate is opaque. Therefore, the pixel electrode 118 is formed of a reflective metal such as aluminum, and the electro-optical device 100 is used as a reflective type. In contrast, the counter substrate 102
Is transparent because it is made of glass or the like. Of course, the element substrate 101 may be formed of a transparent insulating substrate such as glass. When such a transparent insulating substrate is used, a reflective display can be obtained by forming the pixel electrode with a reflective metal, and a transmissive display can be obtained by using other materials.

In the element substrate 101, a light-shielding film 106 is provided inside the sealant 104 and outside the display area 101a. In the region where the light-shielding film 106 is formed, the scanning line driving circuit 130 is formed in the region 130a, and the data line driving circuit 140 is formed in the region 140a. That is, the light shielding film 10
Numeral 6 prevents light from entering a drive circuit formed in this region. This light-shielding film 106 has a counter electrode 10
8 together with the counter electrode potential VLCCOM. Therefore, in the region where the light-shielding film 106 is formed, the voltage applied to the liquid crystal layer becomes almost zero.
The display state is the same as the state where no voltage is applied to the pixel electrode 118.

In the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line driving circuit 140 is formed and separated from the sealing material 104 by external control. It is configured to input signals and power.

On the other hand, the counter electrode 108 of the counter substrate 102
Is electrically connected to the light-shielding film 106 and the connection terminals on the element substrate 101 by a conductive material (not shown) provided in at least one of the four corners of the substrate bonding portion. That is, the common electrode voltage V
LCCOM is configured to be applied to the light-shielding film 106 via a connection terminal provided on the element substrate 101 and further to the counter electrode 108 via a conductive material.

In addition, depending on the use of the electro-optical device 100, for example, first, in the case of a direct-view type, first, color filters arranged in a stripe shape, a mosaic shape, a triangle shape, etc. Second, a light-shielding film (black matrix) made of, for example, a metal material or a resin is provided. When used as a light valve of a projector described later, no color filter is formed. In the case of a direct-view type, a front light for irradiating the electro-optical device 100 with light from the counter substrate 102 side is provided as necessary. In addition, an alignment film (not shown) rubbed in a predetermined direction or the like is provided on each of the electrode forming surfaces of the element substrate 101 and the counter substrate 102 so as to adjust the alignment of the liquid crystal molecules in a state where no voltage is applied. On the other hand, on the side of the counter substrate 101, a polarizer (not shown) corresponding to the alignment direction is provided. However, the liquid crystal 10
As 5, the use of polymer-dispersed liquid crystal dispersed as fine particles in a polymer eliminates the need for the above-described alignment film and photon, resulting in higher light use efficiency, and hence higher brightness and lower power consumption. This is advantageous in terms of conversion.

In the embodiment, the element substrate 101 constituting the electro-optical device is a semiconductor substrate.
Although the transistor 116 connected to the pixel electrode 118 and the components of the driving circuit are formed by MOS-type FETs, the present invention is not limited to this. For example, the element substrate 1
01 may be an amorphous substrate such as glass or quartz, and a semiconductor thin film may be deposited thereon to form a thin film transistor (TFT). When a TFT is used in this way,
A transparent substrate can be used as the element substrate 101.

The liquid crystal may be a TN type liquid crystal, or a liquid crystal.
STN (Super Twisted) having a twist orientation of 0 degree or more
Nematic) type, polymer-dispersed type, and dye (guest) having anisotropy in visible light absorption in the major axis direction and minor axis direction of molecules dissolved in liquid crystal (host) with a fixed molecular arrangement A guest-host type liquid crystal in which dye molecules are arranged in parallel with liquid crystal molecules can be used.

The liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned horizontally with respect to both substrates when voltage is applied. May be configured,
When a voltage is not applied, the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates, while when a voltage is applied, the liquid crystal molecules are arranged in a direction perpendicular to both substrates. Good. Further, instead of arranging the counter electrode on the counter substrate, the pixel electrode and the counter electrode may be arranged on the element substrate in a comb-like shape at intervals. In this configuration, the liquid crystal molecules are horizontally aligned, and the orientation direction of the liquid crystal molecules changes according to the horizontal electric field between the electrodes. As described above, as long as the liquid crystal and the alignment method are compatible with the driving method of the present invention, various types can be used.

In addition to the liquid crystal device, the electro-optical device can be applied to various electro-optical devices having an electro-optical effect having a threshold characteristic. As described above, the present invention is applied to all electro-optical devices having a configuration similar to the above-described configuration, and particularly to all electro-optical devices that perform grayscale display using pixels that perform on / off binary display. Applicable.

<Electronic Equipment> Next, some examples in which the above-described liquid crystal device is used in specific electronic equipment will be described.

<Part 1: Projector> First, a projector using the electro-optical device according to the embodiment as a light valve will be described. FIG. 21 is a plan view showing the configuration of this projector. As shown in this figure,
Inside the projector 1100, a polarized light illumination device 1110 is provided.
Are arranged along the system optical axis PL. In the polarized light illuminating device 1110, light emitted from the lamp 1112 is reflected by the reflector 1114 to become a substantially parallel light flux, and enters the first integrator lens 1120. As a result, the light emitted from the lamp 1112 is split into a plurality of intermediate light beams. This split intermediate beam is
The polarization conversion element 1130 having the second integrator lens on the light incident side is converted into one type of polarized light beam (s-polarized light beam) with almost uniform polarization direction, and emitted from the polarized light illumination device 1110.

Now, the s-polarized light beam emitted from the polarized light illuminator 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarizing beam splitter 1140. Of this reflected light beam, the light beam of blue light (B) is reflected by the blue light reflecting layer of the dichroic mirror 1151, and is modulated by the reflection-type electro-optical device 100B. Further, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of red light (R) is the dichroic mirror 11
The light is reflected by the red light reflection layer 52 and is modulated by the reflection type liquid electro-optical device 100R. On the other hand, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of green light (G) is the dichroic mirror 11
The light passes through the 52 red light reflecting layer and is modulated by the reflection-type electro-optical device 100G.

Thus, the electro-optical device 100R,
The red, green, and blue lights, each of which has been color-modulated by 100G and 100B, respectively,
2, 1151, and sequentially synthesized by the polarization beam splitter 1140, and then projected on the screen 1170 by the projection optical system 1160. The dichroic mirrors 1151 and 1152 attach R, G, and E to the electro-optical devices 100R, 100B, and 100G.
Since a light beam corresponding to each primary color of B enters, no color filter is required.

In the present embodiment, a reflection type electro-optical device is used, but a projector using a transmissive type electro-optical device may be used.

<2: Mobile Computer> Next, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 22 is a perspective view showing the configuration of the personal computer.
In the figure, a computer 1200 includes a keyboard 12
02, a display unit 1206,
It is composed of This display unit 1206 is
It is configured by adding a front light to the front surface of the electro-optical device 100 described above.

In this configuration, the electro-optical device 100
Is used as a reflection direct-view type, so that the pixel electrode 1
At 18, the reflected light is scattered in various directions,
A configuration in which unevenness is formed is desirable.

<Part 3: Mobile Phone> Further, an example in which the above-described electro-optical device is used in a mobile phone will be described. FIG. 23 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 has a plurality of operation buttons 130.
2, along with the earpiece 1304 and the transmitter 1306,
An electro-optical device 100 is provided. The electro-optical device 100 is also provided with a front light on its front surface as needed. Also in this configuration, the electro-optical device 1
Since 00 is used as a reflection direct-view type, it is desirable that the pixel electrode 118 be formed with irregularities.

Note that the electronic devices are shown in FIGS.
In addition to those described with reference to, a liquid crystal television, a viewfinder type, a video tape recorder of a monitor direct-view type, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a PO
An S terminal, a device equipped with a touch panel, and the like are included. Needless to say, the electro-optical device according to the embodiment or the application can be applied to these various electronic devices.

As described above, according to the present invention, a signal applied to a data line is binarized, and a high-quality gradation display can be performed.

[0107]

As described above, according to the present invention, each field is divided into a plurality of sub-fields, and the sub-field having the minimum period is the electro-optical material constituting the pixel. Is approximately the same as the threshold period when pulse width modulation is performed, so that when performing gradation display by sub-field driving,
The transfer speed of the display element and the pixel selection time can be drastically increased, and even if the number of gradations is increased, it is not necessary to almost shorten the period of the minimum subfield. Therefore, the display capacity can be increased and the number of gradations can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the invention.

FIG. 2 is a circuit diagram showing one mode of a pixel of the electro-optical device according to the embodiment of the present invention shown in FIG.

3A is a block diagram showing a configuration of a data line driving circuit in the electro-optical device according to the embodiment of the present invention shown in FIG. 1, and FIG. 3B shows a function of a multiplexer 1440 of the data line driving circuit. It is a truth table.

FIG. 4 is a block diagram showing a specific configuration of a data conversion circuit in the electro-optical device according to the embodiment of the present invention shown in FIG.

FIG. 5 is a timing chart showing an operation of the electro-optical device according to the embodiment of the present invention shown in FIG.

FIG. 6 is a timing chart showing a specific example of timing when conversion data corresponding to gradation data designated to a certain pixel is written.

FIG. 7 is a characteristic diagram showing a relationship between an effective voltage applied to a normally black mode liquid crystal and a transmittance (or reflectance) of the liquid crystal in a liquid crystal device as an electro-optical device.

FIG. 8 is a characteristic diagram showing a relative transmittance (reflectance) with respect to a writing pulse width of a liquid crystal in a liquid crystal device as an electro-optical device when a time width of 1000 clocks corresponds to one field.

FIG. 9 is a characteristic diagram showing characteristics of gradation data with respect to a writing pulse width applied to liquid crystal in a liquid crystal device as an electro-optical device.

FIG. 10 is an enlarged view of a portion where the gradation data is small in the characteristic diagram shown in FIG. 9;

FIG. 11 shows characteristics of gradation data (transmittance) with respect to a write pulse width of an electro-optical material having a threshold value and a change in transmittance in a change region of the transmittance having a linear characteristic with respect to the write pulse width. FIG.

FIG. 12 is a diagram showing a relation between a write pulse width (PW) corresponding to each gradation and a table obtained from the characteristic diagrams shown in FIGS. 9 and 10;

13 selects the write pulse width closest to the write pulse width corresponding to each gray scale in FIG. 12 from FIG. 17 and assigns it from gray scale 0 to gray scale 63, thereby changing the relationship between the gray scale and the write pulse width. FIG.

FIG. 14 is a diagram showing a difference between write pulse widths in each gradation in FIGS. 12 and 13 for each gradation;

FIG. 15 is a diagram showing an example of a relationship between eight subfields SF0 to SF7 forming one field and a write pulse width assigned to each subfield.

FIG. 16 is a diagram showing another example of a relationship between eight subfields SF0 to SF7 forming one field and a write pulse width assigned to each subfield.

FIG. 17 shows subfields SF0 to SF shown in FIG.
7 is a diagram showing a relationship between converted data obtained by combining the number of clocks corresponding to the write pulse width assigned to each of No. 7 and the write pulse width.

FIG. 18 is a diagram showing the contents of a look-up table in the data conversion circuit shown in FIG. 4;

FIG. 19 is a plan view showing the structure of the electro-optical device according to the embodiment.

FIG. 20 is a sectional view showing the structure of the electro-optical device according to the embodiment.

FIG. 21 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device according to the embodiment is applied.

FIG. 22 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device according to this embodiment is applied.

FIG. 23 is a perspective view showing a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device according to the embodiment is applied.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 electro-optical device 101 element substrate 101 a display area 102 counter substrate 105 liquid crystal (electro-optical material, electro-optical element) 108 counter electrode 112 scanning line 114 data line 116 transistor (switching element) 118 pixel electrode 119 storage capacitance 130 scanning line driving circuit 140 data line drive circuit 1410 X shift register 1420 first latch circuit 1430 second latch circuit 200 timing signal generation circuit 300 data conversion circuit 400 drive voltage generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 641 G09G 3/20 641A 642 642A (72) Inventor Yutaka Ozawa 3-3 Yamato, Suwa-shi, Nagano Prefecture No. 5 Seiko Epson Corporation (72) Inventor Ryo Ishii 3-3-5 Yamato, Suwa-shi, Nagano F-term in Seiko Epson Corporation (reference) 2H093 NA16 NA33 NA51 NA51 NB21 NC03 NC22 NC24 NC26 NC29 NC34 ND05 ND06 5C006 AA14 AA15 AA22 AC02 AF44 AF51 BB16 BC03 BC06 BC13 EC05 EC11 EC13 FA25 FA37 FA56 5C080 AA10 BB05 CC03 DD05 DD30 EE29 FF07 JJ01 JJ02 JJ03 JJ04 JJ05 JJ06 KK02 KK07 KK43

Claims (7)

[Claims] A plurality of data lines and a plurality of scanning lines; a pixel electrode; and an electro-optical element interposed between intersections of the plurality of data lines and the plurality of scanning lines. A method for driving an electro-optical device that performs grayscale display by driving a plurality of pixels having an on state or an off state according to grayscale data, wherein each field is divided into a plurality of subfields for one field, A method of driving an electro-optical device, wherein a sub-field having a minimum period among the plurality of sub-fields is substantially equal to a threshold period when pulse width modulation is performed on the electro-optical material forming the pixel. . 2. The electro-optical device according to claim 1, wherein a period of each subfield obtained by dividing one field is a period in which a different effective voltage can be applied to a pixel for each subfield. How to drive the device. 3. A pixel electrode disposed corresponding to each intersection of a plurality of scanning lines and a plurality of data lines; a switching element for controlling a voltage applied to each of the pixel electrodes; and a plurality of data lines. And an electro-optical material sandwiched in an intersection region of a plurality of scanning lines, and a driving circuit of an electro-optical device that drives a pixel including a counter electrode disposed to face the pixel electrode. One field is divided into a plurality of sub-fields, and a sub-field which is a minimum period among the plurality of sub-fields is made substantially equal to a threshold period when the electro-optical material constituting the pixel is pulse width modulated. In each of the plurality of sub-fields, a scanning line driving circuit for supplying a scanning signal for turning on the switching element to each of the scanning lines, and turning on each of the pixels. A data line driving circuit that supplies a data signal indicating a state or an OFF state to a data line corresponding to the pixel during a period in which the scanning signal is supplied to a scanning line corresponding to the pixel. The data signal is turned on or off so that the ratio between the time for turning on each pixel and the time for turning off each pixel in one field is a ratio corresponding to the gradation of the pixel. A driving circuit for an electro-optical device, which is a signal indicating a state. 4. The electro-optical device according to claim 3, wherein a period of each subfield obtained by dividing one field is a period in which a different effective voltage can be applied to a pixel for each subfield. The drive of the device. 5. A pixel electrode disposed corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, a switching element for controlling a voltage applied to each pixel electrode, and a pixel electrode. A pixel having a counter electrode disposed to face each other, each field being divided into a plurality of sub-fields per field, and a sub-field which is a minimum period among the plurality of sub-fields is defined as an electro-optical A scanning line driving circuit that supplies a scanning signal for conducting the switching element to each of the scanning lines in each of the plurality of subfields, and a scanning line driving circuit that supplies the scanning signal to each of the plurality of pixels; The data signal indicating the ON state or the OFF state of the pixel is supplied to the scanning line corresponding to the pixel during the period in which the scanning signal is supplied. And a data line driving circuit for supplying a corresponding data line, and the data signal is such that the ratio of the time for turning on each pixel to the time for turning off each pixel in one field is the same as that of the pixel. An electro-optical device, which is a signal for instructing an ON state or an OFF state of each pixel so as to have a ratio according to a gradation. 6. The electro-optical device according to claim 5, wherein the period of each subfield obtained by dividing one field is a period in which a different effective voltage can be applied to a pixel for each subfield. apparatus. 7. An electronic apparatus comprising the electro-optical device according to claim 5.