JP2001027886A - Driving circuit for high definition planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate left and right video signal data individually driving bisected left and right half side display areas by using respective single left side and right side line memories which respectively have the capacity capable of storing data equivalent to the 1/2 horizontal period of video signal data. SOLUTION: This driving circuit has a memory controller 45 which divides data equivalent to one horizontal period of the video signal data into data equivalent to the 1/2 horizontal periods of the first half and the second half and writes then respectively in left side and right side line memories and also which controls the left side and right side line memories so as to start the reading of the data equivalent to the 1/2 horizontal period of the first half written in the left side line memory and the data equivalent to the 1/2 horizontal period of the second half to be written in the right side line memory with the 1/2 speed of a speed at the time of respective write-ins or with a speed being slower a little than it from the prescribed point of time when the writing of data equivalent to the 1/2 horizontal period of the first half to the left side line memory is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PALC (Plasma Addressed Liquid Crystal).
The present invention relates to a driving circuit for a high-definition flat panel display device suitable for application to a display device, a PDP (Plasma Display Panel), and the like.

[0002]

2. Description of the Related Art Recently, large and thin display devices such as PDP and PALC display devices have been used to obtain more powerful images in consideration of the installation space that can be secured in a home. The television receivers used have become widespread.

[0003] With the advance of technology, these television receivers have realized much higher definition than the past, but the number of pixels in the horizontal direction is, for example, HDTV.
When the number of pixels in the horizontal direction of the high resolution digital television system (High Resolution Digital Television system) is 1920, the pixel clock frequency for driving this is considerably high at about 150 MHz, and the current high withstand voltage process I manufactured by semiconductor technology using
Even in the case of C, there is a limit to a driving method using this driving frequency directly. Therefore, in order to reduce the driving frequency, a screen left / right split driving method described below is employed.

A maximum operating frequency of a column driver IC for driving a display device having 1920 pixels in the horizontal direction is about 40.
MHz, first, the above 150 MHz
The z data string is alternately distributed to the upper and lower column electrodes to form a 75 MHz data string of 960 pixels each,
Further, the video signal of one horizontal period is divided into two areas on the left and right of each 480 pixels, and the divided signals are written into the line memory, and are simultaneously read out at half the clock frequency of 37.5 MHz, thereby performing a time axis expansion process. Driver I
The maximum operating frequency of C is set within 40 MHz.

That is, the simplest digital method of converting the rate into a video data string of 37.5 MHz lower than the maximum operating frequency of the column driver IC of 40 MHz (expanding the time axis), and then supplying the video data to the column driver IC. Signal processing is performed.

A display using a plasma-addressed liquid crystal display device (abbreviated as PALC) which forms a large screen equivalent to that of a television receiver or a projector device and realizes a thickness comparable to that of a TFT liquid crystal panel for a display portion. A device has been proposed.

This plasma addressed liquid crystal display device is
High brightness and high contrast comparable to TFT liquid crystal panels can be realized, and by utilizing PDP manufacturing technology,
Large screens can be realized.

A conventional plasma addressed liquid crystal display (PALC) for forming an image by an active matrix system will be described below with reference to FIGS.

First, a structure of a PALC used in a specific example of an embodiment of the present invention described later will be described with reference to FIGS. FIG. 10 shows PALC
FIG. 2 is an exploded perspective view of a liquid crystal display device using the same. FIG.
FIG. 2 is a perspective view showing a part of the structure of the ALC, and a part is shown in cross section. As shown in FIG. 10, the PALC 1 has a structure as a transmissive display device for forming an image by selectively transmitting a light beam radiated from a backlight 2 disposed on its back surface by an active matrix type liquid crystal. ing.

As shown in FIG. 11, a plasma substrate (back glass) 5 is provided with scanning grooves (cutting) at predetermined intervals, for example, horizontally partitioned into hollows by partition walls (ribs) 6, 6, 6,. The scanning groove formed by the following is also possible),
Are formed. In these scanning grooves 7, the anode electrodes 8,
, And the cathode electrodes 9, 9, 9,... Are formed at regular intervals so as to form a pair. That is, this scanning groove 7 constitutes a horizontal scanning line corresponding to the effective screen of PALC1, and the number of scanning lines (for example, about 480)
Book) is formed.

By arranging the thin glass substrate 10 on which an insulating layer is formed in front of the partition walls 6, 6, 6,..., The scanning grooves 7, 7, 7,.
The inside thereof is filled with a rare gas such as helium gas or a mixed gas of rare gases as a plasma gas.

The cathode electrode 9 is supplied with, for example, about -300 V from a plasma discharge driver circuit (not shown).
Is applied at a predetermined timing (however, a ground potential is applied to the anode electrode 8), and a plasma discharge occurs between the anode electrode 8 and the cathode electrode 9 as described later in detail. I try to make it.

By this plasma discharge, the plasma gas is ionized in the scanning groove 7 and an electric conductor (plasma channel) is formed until the plasma particles are completely extinguished. (Strobe).

In front of the thin glass (insulating layer) 10, a liquid crystal layer (liquid crystal display device) for forming pixels in a matrix is provided.
11, a color filter (layer) 12 composed of striped red, green, and blue filter portions 12R, 12G, and 12B corresponding to each color of red, green, and blue, and striped red and green driving pixels of the liquid crystal layer 11. , Blue drive electrodes 13R, 13G,
13B, transparent electrodes (transparent drive electrodes) (transparent electrode layers) (for example, ITO (Indium Tin Oxide: indium tin oxide) thin film) 13 are arranged at regular intervals in the scanning grooves 7,
Are arranged so as to be orthogonal to 7, 7,..., And each orthogonal portion thereof is configured to be each pixel.

That is, the transparent drive electrode 13 of the PALC 1
By supplying video signals (data) for one horizontal line to R, 13G, and 13B, and sequentially selecting (strobe) and discharging the plasma gas in the scanning groove 7 in the vertical direction, the transparent driving electrodes 13R, 13G, and 13B are discharged. A video signal is applied to the liquid crystal of the pixel where 13G, 13B and the scanning groove 7 intersect,
Since the transmittance of the light emitted from the backlight 2 differs for each pixel, a color image can be displayed.

That is, as shown in FIG.
A polarizing filter 3 is provided on each of the input side and the output side of the LC1,
By arranging 4, the transmission amount of the light polarized by the PALC 1 can be controlled, and a color image can be obtained by the same principle as that of a normal TFT liquid crystal display device.

Next, the switching operation for forming an image for one field will be described in more detail with reference to FIGS. FIG. 12 is a diagram schematically showing a part of the PALC 1 shown in FIG. 11 from the side. In order to explain the switching operation by the plasma channel,
FIG. 13A shows a switch SW for convenience.

As described above, when a plasma generating pulse of, for example, -300 V is applied to the cathode electrode 9 (a ground potential is applied to the anode electrode 8) and a plasma discharge is performed, a plasma channel is formed in the scanning groove 7. But
This plasma channel becomes a virtual electrode and the transparent electrode layer 1
3 (red, green and blue drive electrodes 13R, 13G, 13B) and the anode electrode 8 apply a video signal voltage. That is, the illustrated switch SW is turned ON.

FIG. 12 shows that when a voltage of -300 V is applied to the plasma channel by the switch SW, plasma gas is generated in the scanning groove 7 of the first line, and the strobe is generated.
The state where (1) is turned on is shown. This shows a state in which no plasma gas has yet been generated in the scanning groove 7 of the second line, and the strobe remains off. As shown in FIG. 12, when a plasma channel is formed by plasma discharge, the inside of the scanning groove 7 becomes conductive,
This is equivalent to FE, as shown in FIG. 13B.
T (Field-effect Transistor) can be described as the operation of the switching element.

By the switching operation by the plasma channel, a virtual electrode is generated on the inner surface of the thin glass (substrate) 10 shown in FIG.
By applying a video signal voltage for driving pixels to G and 13B, the scanning groove 7 and the driving electrodes 13R,
A drive voltage is applied to each pixel (for one line) of the liquid crystal layer 11 at the intersection of 13G and 13B.

Therefore, the plasma discharge is sequentially applied to the scanning grooves 7.
By scanning so as to occur within (for example, the first line to the 480th line) and forming an image of one field, for example, an image of one field can be displayed.

That is, after selecting which line of an image is to be formed by the plasma channel, a drive voltage for forming an image of that line is applied to the red, green and blue drive electrodes 13R, 13G and 13B. 1 realizes selective scanning of lines constituting one field.
At this time, the light transmitted through the liquid crystal layer 11 is
By transmitting the red, green, and blue filter sections 12R, 12G, and 12B, a color image can be displayed. This makes it possible to form an image for one field by sequentially applying a drive voltage to the cathode electrodes from the first line to the 480th line in synchronization with the driving of the pixels for one line.

By configuring a display device using a PALC capable of forming an image with such a structure and operation principle as a display device, a thin, lightweight, large-screen display device can be configured.

Referring to FIG. 14, a specific circuit of a driving device of a conventional liquid crystal display device having a plasma addressed liquid crystal display device will be described in detail. In FIG. 14, a BS / CS tuner or DVD is input through an input terminal 20.
(Digital Versatile Disc) MPEG (Mootion Pictur) from an external device such as a playback device, VTR (video tape recorder) (helical scan type magnetic recording and playback device), etc.
The video signal of the HDTV system coded by the e Experts Group-2) is supplied to the MPEG-2 decoder 21 and decoded. The HDTV luminance signal and color difference signal (both progressive signals) obtained from the MPEG-2 decoder 21 are supplied to the double speed conversion unit 22. Further, the MPEG-2 decoder 21 extracts a synchronization signal from a luminance signal obtained by decoding. This synchronizing signal is supplied to an LCD (Liquid Crystal Display) controller 29 described later, and the LCD controller 29 generates an operation clock of each function circuit described below to synchronize various signal processing. ing.

A frame memory capable of storing one frame of video signal (luminance signal and color difference signal) is provided in the double speed conversion section 22, and motion components are detected using this frame memory. Then, in the still image area of the video signal written in the frame memory, the video signal of the field at that time and the video signal of one horizontal period one field before are read twice consecutively at twice the writing speed.

In the moving image area of the video signal written in the frame memory, the video signal is generated by interpolation between the video signal of one horizontal period of the field information at that time and the video signals of one horizontal period above and below it. The interpolated video signal is read out at double speed and converted to a 1125 line / 60 Hz progressive signal.

The video signal that has been subjected to the double speed processing is subjected to color adjustment, hue adjustment, and the like under the control of the microcomputer control section 33 in the video signal processing section 23, and then subjected to inverse matrix processing to produce red, green, and blue colors. Each primary color signal is generated. Each of the primary color signals generated by the video signal processing unit 23 is supplied to an A / D converter 24 having 8-bit quantization accuracy, and is converted into digital red, green, and blue video data V8. The frequency of the clock used in the A / D converter 24 is 148.5 MHz which is twice the 74.25 MHz which is the sampling frequency of the interlaced video signal for HDTV.

The digital progressive video signal from the A / D converter 24 is alternately distributed to 960 pixels to the upper and lower column drive electrodes of the PALC 36, thereby obtaining
The driving frequency is 74.25, which is half of 148.5 MHz.
MHz and its driving frequency 74.25 MH
In order to further reduce z to 37.125 MHz, which is half of that, the left / right division drive circuit 60 performs double time axis expansion processing to perform left / right division drive of the PALC 36. The specific configuration of the left / right divided drive circuit 60 is shown in FIG.

The specific configuration and operation of the left / right division drive circuit 60 will be described later in detail with reference to FIGS. 8 and 9, but a part thereof will be described here. Video signal data from the A / D converter 24, as shown in FIG. 8, the left and right line memories _{41L 1, 41L 2; 41R 1} , after being time-base-decompressed twice through 41R _2, the left and right liquid crystal It is supplied to column drivers 28 and 27. Here, description of the changeover switches 42L and 42R is omitted.

Left and right liquid crystal column drivers 28, 2
Reference numeral 7 denotes video data for one horizontal period (for example, 1920 pixels), that is, 1920 pixels × 3 channels (red, green,
(Blue), that is, the video data V8 of 5760 pixels is latched, and the video data V8 of each pixel is held for one horizontal period. When a plasma discharge is generated in a predetermined scanning groove 7 (FIG. 11) by a plasma driver 31 to be described later, the readout is read out for each horizontal line, and further, a D / A converter built in the liquid crystal column drivers 28 and 27 After being converted into analog signals, the transparent drive electrodes (ITO) 13 (red, red, and black) of the left half and right half display areas of the PALC (plasma address type liquid crystal display device) 36 (1), respectively.
Green, blue drive electrodes 13R, 13G, 13B) (see FIG. 11).

Returning to FIG. 14, the description will be continued. The LCD controller 29 is configured to operate with a power supply of, for example, 5 V, and based on a system clock generated based on a synchronization signal from the MPEG-2 decoder 21, an anode inversion pulse ( The horizontal pulse H and the plasma driver 31 are driven to generate a plasma pulse for plasma discharge for each scanning groove 7 (horizontal line).

The anode drive voltage from the anode inversion drive circuit 30 is applied to the anode 8 (see FIG. 11) of the PALC 36 (1).

The plasma driver 31 is, here, an HDT
The horizontal scanning lines corresponding to 1080 lines constituting the screen of the V system, that is, the scanning grooves 7 formed in the PALC 36 (1) are sequentially selected as shown in FIG. About -300V applied
A plasma discharge is generated by the power supply voltage of.

That is, in synchronization with the double-speed video data V8 input to the left and right liquid crystal column drivers 28, 27 in FIG. 8, the scanning grooves 7, 7, 7,. The discharge state is repeated for each field, so that the PALC3
6 (1) can be driven. As a result, the input video signal can be displayed as a video.

The backlight 35 (2) is arranged as a light source for illuminating the PALC 36 (1) from the back side as shown in FIG.
A display image is formed by transmitting the predetermined pixel of (1). Further, picture adjustment can be performed by adjusting the brightness of the backlight 35 (2).

The microcomputer control unit 33 allows the user to operate the operation unit 32.
Various controls such as the above-described image adjustment and power ON / OFF are performed in accordance with a command input from the PC. In FIG. 14, the control target of the microcomputer control unit 33 and the microcomputer control unit 33
Is connected with a thin solid line.

Next, the plasma (discharge) driver 31 will be described in detail with reference to FIG. In FIG.
Anode 37 and cathode 9 of ALC37 (1)
Are also shown. The plasma driver 31 uses, for example, a voltage of about −300 V from the plasma power supply Ep, and this voltage is applied to the cathode electrode 9 (for example, the first line L1 to the 1080th line L1080: the number of effective scanning lines) of each line. 1), 9 (2), ..., 9 (1080)
Is applied through switching means and a current source.
The cathode electrodes 9 (1) to 9 (1080) are arranged as switching elements for plasma discharge, for example, NMOS (N channel MOS) transistors Tr.
(1), Tr (2),..., Tr (1080).

NMOS transistors Tr (1) to Tr
The source electrodes of (1080) are commonly connected, and are further connected to a plasma power source E through a current source Si of, for example, about 100 mA.
It is connected to the negative electrode of p, and is controlled so that the current at the time of plasma discharge is constant, so that stable plasma discharge is performed. Cathode electrode 9 (1), 9
, 8 (108) corresponding to the anode electrodes 8 (1), 8 (2),.
0) is commonly connected to the positive electrode of the plasma power supply Ep. Also, the NMOS transistors Tr (1) to Tr (1)
For example, a positive pulse (plasma discharge pulse) of about 10 μsec supplied from the LCD controller 29 of FIG. 14 is sequentially applied to the gate electrode of each line 080).

NMOS transistors Tr (1) to Tr
When the plasma pulse from the LCD controller 29 of FIG. 14 is sequentially applied to the gate electrode of (1080),
First, for example, a plasma discharge occurs between the anode electrode 8 (1) and the cathode electrode 9 (1) as shown by a hatched pattern on the first line L1, and thereafter, 1 is synchronized with the pixel signal for one line. Line L1 to 1080 Line L1
By sequentially applying a plasma pulse to the cathode electrodes 9 (1) to 9 (1080) up to 080, an image for one field can be formed.

Next, the phase relationship between the video drive signal (write video data) and the plasma discharge pulse supplied to the PALC 1 will be described with reference to FIG. When the effective video period for one line is about 14 μsec, for example, the NM corresponding to the first line L1 at the timing shown in FIG. 16B.
10 μsec to the gate electrode of the OS transistor Tr (1)
When a positive plasma pulse voltage having a width is applied, FIG.
As shown in C, a negative pulse voltage having a voltage of -300 Vpp and a width of 10 [mu] sec is applied to the cathode electrode 9 (1) corresponding to the first line L1, and a plasma discharge occurs in the first scanning groove 7. In a state where the scanning groove 7 is plasma-discharged, a video signal of a maximum of 70 Vpp sampled and held for each pixel shown in FIG.
The video signal for one line is applied to the PALC 37 (1)
(FIG. 14).

In the following second line L2, FIG.
As shown in the figure, the NMOS transistor Tr (2)
When a positive plasma pulse voltage having a width of 10 μsec is applied to the gate electrode of FIG.
A voltage of -300 is applied to the cathode electrode 9 (2) corresponding to
A negative pulse voltage of 10 μsec width is applied at V, and a plasma discharge is generated in the next scanning groove 7. In a state where the scanning groove 7 is plasma-discharged, as shown in FIG. 16A, sample-and-hold is performed for each pixel, and the inverted data of the video signal of the second line of 70 V at the maximum is about 14 μs, for example.
The voltage is continuously applied to the drive electrode (ITO) 13 during c. Thus, in the first field, the inversion drive is performed alternately for each of the odd-numbered lines and the even-numbered lines, and in the next field, the data is alternately and reversely driven in the opposite phase.
The AC drive of (1) is realized to prevent the deterioration of the liquid crystal molecules due to the continuous application of the DC voltage.

Next, the left / right divided drive circuit 60 in FIG. 14 will be described with reference to FIG. 8. The same reference numerals are given to portions corresponding to those in FIG. 14, and redundant description will be omitted. The first and second digital video signal data (digital red, green, and blue signal data) V8 from the A / D converter 24 in FIG. 14 each have a storage capacity capable of storing a half horizontal cycle of the video signal data. 2 left line memory 41
L ₁ , 41L ₂ and the first and second right-side line memories 41R ₁ , 41R _{2 so} that writing and reading are performed alternately line by line, respectively, and the first or second left-side line memory 41L ₁ , 41L _{2 and} the read output from the first or second right line memories 41R ₁ , 41R ₂ are respectively switched by the changeover switches 42L, 42R, and the left and right liquid crystal column drivers 2 are respectively switched.
8, 27. The first and second left line memories 41L ₁ and 41L ₂ and the first and second right line memories 41R ₁ and 41R ₂ have write and read address counters, respectively.

The horizontal synchronizing signal from the decoder 21 shown in FIG.
ASE Locked Loop) 44 to generate a write-side clock synchronized with the horizontal synchronization signal and a read-side clock having half the frequency of the write-side clock, and generate the write-side clock and the read-side clock. It is supplied to the memory controller 45. Memory controller 45
Are the first and second left line memories 41L ₁ , 41L
₂ and first and second right line memories 41R ₁ , 4
Supplying a read enable signal and the read side clock commonly to 1R _2. Also, the memory controller 45
A left write enable signal and a write clock are supplied to the first and second left line memories 41L ₁ , 41L ₂ and the first and second right line memories 41R ₁ , 4L 2
Supplies right write enable signal and the write side clock 1R _2. The memory controller 45 supplies a changeover signal for each line (H) to the changeover switches 42L and 42R.

Next, referring to FIG. 9, writing and writing to the first left (right) line memory 41L ₁ (41R ₁ ) and the second left (right) line memory 41L ₂ (41R ₂ ) of FIG. The read operation will be described. In FIG.
The horizontal axis represents time, and the vertical axis represents left and right line memories 4.
1L ₁ , 41L ₂ ; Write and read addresses of 41R ₁ , 41R ₂ are shown. A thin solid line indicates a change in a write address, and a thick solid line indicates a change in a read address. FIG.
As shown in FIG. 3A, the first and second half horizontal periods (T _H ) of the video signal data of the n-th line are divided into the first left line memory 41L ₁ and the first right line memory, respectively. the 41R _1, written as shown in the thin solid line (W). As shown in FIG. 9B, the first half and the second half of one horizontal period of the video signal data of the next (n + 1) th line
Each horizontal cycle is stored in the second left line memory 41L.
₂ and a second right line memory 41R _2, written as shown in the thin solid line with (W), as shown in FIG. 9A, respectively stored in the first left line memory 41L ₁ and the first right line memory 41R ₁ Of the first half and the second half of the video signal data of the n-th line,
Using a read clock having half the frequency of the write clock, read simultaneously as indicated by the thick solid line (R)
As a result, one horizontal cycle of the video signal data of the n-th line which is expanded in the time axis twice as long is obtained.

As shown in FIG. 9A, the next (n + 2) line
The first half and the second half of one horizontal period of the video signal data of the eye
/ 2 horizontal periods for the first left line memory 4
1L ₁And the first right line memory 41R₁And thin fruit
Along with writing (W) as shown by the line, as shown in FIG.
And the second left line memory 41L._TwoAnd the second right la
In-memory 41R_Two(N +
1) The first half and the second half of the video signal data of the line
The horizontal period is equal to half the frequency of the write clock.
Using the number of read clocks at the same time
By reading (R), the time axis is extended twice as long.
1 horizontal cycle of video signal data of the (n + 1) th line obtained
Minutes. Thereafter, the same operation as described above is repeated.

[0046]

In the prior art shown in FIG. 8, if the maximum operating frequency of a column driver IC for driving a display device having 1920 pixels in the horizontal direction is about 40 MHz, as described above. In addition, 150 of HDTV system
The MHZ data sequence is alternately distributed to the upper and lower column electrodes to form a 960 pixel 75 MHz data sequence, and further, the video signal for one horizontal period is divided into right and left regions of 480 pixels each and divided into two regions for the line memory. A time axis expansion process of writing and simultaneously reading out the data at a half clock frequency of 37.5 MHz is performed, and the data is stored within the maximum operating frequency of the column driver IC of 40 MHz. As many as four line memories having a capacity capable of storing a period (a line memory having a total storage capacity of two horizontal periods of video signal data)
There is a drawback that requires.

In view of the above, the present invention uses a single left and right line memory each having a capacity capable of storing a half horizontal period of video signal data, thereby realizing a high definition flat display device. An object of the present invention is to propose a driving circuit of a high-definition flat panel display device capable of generating left and right video signal data for separately driving the divided left and right half display areas.

[0048]

According to a first aspect of the present invention, there is provided a driving circuit for a high-definition flat-panel display device which drives the high-definition flat-panel display device by dividing the high-definition flat-panel display device into two right and left parts and driving them separately. In the circuit, a single left and right line memory for time axis expansion having a capacity capable of storing a half horizontal period of video signal data, and a writing side synchronized with a horizontal synchronizing signal related to the video signal data A write-side PLL that generates a clock and a horizontal sync signal are synchronized with a pseudo-horizontal sync signal having a phase difference of (（) horizontal period, and are の of the write-side clock frequency or its write side. A read-side PLL for generating a read-side clock having a frequency slightly lower than half the frequency of the clock; a write-side clock from the write-side PLL; and a read-side clock from the read-side PLL. Are supplied, and one horizontal cycle of the video signal data is divided into the first half and the second half of the horizontal cycle, respectively, and written into the left and right line memories, respectively. From a predetermined point in time when writing to the left line memory for the first half horizontal cycle is completed, the first half horizontal cycle of one horizontal cycle of the video signal data recorded in the left line memory and the right line The latter half 周期 horizontal cycle of one horizontal cycle of the video signal data to be written to the memory is calculated from the half speed of the writing speed or the half speed of the writing speed. A memory controller for controlling the left and right line memories so as to start reading at a slightly lower speed.

According to the first aspect of the present invention, in the driving circuit of the high-definition flat-panel display device, which divides the high-definition flat-panel display device into two right and left parts and drives each of them separately, one half of the video signal data
A left and right line memory for single time axis expansion each having a capacity capable of storing a horizontal period, a writing PLL for generating a writing clock synchronized with a horizontal synchronization signal related to video signal data, For the synchronization signal,
(1/2) Synchronizes with the pseudo horizontal synchronizing signal having a phase difference of the horizontal period, and is １ ／ of the frequency of the write-side clock, or
A read-side PLL that generates a read-side clock having a frequency slightly lower than half the frequency of the write-side clock
Are supplied to the memory controller with a write-side clock from the write-side PLL and a read-side clock from the read-side PLL, respectively, and the memory controller converts one horizontal cycle of the video signal data into the first half and the second half. A predetermined division in which the video signal data is divided into 水平 horizontal cycles and written into the left and right line memories, respectively, and the writing of the video signal data to the left line memory in the first half 周期 horizontal cycle of one horizontal cycle is completed. From the point in time, the first half of one horizontal cycle of the video signal data recorded in the left line memory and the second half of the one horizontal cycle of the video signal data written in the right line memory.
The left and right line memories are set to start reading at two horizontal periods at half the speed at the time of writing or at a speed slightly lower than half the speed at the time of writing. Control.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first aspect of the present invention is a driving circuit for a high-definition flat-panel display device which separately divides a high-definition flat-panel display device into two parts on the left and right sides and separately drives them. A left and right line memories for single time axis expansion each having a capacity capable of storing minutes, a write-side PLL for generating a write-side clock synchronized with a horizontal sync signal related to video signal data, and a horizontal sync signal Against
(1/2) Synchronizes with the pseudo horizontal synchronizing signal having a phase difference of the horizontal period, and is １ ／ of the frequency of the write-side clock, or
A read-side PLL that generates a read-side clock having a frequency slightly lower than half the frequency of the write-side clock
And a write-side clock from the write-side PLL and a read-side clock from the read-side PLL are supplied, respectively.
One horizontal cycle of the video signal data is divided into 1/1/2 of the first half and the second half.
It is divided into two horizontal periods and written into the left and right line memories, respectively.
From a predetermined point in time when writing into the left line memory for the first half of the horizontal period is completed, the first half of the video signal data recorded in the left line memory for the first half of the horizontal period And the latter half 周期 horizontal cycle of one horizontal cycle of the video signal data written to the right line memory are respectively 速度 of the writing speed, or 書 込 み of the writing speed. And a memory controller for controlling the left and right line memories so as to start reading at a speed slightly lower than the speed of the second line.

According to a second aspect of the present invention, there is provided a driving circuit for a high-definition flat panel display according to the first aspect of the present invention, in which a ramp-up component of a negative feedback voltage during a pseudo horizontal synchronizing signal period of a read-side PLL is reduced. The time constant of the low-pass filter in the read-side PLL is made longer than the original time constant, and the horizontal retrace period of the video signal data is made shorter than the original length.

[Specific Example of Embodiment of the Invention] A driving circuit of a high-definition flat panel display device according to a specific example of the embodiment of the present invention will be described below with reference to FIGS. FIG.
The same reference numerals are given to portions corresponding to FIG. 8 and FIG.

As shown in FIG. 7, the digital video signal data (digital red, green and blue signal data) V8 from the A / D converter 24 has a capacity capable of storing a half horizontal cycle of the video signal data. To the left and right line memories 41L and 41R, respectively, to perform writing and reading, respectively.
The read output from 1R is supplied to the left and right liquid crystal column drivers 28 and 27, respectively. The left and right line memories 41L and 41R have write and read address counters, respectively.

FIG. 7 shows only the left and right line memories 41L and 41R and the left and right liquid crystal column drivers 28 and 27 which constitute the left / right divided drive circuit. Therefore, a description will be given with reference to FIG. 1 showing in detail the configuration of the left / right divided drive circuit together with FIG. MPEG-2
The horizontal synchronizing signal from the decoder 21 is supplied to the write-side PLL 46 through the input terminal 43, and a write-side clock synchronized with the horizontal synchronizing signal is generated and supplied to the memory controller 45. Also, the pseudo-horizontal synchronization signal generated from the writing-side PLL 46 is supplied to the writing-side PLL 47,
In synchronization with the pseudo-horizontal synchronization signal, a read-side clock having a frequency half the frequency of the write-side clock is generated and supplied to the memory controller 45.

The memory controller 45 supplies a read enable signal and a read clock to the left and right line memories 41L and 41R in common. The memory controller 45 supplies a left write enable signal and a write clock to the left line memory 41L, and supplies a right write enable signal and a write clock to the right line memory 41R.

Next, with reference to FIG. 2, the write and read operations for the left and right line memories 41L and 41R in FIG. 1 will be described. In FIG. 2, the horizontal axis indicates time, and the vertical axis indicates write and read addresses of the left and right line memories 41L and 41R. A thin solid line indicates a change in a write address, and a thick solid line indicates a change in a read address. As shown by a thin solid line, the left half of the left line memory 41L and the right half of the right line memory 4 represent the first half and the second half of one horizontal cycle of the video signal data of the nth line.
Write to 1R sequentially. Then, the left line memory 41
L, the video signal data of the n-th line stored in the left line memory 41L from a predetermined point in time when the writing of the video signal data of the n-th line for the first half of the one horizontal cycle is completed. The first half of the horizontal period of one horizontal cycle and the second half of the video signal data of the n-th line written in the right line memory 41R in the second half of the horizontal period
The horizontal period is read out by a read clock having a frequency half of the frequency of the write clock as indicated by a thick solid line, whereby one horizontal period of the video signal data of the n-th line which is doubled in time axis is expanded. Minutes.

Next, the first and second half 水平 horizontal periods of one horizontal period of the video signal data of the (n + 1) th line are stored in the left line memory 41L and the right line memory 41R as shown by thin solid lines. Write sequentially. And
(N + 1) lines stored in the left line memory 41L from a predetermined point in time when the writing of the (n + 1) th video signal data for the first half of the one horizontal period into the left line memory 41L is completed. Eye video signal data 1
The first half horizontal cycle of the horizontal cycle and the second half horizontal cycle of the first horizontal cycle of the video signal data of the (n + 1) th line written to the right line memory 41R are used as the write clock. By reading with a read clock having a frequency half of the frequency as indicated by a thick solid line, one horizontal period of the video signal data of the (n + 1) th line that is doubled in time axis is obtained.

In this case, the read address of the right line memory 41R does not exceed the write address of the right line memory 41R.

In FIG. 2, τ is a stop period of the read address counter, and this period corresponds to a horizontal retrace period.

Next, with reference to FIG. 3, an example of a concrete circuit of the PLL applicable to the read-side (write-side) PLL 46 (47) of FIG. 1 will be described. Voltage controlled oscillator (VC
O) 55 is a coil C having one end connected to a bypass capacitor C
₃ and further through a variable capacitance diode C _V to ground. The other end of the coil L is grounded through the capacitor C _4. An input end and an output end of the inverter IV are connected to one end and the other end of the coil L, respectively. Then, a clock output terminal 56 is derived from the output terminal of the inverter IV. The oscillation frequency f of the oscillator 55 is represented by the equation shown in FIG. 3 where the inductance of the coil L is L, the capacitance of the variable capacitance diode C _V is C _V , and the capacitance of the capacitor C ₄ is C ₄ .

The clock from the voltage controlled oscillator 55 is
The clock is supplied to a clock input terminal of a 12-bit counter 50 as a frequency divider and frequency-divided. In the case of the HDTV signal progressively converted to double speed, the oscillation frequency of the oscillator 55 is set to 148.5 MHz, and
Divide the 8.5 MHz clock by 1/2200.

The output of the counter 50 is supplied to an H pulse generator (binary decode circuit) 51 for phase comparison.
When the count value of the counter 50 is -2200 to -1101, the H pulse is at a low level, and the count value is -11.
In the case of 00 to -1, the H pulse goes high.

The H pulse from the pulse generator 51 is supplied to a phase comparison circuit (transfer gate) 52, and is compared with a double-speed horizontal synchronizing signal from an input terminal 53 supplied to a gate terminal of the phase comparator 52. Is done. Then, only during the low level period of the horizontal synchronizing signal, the H pulse having the duty of 50% is passed.

The phase comparison output from the phase comparator 52 is
Gleed type low pass filter 54 is supplied to filter
The output is the variable capacitance diode C of the voltage controlled oscillator 55._V
To control the oscillation frequency. This row
The pass filter 54 is connected to the output terminal of the phase comparator 52
Densa C₁And a resistor R_FourThrough
The capacitor C of the voltage controlled oscillator 55_ThreeAnd variable
Capacitance diode C_VIs connected to the midpoint of the connection. In addition,
The output terminal of the phase comparator 52 is a resistor R_ThreeThrough
Capacitor C_TwoThrough the ground. DC voltage + 5V
Resistor R₁, R _TwoResistor divider consisting of a series circuit of
And the divided voltage is applied to a resistor R_FourOscillation through
Variable diode C of the device 55_VIs applied to This place
In this case, the output voltage of the low-pass filter 54 becomes an intermediate voltage value.
Then, the negative feedback loop of the PLL is stabilized. Immediately
That is, during the low level period of the horizontal synchronization signal, the phase comparison output waveform
The rising part comes in.

Next, the PLLs 46 and 47 in the left / right divided drive circuit of the specific example of FIG. 1 will be described. In the left-right divided drive circuit of the specific example of FIG.
It is conceivable that the LLs 46 and 47 are configured by a common PLL to generate a write clock and a read clock synchronized with the horizontal synchronization signal from the input terminal 43, respectively. In this case, the following problem occurs.

That is, when a video signal having a skew (fluctuation in the time axis) in the horizontal time axis direction is handled like a variable speed reproduction video signal from a VTR, the upper image is prevented from being bent on the screen of the video signal. To reduce the time constant of the low-pass filter in the PLL (for example, 2 to 3 μsec),
It is necessary to increase the response speed of the LL. However, doing so increases the fluctuation of the feedback voltage for the voltage-controlled oscillator during the horizontal synchronizing signal period. When the video signal data is read from 41R and 41L, the output voltage of the low-pass filter (LPF) at the center of the read video period greatly changes as shown in FIG. 5D of the PLL timing chart shown in FIG. Thus, there has been a problem that the clock frequency in the central portion of the read video period becomes unstable, and a vertical streak that interferes with the video signal occurs.

FIG. 5 will be described in association with each section of the PLL of FIG. FIG. 5A shows a phase comparison waveform (which means a waveform to be compared in phase) which is an output of the phase comparison H pulse generator 51, and FIG. 5B shows a horizontal synchronization signal from the input terminal 53. FIG. 5C shows a phase detection voltage (PLL phase detection voltage) from the phase comparator 52. FIG. 5D shows the output voltage of the low-pass filter 54. Since the time constant of the low-pass filter 54 is shortened, both the levels of the positive and negative pulses are high. 5E and 5F show the write address and read address of the left and right line memories 41L and 41R, respectively.

Therefore, in the left / right divided drive circuit of the specific example of FIG. 1, the write-side PLL 46 shifts the horizontal synchronization signal (FIG. 4A) from the input terminal 43 by (1/2) the horizontal period. A phased (late) horizontal synchronization signal (FIG. 4C) is generated and supplied to the read-side PLL 47. In this case, the left and right line memories 41L, 4L
Since the video signal data once stored in the 1R is read again from the scanning start point, there is a skew (time-axis variation) in the horizontal time-axis direction, like the variable-speed reproduction video signal from the VTR in the reading-side PLL 47. Since it is not necessary to follow the video signal at high speed, it is not necessary to shorten the time constant of the low-pass filter 54, and the time constant can be increased (for example, 20 to 30 sec). For this reason, as described with reference to FIG.
When the video signal data is read from R and 41L, as shown in FIG. 4E of the timing chart of the PLL shown in FIG. 4, the output voltage (feedback voltage) of the low-pass filter (LPF) in the central portion of the read video period fluctuates. That is, the positive and negative amplitudes become smaller, the clock frequency in the central part of the readout video period becomes stable, the stable time axis elongation is performed over the entire readout period, and the vertical streak that interferes with the video signal is reduced. There is almost no risk of occurrence.

FIG. 4 will be described in association with each section of the PLL of FIG. 4A shows a horizontal synchronizing signal from the input terminal 53, and FIG. 4B shows an H pulse generator 51 for phase comparison.
FIG. 4C shows a horizontal synchronization signal obtained by shifting (phase-shifting) (delaying) the horizontal synchronization signal of FIG. 4A by (１ ／) horizontal period. FIG. 4D shows a phase detection voltage (PLL phase detection voltage) from the phase comparator 52. FIG. 4E shows the output voltage of the low-pass filter 54. Since the time constant of the low-pass filter 54 is increased, the levels of the positive and negative pulses are considerably low. 4F and 4G show a write address and a read address of the left and right line memories 41L and 41R, respectively.

Thus, (1/1 /
2) Since the horizontal synchronizing signal shifted by the horizontal period is supplied, the horizontal blanking period in the read-side PLL 47, that is, the read clock in the so-called horizontal retrace period can be stabilized. , The horizontal video signal period can be extended by about 15 to 27% for various video signal data.

Actually, a progressive signal of 1920 × 1080 pixel standard obtained from a personal computer has a retrace period of about 4 μsec and an effective video signal period of 11 μsec. Therefore, the period of one pixel is 11 μsec / 1920. = 5.7 nsec. Therefore, the frequency of the pixel driving clock is 175 MHz
And become very high.

In this case, if the frequency of 175 MHz is divided by 4, the frequency becomes 43.75 MHz, which exceeds the maximum operating frequency of 40 MHz, which is the maximum operating frequency of a general column driver IC.

Therefore, in the left / right divided drive circuit of the specific example of FIG. 1, for example, the above-described horizontal blanking period, that is, the horizontal retrace period is set from 4 μsec to 2 μsec.
And the effective video signal period is reduced from 11μsec to 13μse
When expanded to c, the general number of pixels is 1920 × 1
This is the same as the double-speed progressive signal of the HDTV signal of the 080i broadcast standard, and the sampling clock frequency required for the double-speed progressive signal can use a display drive clock of 148.5 MHz which is twice 74.25 MHz.

Further, in the left / right divided drive circuit of the specific example of FIG. 1, the above-mentioned horizontal blanking period, that is, the horizontal retrace period can be reduced from the above-mentioned 4 μsec to 0 sec. 11μse signal period
c (dashed line in FIG. 6) to 15 μsec (thick solid line in FIG. 6), the read clock frequency is 175 MHz.
128 MHz which is 27% lower than z can be used. Therefore, unnecessary radiation (Electric & Magnetic Inte
This is a very effective measure as a countermeasure. In this case, the frequency of the read clock is slightly lower than half the frequency of the write clock. FIG.
Is a diagram similar to FIG. 2, and changes in the write addresses of the left and right line memories 41L and 41R are the same as in FIG. 2. The broken line in FIG. 6 is similar to the change in the read address of the left and right line memories 41L and 41R on the n-th line in FIG. The thick solid line in FIG. 2 indicates the change in the read address of the nth line and the (n + 1) th line of the left and right line memories 41L and 41R when the effective image period is set to 15 μsec.

[0075]

According to the first aspect of the present invention, in a driving circuit of a high-definition flat-panel display device which divides a high-definition flat-panel display device into two right and left parts and drives them separately, a half horizontal period of video signal data is used. A left and right line memories for single time axis expansion each having a capacity capable of storing minutes, a write-side PLL for generating a write-side clock synchronized with a horizontal sync signal related to video signal data, and a horizontal sync signal Against
(1/2) Synchronizes with the pseudo horizontal synchronizing signal having a phase difference of the horizontal period, and is １ ／ of the frequency of the write-side clock, or
A read-side PLL that generates a read-side clock having a frequency slightly lower than half the frequency of the write-side clock
And a write-side clock from the write-side PLL and a read-side clock from the read-side PLL are supplied, respectively.
One horizontal cycle of the video signal data is divided into 1/1/2 of the first half and the second half.
It is divided into two horizontal periods and written into the left and right line memories, respectively.
From a predetermined point in time when writing into the left line memory for the first half of the horizontal period is completed, the first half of the video signal data recorded in the left line memory for the first half of the horizontal period And the latter half 周期 horizontal cycle of one horizontal cycle of the video signal data written to the right line memory are respectively 速度 of the writing speed, or 書 込 み of the writing speed. And a memory controller for controlling the left and right line memories so as to start reading at a speed slightly lower than the speed of the second line. Therefore, each memory controller has a capacity capable of storing a half horizontal period of the video signal data. One left and right line memories can be used to generate left and right video signal data for separately driving the two divided left and right half display areas of the high definition flat panel display device. , Therefore, it becomes a low-cost, and,
Since the read-side PLL generates a read-side clock synchronized with the pseudo-horizontal synchronization signal having a phase difference of (1/2) horizontal period with respect to the horizontal synchronization signal, the PLL is provided during the horizontal blanking period on the read side. A drive circuit for a high-definition flat-panel display device can be obtained which can drive a slight ramp-up region of the feedback voltage and can perform stable time-axis expansion processing over the entire reading period.

According to the second aspect of the present invention, in the driving circuit of the high definition flat panel display according to the first aspect of the present invention, the read-side PL
The time constant of the low-pass filter in the read-side PLL is made longer than the original time constant and the horizontal retrace period of the video signal data is originally reduced so as to reduce the fluctuation component of the negative feedback voltage during the pseudo horizontal synchronization signal period of L. , The single left and right line memories each having a capacity capable of storing a half horizontal period of the video signal data are used to realize the high definition flat display device 2.
It is possible to generate left and right video signal data for separately driving the divided left and right half display areas, so that the cost is low, and the horizontal synchronization signal from the read-side PLL is (1/2). Since the read-side clock synchronized with the pseudo-horizontal synchronizing signal having the phase difference of the horizontal period is generated, P
A high-definition flat-panel display that can drive a slight LL feedback voltage fluctuation region, perform stable time-axis expansion processing throughout the readout period, and can support even higher driving frequencies. A drive circuit for the device can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a left-right divided driving circuit of a driving circuit of a high-definition flat panel display according to a specific example of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing memory write and read timings of left and right line memories of a left / right divided drive circuit of a specific example.

FIG. 3 is a circuit diagram showing a specific example of a read-side (write-side) PLL of the left / right divided drive circuit of the specific example.

FIG. 4 is a timing chart for explaining that a read-side clock of a left / right division drive circuit of a specific example is stable.

FIG. 5 is a timing chart for explaining a ramp of a read-side clock before improvement of a left / right division drive circuit of a specific example.

FIG. 6 is a timing chart in the case of extending the read period of the left / right divided memory of the left / right divided drive circuit of the specific example to the retrace period.

FIG. 7 is a block diagram illustrating a driving circuit of a high-definition flat panel display device according to a specific example of the embodiment of the present invention.

FIG. 8 is a block diagram showing a left / right division drive circuit of a conventional example.

FIG. 9 is a timing chart showing write and read timings of a left-right divided memory of a left-right divided drive circuit of a conventional example.

FIG. 10 is an exploded perspective view showing a part of a conventional plasma addressed liquid crystal display device.

FIG. 11 is a perspective view showing a part of a conventional plasma addressed liquid crystal display element (apparatus).

FIG. 12 is a perspective view showing a part of a plasma-addressed liquid crystal display element (apparatus) for explaining generation of a plasma channel in a conventional plasma-addressed liquid crystal display element (apparatus).

FIG. 13 is an explanatory diagram showing a plasma channel of a conventional plasma-addressed liquid crystal display element (apparatus) and an equivalent circuit thereof.

FIG. 14 is a block diagram showing a driving circuit of a conventional plasma addressed liquid crystal display device.

FIG. 15 is a circuit diagram showing a specific circuit of a plasma discharge driver of a drive circuit of a conventional plasma addressed liquid crystal display device.

FIG. 16 is a timing chart showing a phase relationship between write image data and a plasma discharge pulse in a driving circuit of a conventional plasma addressed liquid crystal display device.

[Explanation of symbols]

28, 27 Left and right liquid crystal column drivers, 36
Plasma address type liquid crystal display device, 41L, 41R Left and right line memories, 45 memory controller,
46, 47 Write side and read side PLL.

Claims (2)

[Claims] 1. A driving circuit for a high-definition flat-panel display device that separately divides a high-definition flat-panel display device into two parts on the left and right sides, and has a capacity capable of storing a half horizontal period of video signal data. A single left and right line memory for extending the time axis, a write PLL generating a write clock synchronized with a horizontal sync signal related to the video signal data, and (1/2) ) Synchronizing with a pseudo horizontal synchronizing signal having a phase difference of a horizontal period, generating a read-side clock having a frequency which is half of the frequency of the write-side clock or slightly lower than half of the frequency of the write-side clock. And a write-side clock from the write-side PLL and a read-side clock from the read-side PLL. The horizontal cycle is divided into the first half and the second half of the horizontal cycle, respectively, and written into the left and right line memories, respectively, and the first half of the video signal data is divided into the first half of the horizontal cycle. From the predetermined time point when the writing to the left line memory is completed, the first half of the one horizontal period of the video signal data recorded in the left line memory is written to the right line memory. The latter half 周期 horizontal cycle of one horizontal cycle of the video signal data is set to 速度 of the writing speed or slightly lower than 書 込 み of the writing speed. And a memory controller that controls the left and right line memories so as to start reading at a high speed. 2. The driving circuit for a high-definition flat-panel display device according to claim 1, wherein the read-side PLL has a reduced negative feedback voltage component in the pseudo-horizontal synchronization signal period of the read-side PLL. Wherein the time constant of the low-pass filter is longer than the original time constant and the horizontal retrace period of the video signal data is shorter than the original length.