JPS63194481A - Display using solid-state display device - Google Patents

Abstract

PURPOSE:To improve resolution at the time of enlarging by adjusting the horizontal clock frequency or the vertical clock frequency of a video signal. CONSTITUTION:At the time of displaying under an enlarged state, in a vertical clock control circuit 7, a start pulse B synchronizing with the vertical clock frequency V is oscillated in an oscillator 7a to be a pulse C modulated to a desired enlargement magnification in a pulse repetition frequency modulator 7b and outputted from a vertical shift register 5 as a clock D from a switch 7c. In a horizontal clock control circuit 8, a start pulse (b) synchronizing with a vertical clock H is oscillated in the oscillator 7a to be a pulse (c) modulated to the desired enlargement magnification in a pulse repetition frequency variable equipment 8b and outputted to a horizontal shift register 6 as a clock (d) from a switch 8c.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a display constructed using a solid-state display device such as a liquid crystal, and more specifically, a solid-state display that enlarges and displays images by adjusting the clock frequency of a video signal. Related to displays using devices.

[Prior art]

Traditionally, television displays have been
CRT is commonly used, but in recent years liquid crystal (LC)
Due to the remarkable improvement in the performance of solid-state display devices such as light-emitting diodes (LEDs) and electroluminescence (EL), these solid-state display devices have come to be used as various displays. In particular, liquid crystal displays are becoming popular in fields that could not be realized with conventional CRTs, such as small portable televisions. The horizontal scanning and vertical scanning deflections of these solid-state display devices are performed depending on the synchronized clock frequency of the video signal.

By the way, some conventional CRTs are configured to enlarge or reduce a part of the screen. In CRT, "electromagnetic deflection or electrostatic deflection is performed by swinging the electron beam, and in order to enlarge or reduce the deflection, the swing width of the electron beam is controlled by controlling the changing current. However, With this CRT, even though there is no change in the number of scanning lines, especially when enlarging, the entire scanning line interval is increased by simply adjusting the amplitude of the electron beam. Therefore, there was a problem that not only the limit of the magnification ratio was small, but also an overscan state occurred and the resolution deteriorated.

The present invention focuses on the fact that the deflection of a solid-state display device depends on the clock frequency of the video signal, and has developed a display using a solid-state display device that can improve the resolution, especially during enlargement, which cannot be obtained with a CRT. This is what we are trying to provide.

[Means for solving problems]

In order to achieve the above object, the present invention has a configuration in which display can be enlarged by adjusting the horizontal clock frequency or vertical clock frequency of a video signal.

[Effect]

According to the configuration of the present invention, a part of the screen is displayed in an enlarged state by adjusting the frequency of the horizontal clock or the frequency of the vertical clock.

〔Example〕

The present invention will be explained based on an embodiment shown in the drawings.

Figure 1 is an overall configuration diagram of an active matrix liquid crystal drive circuit, Figure 2 is a block diagram of a control circuit that controls the vertical clock frequency, Figure 3 is a block diagram of a control circuit that controls the horizontal clock frequency, and Figure 3 is a block diagram of a control circuit that controls the horizontal clock frequency. Figure 4 is a timing chart of the video signal and vertical clock in each part of Figure 2, Figure 5 is a timing chart of the video signal and horizontal clock in each part of Figure 3, and Figure 6 is a timing chart of the video signal and horizontal clock in each part of Figure 3. FIG. 7 is a timing chart of the clock shifted by the shift register.

The active matrix drive circuit shown in Figure 1 is
Tuner 2 sequentially from antenna 1 that receives the video signal
, a circuit 3 for performing video detection, etc., and a control pulse generation circuit 4 are connected, and the control pulse generation circuit 4 generates a vertical clock and a horizontal clock, outputs the vertical clock to the vertical shift register 5, and outputs the horizontal clock to the vertical shift register 5. is output to the horizontal shift register 6. A vertical clock control circuit 7 and a horizontal clock control circuit 8 are interposed between the control pulse generation circuit 4 and the vertical shift register 5 and horizontal shift register 6, respectively.

That is, as shown in FIG. 2, the vertical clock control circuit 7 includes an oscillator 7a that oscillates start and stop signals.
, a pulse number modulator 7b that enlarges and modulates the number of pulses, and a switch C and a switch C are connected in series, and the clock frequency of the video signal input from the control circuit 7 side to the switch 7C is changed from the normal state. In addition to adjusting the height and low, the timing of output to the vertical shift register 5, that is,
It is possible to synchronize.

Further, as shown in FIG. 3, the horizontal clock control circuit 8
An oscillator 8a that oscillates start and stop signals, a pulse number variable device 8b that changes the number of pulses, and a switch 8C
are connected in series to adjust the clock frequency of the video signal input to the switch 8C from the control circuit 7 side to high or low, and to synchronize the timing of the output to the horizontal shift register 6. is now possible.

The vertical shift register 5 is connected to a driver 9,
This driver 9 is connected to the gate of the solid state display device 10.

Further, the horizontal shift register 6 is connected to the circuit 3 that performs video detection, etc., and is connected to a sample-and-hold array 11 that has a video output for horizontal pixels. This driver 12 connects to the solid state display device 1.
Connected to the drain of 0.

In such a configuration, when displaying in normal size,
The video signal input to the control pulse transmitting circuit 4 through the antenna 1, tuner 2, and video detection circuit 3 is converted to a vertical clock frequency as shown in FIG. 4 (V) and FIG. 5 (H) by the control pulse transmitting circuit 4. (■) and horizontal clock frequency (H), which are input to the vertical shift register 5 and horizontal shift register 6, respectively. Then, the vertical shift register 5 outputs the signal for the scanning line to the gates of the parallel lines of the solid-state display device 10 in synchronization with the scanning, and
While turning on and off the horizontal shift register 6, the sample and hold circuit 11 has a video output corresponding to the number of horizontal pixels.
It is input as an input timing signal and outputs a video signal for horizontal pixels, and this video signal is multiplied by N to the capacitance of the liquid crystal by turning on and off the TPT of the solid-state display device 10 using the line gate signal, and is stored in this capacitance. The amount of light transmitted through the liquid crystal is controlled by the applied voltage, and an image is displayed on the display screen.

Next, when displaying in an enlarged state, the vertical clock frequency (V) generated by the control pulse generation circuit 4 (FIG. 4 (V)) and the horizontal clock frequency (H) (FIG. 5 (
H)) are the switches 7 of the vertical clock control circuit 7, respectively.
C, is input to the switch 8C of the horizontal clock control circuit 8. During this time, the vertical clock control circuit 7 generates a start pulse (B) synchronized with the vertical clock frequency (V) (Fig.
) is oscillated by the oscillator 7a, and the pulse number modulator 7b
(C) (Fig. 4)
C)), and the clock (D) (fourth
It will be output to the vertical shift register 5 as shown in FIG. Therefore, the same signal (1/2H) is output from the vertical shift register 5 to the solid-state display device 10 on multiple horizontal lines as shown in FIG. 7(b), that is, the same signal is output multiple times. written (2 in the example)
The portion output multiple times becomes the enlarged portion, and the entire image is enlarged in the vertical direction according to the frequency (1.5 times in the case of FIG. 4). On the other hand, the horizontal clock control circuit 8 generates a start pulse (b) (Fig. 5 (b)) synchronized with the vertical clock (H) (Fig. 5 (H)).
) is oscillated by the oscillator 7a, and the pulse number variable device 8b
Pulse (C) modulated to the desired magnification factor (Fig. 5 (
c)), and the clock (d) (fifth
(d)) and is output to the horizontal shift register 6. Therefore, the same signal is output from the horizontal shift register 6 to the solid-state display device 10 across multiple vertical lines, and the portion spanning across these multiple lines becomes an enlarged portion. The entire image is enlarged in the horizontal direction (1.5 times in the case of FIG. 5).

At this time, which part of the display screen is to be enlarged is determined by the positions of the vertical start pulse (2) and the horizontal start pulse (H). That is, in order to enlarge the part surrounded by the broken line in Fig. 6(a) as shown in Fig. 6(b), for example, the enlargement rate should be set to 1.
．． If multiplied by 5, the vertical and horizontal start pulses will be 25%.
This can be done by delaying. In other words, the frequency of double writing is adjusted according to the magnification ratio.

Note that in the above embodiment, the clock frequency and the start pulse are synchronized, but they do not have to be synchronized, but in this case, the same signals will overlap,
This is not practical because the images overlap on the display screen.

Further, in the above embodiment, only the case of enlargement was described, but it goes without saying that it can also be reduced by adjusting the clock frequency.

In addition, in the above embodiment, increasing the clock frequency increases the clock frequency and decreasing the clock frequency decreases the clock frequency, but conversely, increasing the clock frequency causes the clock frequency to decrease, and lowering the clock frequency decreases the clock frequency. It can also be configured as follows.

Further, although a liquid crystal display device is shown as a solid state display device, it may be an LED, an EL, etc., and any solid state display device is sufficient.

Note that in the above embodiment, the clocks for the normal screen and the enlarged screen are switched by a switch, but the same operation is possible with the bus modulator 7b and the pulse number variable device 8b, and the configuration does not necessarily require switching by the switch 8C. good.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to improve the magnification rate with a simple circuit that adjusts the clock frequency, and it is also possible to obtain excellent resolution during magnification.

[Brief explanation of the drawing]

The drawings show an embodiment of a display using a solid-state display device according to the present invention, and FIG. 1 is an overall configuration diagram of an active matrix type liquid crystal drive circuit;
Figure 2 is a block diagram of a control circuit that controls the vertical clock frequency, Figure 3 is a block diagram of a control circuit that controls the horizontal clock frequency, and Figure 4 shows the relationship between the video signal and vertical clock in each part of Figure 2. Timing chart, Figure 5 is a timing chart of the video signal and horizontal clock in each part of Figure 3, Figure 6 is an explanatory diagram of the operation when determining the enlarged range on the screen by the start pulse, Figure 7 is the shift 3 is a timing chart of a horizontal clock shifted by a register. (Explanation of symbols for main parts of the drawing) 7. Vertical clock control circuit 8. Horizontal clock control circuit 10. Solid state display device

Claims (1)

[Claims] A display using a solid-state display device, characterized in that display can be enlarged by adjusting the horizontal clock frequency or vertical clock frequency of a video signal.