JPH07110669A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To switch a display method to a method matching the image that video signals show when plural video signals are displayed on a liquid crystal panel having a specific number of pixels. CONSTITUTION:A switching circuit 20 is switched between a character system display mode and a natural image system display mode through the operation of a key input means, and a control signal i1 indicating the switched mode is supplied to a panel control circuit 17. The panel control circuit 17 generates a control pulse group consisting of clock pulses for an X driver 22, which are controlled in cycle and timing on the basis of the control signal e1 from a PLL 12 and the control signal i1 from the switching circuit 20, and a start pulse, and supplies it as a control pulse signal g1 to the X driver 22 of the liquid crystal panel 21. Consequently, when the video signals are displayed on the liquid crystal panel having the specific number of pixels, the method can be switched to the display method matching the image that the video signals show.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of displaying a plurality of different video signals on a liquid crystal panel having a specific number of pixels, and in particular, a display method suitable for the type of the video signal can be switched and displayed. The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, due to the rapid spread of personal computers, the demand for liquid crystal display devices for displaying an output screen of a personal computer is increasing, and both a video signal of a television broadcast and an output screen of the personal computer. The number of liquid crystal display devices capable of displaying is also increasing. In this type of liquid crystal display device, C
Compared to the RT method, the depth is smaller, and the one with excellent focus performance and convergence performance is becoming popular.
If the CRT method is approached in terms of price, it may become the mainstream.

FIG. 3 is a block diagram showing such a conventional video display device.

In FIG. 3, reference numeral 50 is a personal computer, and the personal computer 50 outputs an analog video signal a5 of an output screen, a vertical synchronizing signal b5 and a horizontal synchronizing signal c5, respectively, to an input terminal 5 of a liquid crystal display device 51.
Supply to 2, 53, 54.

Next, the liquid crystal display device 51 will be described.

A phase locked loop circuit (hereinafter referred to as a PLL circuit) 55 of the liquid crystal display device 51 includes input terminals 53 and 54.
Control signals d5 and e5 synchronized with the vertical synchronizing signal b5 and the horizontal synchronizing signal c5 from the drive circuit 56, respectively.
And to the panel control circuit 57.

The drive circuit 56 converts the video signal a5 from the input terminal 52 into a video signal f5 having a drive voltage waveform based on the control signal d5 from the PLL circuit 52, and the liquid crystal panel 6
1 to the X driver 62.

The panel control circuit 57 generates a control pulse group consisting of a clock pulse and a start pulse for the X driver 62 of the liquid crystal panel 61 on the basis of the control signal e5 from the PLL circuit 52, and the liquid crystal as the control pulse signal g5. The control pulse group including the clock pulse and the start pulse for the Y driver 62 is generated while being supplied to the X driver 62 of the panel 61, and the control pulse signal h5 is Y
Supply to the driver 63.

The X driver 62 extracts a video signal of a pixel in the horizontal direction from the video signal f5 from the drive circuit 56 based on the control pulse signal g5 from the panel control circuit 57 and samples it. The video signal of the pixel is held for one horizontal scanning period and output to the plurality of signal lines of the display unit 64.

The Y driver 63 sequentially outputs an ON signal to the plurality of scanning lines of the display section 64 for each horizontal scanning period based on the control pulse signal h5 from the panel control circuit 57.

The video signal from the X driver 62 is written in the pixel electrode of the signal line turned on by the Y driver 63 in the display section 64. As a result, a video based on the video signal f5 is displayed on the display unit 64.

FIG. 4 is a block diagram showing the liquid crystal panel 61 of FIG. 3 in more detail.

In FIG. 4, the video signal f5 shown in FIG. 3 is guided to the input terminal 71. A clock pulse signal g51 and a start pulse signal g52 corresponding to the control pulse signal g5 shown in FIG. 3 are led to the input terminals 72 and 73, respectively. The input terminals 74 and 75 have
A clock pulse signal h51 corresponding to the control pulse signal h5 of FIG. 3 and a start pulse signal h52 are respectively guided.

The clock pulse signal g51 and the start pulse signal g52 guided to the input terminals 72 and 73 are supplied to the shift register 76. The shift register 76 and a sample hold circuit 77 described later are equivalent to the X driver 62 of FIG.
Is equivalent to. The shift register 76 is reset at the rising timing of the start pulse of one horizontal scanning period (hereinafter referred to as 1H) in the start pulse signal g52, and outputs an ON signal in synchronization with the clock pulse signal h51 to output wirings 761, 762 ... 76m ( (m is several hundreds to several thousands) and sequentially supplied to the sample hold circuit 77. As a result, the sample and hold circuit 77 is connected to the input terminal 71.
The video signal f5 from the pixel is shifted from left to right by one stage, sampled and held, and the video signals of the held pixels are output to the signal lines X1, X2 ... Xm, respectively.

The clock pulse signal h51 and the start pulse signal h52 guided to the input terminals 74 and 75 are supplied to the shift register 78. The shift register 78 is shown in FIG.
Corresponding to the Y driver 63, and is reset at the timing of the rising edge of the start pulse in one vertical scanning period (hereinafter referred to as 1V) in the start pulse signal h52, and is synchronized with the clock pulse signal h51 of 1H cycle to scan line Y1. , Y2 ... Yn (n is about 1,000), the ON signal is sequentially output for each horizontal scanning period.

The display section 64 has signal lines X1, X2 ... X.
m and scanning lines Y1, Y2 ... Yn, and a thin film transistor (hereinafter referred to as a TFT) 81 is provided at each intersection, and the TFT 81 has a drain D.
, Xm are connected to the signal lines X1, X2, ... Xm, the scanning lines Y1, Y2, ... TFT8
When the ON signal is supplied from the scanning lines Y1, Y2, ..., Yn, No. 1 writes the video signals from the signal lines X1, X2 ,. As a result, the video signal f5 is displayed on the display unit 64.

Here, the NTSC system with an aspect ratio of 4: 3 is used for television broadcasting in Japan, and in the video display device shown in FIGS. 3 and 4,
When both the display of a personal computer output and the display of a television image are made compatible, the number of pixels is selected so that the image signal of an ordinary television broadcast such as the NTSC system can be displayed in detail. On the other hand, when displaying a video signal of a personal computer, it is sufficient that the number of pixels is smaller than when displaying a television video signal. For example, 8N to display personal computer output
Although the number of pixels (N is a natural number) is sufficient, the number of pixels of 9N is required to display a television image. The display example will be described below by taking the case where the number of pixels of 9N is required as an example.

First, a first display example will be described with reference to FIGS. 5 and 6.

In FIG. 5, (a) shows an image shown by a graphic 83 on a screen 81 composed of 8N horizontal pixels (N is a natural number). ), The case in which the aspect ratio is the same and the number of pixels in the horizontal direction must be displayed on the screen 82 of 9N is described.

FIG. 6 is a timing chart showing such a first display method, FIG. 6 (a) shows the video signal f5, FIG. 6 (b) shows the clock pulse signal g51 of the X driver 62, FIG. 6C shows the displayed video signal.

When the video signal f5 is a screen composed of characters, as shown in FIG. 6 (a), a pulse having a sharp edge such that the level of adjacent pixels suddenly changes from white to black Signal. The clock pulse signal g51 for sampling the input video signal f5 is shown in FIG.
As shown in (b), it is not synchronized with the pixel of the video signal f5. In such a case, the clock pulse signal g51 shown in FIG. 6 (b) may coincide with the pixel transition of the video signal f5 shown by T1 in the figure.
As shown by the broken line in FIG. 6 (c), in the pixel with No. 4, the left pixel 2 and the right pixel 3 are intermittently replaced by black or white, the brightness is not stable, and when viewed on the screen. The edges became jittery, making it very difficult to see.

In order to prevent such a problem, a display example as shown in FIG. 7 may be used.

FIG. 7 shows a case where a video signal is displayed by sampling with a clock pulse g51 which matches the video signal of the personal computer to be displayed, and a screen having 8N horizontal pixels (N is a natural number). The image 96 displayed at 91 is displayed in a region 93 having a width of 8N pixels at the center of a screen 92 having the same aspect ratio in the horizontal direction and a pixel number of 9N. As a result, the area 9
The left and right areas 94 and 95 of 3 are blank areas in which no image is displayed. Here, the left end of the area 93 of the screen 82 is the position where the start pulse g52 rises. In this method, the aspect ratio of the image 97 displayed on the screen 92 is longer than the aspect ratio of the graphic 96 in the image 91.

FIG. 8 is a timing chart in the case of such a display example, and FIG. 8A shows the video signal f5.
FIG. 8B shows the clock pulse signal h51.
(C) shows a video signal to be displayed.

In the video signal f5 shown in FIG. 8 (a), the color level of the adjacent pixel is suddenly changed from white to black. Since the clock pulse signal g51 for sampling the input video signal f5 is synchronized with the pixels of the video signal f5 as shown in FIG. 8B, the pixel transition is not sampled, and 8 (c), the signal line 7
The video signal displayed at 9 is in a stable state. However, as shown in FIG. 7, the aspect ratio of the image 97 displayed on the screen 92 is longer than the aspect ratio of the image 96 on the screen 91, which is not suitable for displaying a character-based image.

Therefore, another display example can be considered. A display example will be described with reference to FIG.

FIG. 9 is a modification of the display examples of FIGS. 5 and 6, in which the pixel 2 or 3 portion shown by the dotted line in FIG. 6C is interpolated by the video signal 100 of the average level of the adjacent pixels. It is the one. This will prevent jitter and provide a normal aspect ratio image,
In this case, the continuity of circles, diagonal lines, etc. is lost. Therefore, it is not suitable for natural images such as landscapes and people.

[0028]

In the above-described liquid crystal display device, when a video signal suitable for the first number of pixels is displayed on the liquid crystal panel of the second different number of pixels, jitter or an aspect ratio is generated. The ratio changed, and the text-based screen became unnatural. Further, when pixels are interpolated and displayed on a liquid crystal panel, the continuity of circles, diagonal lines, etc. is lost, making it unsuitable for natural image-based images.

The present invention eliminates the above problems and provides a liquid crystal display device capable of switching to a display method suitable for an input video signal when displaying a plurality of video signals on a liquid crystal panel having a specific number of pixels. With the goal.

[0030]

A liquid crystal display device according to the present invention comprises a liquid crystal display panel comprising a plurality of pixels, each of which is connected with a liquid crystal element at each intersection of a plurality of scanning lines and a plurality of signal lines. A Y driver that sequentially supplies a scanning signal to a scanning line, first and second video signal sources, and video signals from the first and second video signal sources are sampled and supplied to the plurality of signal lines. X driver
First and second clock signals suitable for sampling the first and second video signals, respectively, and a first defining a display start position of the first and second video signals on the liquid crystal display panel. , A signal generating means capable of generating a second start pulse, and the liquid crystal display panel with the first and second signals.
Mode selection means for selecting which of the video signals to display, and the signal generation means in response to the selection operation of the mode selection means, and the first video signal display mode in the first video signal display mode. Control means for supplying the X clock signal and the first start pulse to the X driver, and supplying the second clock signal and the second start pulse to the X driver in the second video signal display mode. And is provided.

[0031]

According to such a configuration, when displaying a television image or a computer output on a liquid crystal panel having a fixed number of pixels, it is possible to display by using a sampling clock or an image processing circuit suitable for the image. Therefore, when displaying a plurality of video signals, selection display can be performed in any display form.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing a liquid crystal module of a liquid crystal display device according to the present invention.

In FIG. 1, reference numeral 10 is a video signal source in a personal computer or a television receiver, and an analog video signal a1 is supplied from this video signal source.
The vertical synchronizing signal b1 and the horizontal synchronizing signal c1 are supplied to the input terminals 12, 13, 14 of the liquid crystal display device 11, respectively.

Next, the liquid crystal display device 11 will be described. The display unit 24 has, for example, the number of pixels (9N in the above-mentioned example) that is compatible with a television video signal that requires a large number of pixels.

On the other hand, the PLL circuit 12 of the liquid crystal display device 11
Generates control signals d1 and e1 synchronized with the vertical synchronizing signal b1 and the horizontal synchronizing signal c1 from the input terminals 13 and 14, and supplies them to the drive circuit 16 and the panel control circuit 17.

The drive circuit 16 converts the video signal a1 from the input terminal 12 into a video signal f1 having a drive voltage waveform based on the control signal d1 from the PLL circuit 12, and the liquid crystal panel 2
1 to the X driver 22.

The switching circuit 20 is switched between a character-based display mode for displaying a personal computer output and a natural image-based display mode for displaying a television image by operating the key input means, and a control showing the switched mode. Signal i
1 is supplied to the panel control circuit 17.

The panel control circuit 17 controls the control signal e1 from the PLL circuit 12 and the control signal i1 from the switching circuit 20.
A control pulse group consisting of a clock pulse and a start pulse for the X driver 22 whose cycle and timing are controlled based on the above is generated and supplied to the X driver 22 of the liquid crystal panel 21 as a control pulse signal g1, and also from the PLL circuit 12. A control pulse group including a clock pulse and a start pulse for the Y driver 23 is generated on the basis of the control signal e1 of the Y driver 23 as the control pulse signal h1.
Supply to.

The X driver 22 extracts the video signal of the pixel in the horizontal direction from the video signal f1 from the drive circuit 16 based on the control pulse signal g1 from the panel control circuit 17 and samples it. The video signal of the pixel is held for one horizontal scanning period and output to the signal line of the display unit 24, respectively.

The Y driver 23 sequentially outputs an ON signal to the plurality of scanning lines of the display section 24 for each horizontal scanning period based on the control pulse signal g1 from the panel control circuit 17.

The video signal from the X driver 22 is written in the liquid crystal pixel of the scanning line turned on by the Y driver 23 in the display section 24. As a result, an image based on the image signal f1 is displayed on the display unit 24.

The operation of such an embodiment will be described below.

First, in the case of displaying a natural image type screen, the user operates the key input means to switch the switching circuit to the natural image type display mode. As a result, the switching circuit 2
0 supplies the control signal i1 indicating the natural image display mode to the panel control circuit 17. As a result, the panel control circuit 17 generates and controls a control pulse group including a clock pulse having the same period as the period of one pixel of the television video signal and a start pulse for starting display from the left corner of the display section 24. The pulse signal g1 is supplied to the X driver. As a result, a high-definition image can be displayed on the entire screen as shown in FIG.

Next, when displaying a character-based image such as a personal computer output, the user switches the switching circuit 20 to the character-based display mode by operating the key input means. As a result, the switching circuit 20 supplies the control signal i1 indicating the character display mode to the panel control circuit 17. As a result, the panel control circuit 17 is switched and set to a mode for sampling with a clock signal suitable for a character-based video signal, and a blank portion is provided from the left corner of the display unit 24 as shown in FIG. A control pulse group consisting of a start pulse for starting and a control pulse signal g
It is supplied to the X driver 22 as 1. As a result, FIG.
The image can be displayed on the screen with the aspect ratio as shown in (b). In this case, the horizontal direction of the image is compressed, but no jitter is generated, so that an unnatural impression is not given.

As described above, in this embodiment, when a plurality of video signals are displayed on the liquid crystal panel having a certain number of pixels, the display method can be switched to the video indicated by the video signals, so that the character system and the natural system are improved. It is possible to give a high impression to the user with both images of the image system.

FIG. 2 is a block diagram showing a liquid crystal display device of a second embodiment according to the present invention. The same constituent elements as those in FIG. 1 are designated by the same reference numerals and the description thereof is omitted.

In FIG. 2, the difference of this embodiment is that an interpolating circuit 32 is provided in front of the driving circuit 16 and a switching circuit 33 is provided.
That is, the video signal a1 is interpolated based on the switching signal j1.

The switching circuit 33 is for switching whether or not to perform sampling of the clock signal synchronized with the pixels of the video signal in the natural image display mode and interpolation of the video signal by operating the key input means. The control signals i1 and j1 corresponding to each mode are supplied to the panel control circuit 17 and the interpolation circuit 32, respectively.

The interpolation circuit 32 receives the input signal from the input terminal 12 when the control signal j1 from the switching circuit 33 indicates the character display mode.
Is converted into a video signal of the average level of adjacent pixels before and after the position where the transition of the pixel coincides with the rising edge of the clock pulse signal h51, and is guided to the drive circuit 16. Further, the control signal j1 from the switching circuit 33
Indicates the natural image display mode, the video signal a1 from the input terminal 12 is not interpolated and is directly driven by the drive circuit 1.
Guided to 6.

The other structure is the same as that of the embodiment shown in FIG.

When displaying a character-based screen, the user operates the key input means to switch the switching circuit 33 to the character-based display mode. As a result, the switching circuit 33 supplies the control signals i1 and j1 indicating the character display mode to the panel control circuit 17 and the interpolation circuit 32, respectively.

As a result, the interpolation circuit 32 operates in the input terminal 1
The video signal a1 from 2 is output before and after the position where the transition of the pixel coincides with the rising edge of the clock pulse signal h51 as the video signal of the average level of the adjacent pixels. As a result, the image in which the jitter shown in FIG. 9C is prevented can be displayed on the screen. On the other hand, since the sampling clock has the same cycle as in the natural image display mode, the aspect ratio does not shrink.

When displaying a natural image type screen, the user operates the key input means to switch the switching circuit 33 to the natural image type display mode. As a result, the switching circuit 33
Supplies the control signals i1 and j1 indicating the natural image display mode to the panel control circuit 17 and the interpolation circuit 32, respectively. As a result, the panel control circuit 17 performs the same operation as in the natural image display mode of the embodiment shown in FIG. At this time, the interpolation circuit 32 guides the video signal a1 from the input terminal 12 to the drive circuit 16 as it is.

According to such an embodiment, the natural image display mode has the same effect as that of the embodiment of FIG.
When displaying a character screen, input video signal a
It is possible to prevent the jitter at the position where the transition of the pixel 1 and the rising edge of the clock pulse signal h51 coincide with each other. Although the continuity of circles, diagonal lines, etc. in the character screen is inferior to that in the case of FIG. 1, there is an effect that a large aspect ratio of the screen can be displayed.

Although the embodiments of FIGS. 1 and 2 are applied to the liquid crystal display device for displaying both the video signal of the television broadcast and the output screen of the personal computer,
It may be applied to a liquid crystal display device for displaying output screens of a plurality of types of personal computers.

[0057]

According to the present invention, when displaying a plurality of video signals on a liquid crystal panel having a specific number of pixels, it is possible to switch to a display method suitable for the video indicated by the video signals. It is possible to give a high impression to users with various images such as natural images.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 3 is a block diagram showing a conventional video display device.

FIG. 4 is a block diagram showing the liquid crystal panel of FIG. 3 in more detail.

FIG. 5 is an explanatory diagram showing a first display method of a video signal in a conventional video display device.

FIG. 6 is a timing chart showing a first display method of a video signal in a conventional video display device.

FIG. 7 is an explanatory diagram showing a second display method of a video signal in a conventional video display device.

FIG. 8 is a timing chart showing a second display method of a video signal in a conventional video display device.

FIG. 9 is a timing chart showing a third display method of a video signal in a conventional video display device.

[Explanation of symbols]

 11 liquid crystal display device 12 PLL circuit 16 drive circuit 17 control circuit 21 liquid crystal panel 22 X driver 23 Y driver 24 display unit

Claims (2)

[Claims] 1. A liquid crystal display panel comprising a plurality of pixels each having a liquid crystal element coupled to each intersection of a plurality of scanning lines and a plurality of signal lines, and a Y driver for sequentially supplying scanning signals to the scanning lines. A first and second video signal source, an X driver for sampling the video signals from the first and second video signal sources and supplying the plurality of signal lines to the plurality of signal lines, First and second clock signals suitable for sampling video signals, and first and second start pulses for defining display start positions of the first and second video signals on the liquid crystal display panel are provided. A signal generating means capable of generating, a mode selecting means for selecting which of the first and second video signals is to be displayed on the liquid crystal display panel, and in response to a selection operation of the mode selecting means. Previous Controlling the signal generating means, supplying the first clock signal and the first start pulse to the X driver in the first video signal display mode, and the second clock signal in the second video signal display mode. The clock signal and the second start pulse are added to the X
A liquid crystal display device comprising: a control unit adapted to supply to a driver. 2. A liquid crystal display panel comprising a plurality of pixels each having a liquid crystal element coupled to each intersection of a plurality of scanning lines and a plurality of signal lines, and a Y driver for sequentially supplying a scanning signal to the scanning lines. A first and second video signal source, an X driver for supplying a video signal to the plurality of signal lines, and a first video signal from the first video signal source for supply to the X driver And the video signal from the second signal source is interpolated and supplied to the X driver.
A signal processing circuit capable of executing the signal, a mode selection unit for selecting which of the first and second video signals is to be displayed on the liquid crystal display panel, and a selection operation of the mode selection unit. In response to the above, in the first video signal display mode, the signal by the first processing is supplied to the X driver, and in the second video signal display mode, the signal by the second processing is supplied to the X driver. A liquid crystal display device comprising: switching means for switching to supply.