JPH06186925A - Driving circuit for display device - Google Patents

Abstract

PURPOSE:To provide a display device having a signal electrode driving circuit capable of accurately supplying a video signal to respective pixels. CONSTITUTION:This device is constituted so that the clear OA picture is obtained by that first of all, a switching signal CON with a 'High' level and a video pixel signal V with a 'Low' level are imparted to a logical gate circuit 3 constituted of all OR circuits G1-Gn and all AND circuits Fl-Fn in one horizontal scanning interval, and respective video pixel signals V'i are initialized to the 'Low' level, and then, the switch signal CON with the 'Low' level and the video pixel signal V with the 'High' level are imparted, and the switch signal COFF is synchronized with the pixel sampling pulse Si of the (i)th pixel to be displayed, and respective video pixel signals V'i with the 'High' level are held surely only to sampling capacitors Ci, and the video pixel signals with the 'Low' level as it is are held to other sampling capacitors. In addition, it is possible that the display is switched to the AV picture display easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit of a matrix type display device such as a liquid crystal display device, an electroluminescence display, a plasma display, etc., and particularly to a signal electrode drive circuit.

[0002]

2. Description of the Related Art First, an equivalent circuit diagram of a display panel 8 in an active matrix type liquid crystal display device 4 and a block diagram of a driving circuit in the periphery thereof are shown in FIG. 4 and will be described with reference to FIG.

Active matrix type liquid crystal display device 4
Is a device that provides an active element such as a thin film transistor 9 at each intersection of the matrix to control the voltage applied to the liquid crystal for display, and displays a moving image (hereinafter referred to as “AV image”) in a small color television or a notebook. It is applied as a display device for displaying a still image (hereinafter referred to as “OA image”) on a book personal computer.

The display panel 8 has a structure in which a liquid crystal is sandwiched between two glasses, and an XY matrix electrode is formed on one glass and a common electrode is formed on the other glass. A plurality of signal electrodes 10 are arranged in parallel as conducting wire electrodes arranged in the vertical direction. Similarly, a plurality of scan electrodes 11 are arranged in parallel as conductor electrodes arranged in the horizontal direction.

The thin film transistor 9 is provided at the intersection of each signal electrode 10 and each scanning electrode 11 and has its gate g.
Is connected to the scanning electrode 11, and its source s is connected to the signal electrode 10. Each pixel electrode 12 is connected to the drain d of the thin film transistor 9. The thin film transistor 9 receives a signal "Hi" from the scanning electrode 11 when it enters the gate g.
When the gh "level is reached, the source s and the drain d are brought into a conductive state, and a voltage based on the video signal input from the signal electrode 10 to the source s is applied to the pixel electrode 12 to change the light transmittance of the liquid crystal layer. The image is displayed.

The scan electrode drive circuit 5 outputs a "High" level signal to one scan electrode 11 and a "Low" level signal to the other scan electrodes 11 during one horizontal scanning period. The scanning electrodes 11 that output a "High" level signal are sequentially switched from above at regular intervals. Thin film transistor 9 connected to the same one scan electrode 11
A high level is simultaneously input to the gates g of the above, and the sources s and the drains d of the thin film transistors 9 are electrically connected.

The signal electrode driving circuit 6 gives a video pixel signal having a voltage amplitude corresponding to the shading of display of each pixel to the signal electrode 10 connected to each pixel. Control circuit 7
Controls the operations of the scan electrode drive circuit 5 and the signal electrode drive circuit 6.

FIG. 5 is a circuit diagram of a conventional signal electrode drive circuit 6.
6 and its drive waveform is shown in FIG. The signal electrode drive circuit 6 shown in FIG. 5 is for full gradation display. Therefore, as shown in FIG. 6, the video signal V input to the signal electrode drive circuit 6 has a continuous value.

The sample and hold circuit section 1 is composed of a plurality of sample and hold circuits provided for each signal electrode 10 one by one. i-th (i is a natural number less than or equal to n. The following subscript i is equal to this i)
The set of sample and hold circuits shown in FIG. 3 is composed of a sampling switch Ai, a sampling capacitor Ci, a hold switch Bi and a hold capacitor Di.

In the sampling switch Ai or the hold switch Bi formed of MOS transistors, the pixel sampling pulse Si and the line switch signal T are input to the gate g thereof, and the pixel sampling pulse Si and the line switch signal T are "High".
The switches Ai and Bi are turned on when the level becomes "h", and are turned off when the pixel sampling pulse Si and the line switch signal T become "Low" level.

The shift register circuit 2, based on the shift pulse CK shown in FIG. 6 (a) inputted from the terminal t2,
By sequentially shifting the horizontal synchronizing pulse S as shown in FIG. 6 (b) supplied from the terminal t1, it is normally "Lo".
Pixel sampling pulses S1, S2, S3, ... A1, A2, A3, ..., An
To the gate g.

Video signal V input through terminal t5
Is the video pixel signals V1 and V2 as shown in FIG.
, V3, ..., Vn (n is the number of pixels on one scanning line. The following subscript n is equal to this n) are sequentially arranged on the time axis at regular intervals. It is supplied to the source s of the switch Ai.

The drain d of the sampling switch Ai is connected to the source s of the hold switch Bi. One electrode of the sampling capacitor Ci is connected to the connecting portion of the sampling switch Ai and the hold switch Bi, and the other electrode is grounded. The drain d of the hold switch Bi is connected to the input side electrode of the output buffer circuit Ei. One electrode of the hold capacitor Di is connected to the connection between the hold switch Bi and the output buffer circuit Ei, and the other electrode is grounded.

When the i-th pixel sampling pulse Si goes to "High" level in order, only the sampling switch Ai is turned on for a certain period, so that the video signal V during that period is converted into the video pixel signal V'i and the sampling capacitor Ci is used. Stored in. In this way, the video signal V for one scanning line is time-divided, and the video pixel signal V′1
, V'2, V'3, ..., V'n are stored in the sampling capacitors C1, C2, C3 ,.

Thereafter, terminals L1, L2, L3, ..., Ln
, The line switch signal T, which is normally at "Low" level, changes to "High" level for a certain period, and all hold switches B1, B2, B3, ..., Bn are simultaneously turned on for a certain period, and the sampling capacitor C1 is turned on. ,
The video pixel signals V'1, V'2, V'3, ..., V'n stored in C2, C3, ..., Cn are transferred to the hold capacitors D1, D2, D3 ,. It

Each output buffer circuit E1, E2, E3,
, En are video pixel signals V'1, V'2, V'3, ..., V'n held in each of the hold capacitors D1, D2, D3, ..., Dn of the sample hold circuit section 1.
Are efficiently transmitted to the signal electrode 10 as video pixel signals V1, V2, V3, ..., Vn.

With the circuit as described above, the video pixel signals V1, V2 having amplitudes corresponding to the shading of the display of each pixel,
, Vn are applied to the signal electrode 10.

In the above-described display device for full gradation display, when one character is displayed in two colors by the video signal V output from a computer or the like, the character is represented by several dots. Specifically, a dot that is a constituent part of a character is represented as "white" by a pixel having high brightness, and a dot that is a constituent part of the background is represented as "black" by a pixel having low brightness. The "High" level voltage VH is applied to the pixel electrode 12 of the pixel forming the character, and the video signal has a waveform like the video signal Va shown in FIG. 6 (h).

The video signal Va is "High" for a certain period.
The signal voltage VH at the time Ti at which the voltage rises to the level
In order to be input only to the designated i-th pixel, the i-th signal electrode 10 which supplies the video signal Va to the pixel electrode 12 of that pixel is accurately designated.
The rising time Ti of the pixel sampling pulse Si supplied by the shift register circuit 2 so that the sampling switch Ai of the sample-hold circuit unit 1 connected to the th signal electrode 10 is turned on for a certain time from the time Ti.
'Is made to coincide with the time Ti at which the video signal Va rises to the "High" level for a certain period.

[0020]

However, no matter how the electronic circuit is assembled, there is always a delay in signal transmission, so that the rising time T of the pixel sampling pulse Si is
It is impossible to completely match i'and time Ti at which the video signal Va rises to the "High" level for a certain period. For example, if the video signal Va is delayed like the video signal Vb shown in FIG. 6 (i), it is i-th and (i + 1).
At the rising times Ti 'and T (i + 1)' of the th pixel sampling pulse Si, S (i + 1), the video signal Vb
Has a "High" level signal voltage VH, the "High" level voltage VH is applied to the pixel electrodes 12 of both of these pixels.

Further, the video signal V usually passes through the amplifier circuit / buffer circuit etc. before being input to the signal electrode drive circuit 6, but when passing through these circuits, after passing through the frequency band, the video signal V is passed. The signal is distorted. For example, the video signal Va applied to the i-th pixel electrode 12 described above.
May be distorted like the video signal Vc shown in FIG. 6 (j). Therefore, the rising time Ti 'of the pixel sampling pulse Si and the video signal Va are constant for a certain period "
Even if it is possible to completely match the time Ti that rises to the “High” level, the i-th and (i +
1) At the rising times Ti 'and T (i + 1)' of the first pixel sampling pulse Si, S (i + 1), the video signal V
Since b has the "High" level signal voltage VH, the "High" level voltage VH is applied to the pixel electrodes 12 of both these pixels. Therefore, when the OA image is displayed, the positions of the pixels forming the characters or the like are inevitably shifted, or the characters or the like displayed on a plurality of pixels are blurred.

It is an object of the present invention to solve the above problem and to provide a display device having a signal electrode drive circuit capable of accurately supplying a video signal to each pixel.

[0023]

In order to achieve the above object, the drive circuit of the display device of the present invention inputs a signal voltage corresponding to the light and shade of the display of the display pixel to each signal electrode of the matrix type display device. Therefore, a plurality of sample and hold circuits corresponding to the number of signal electrodes having a switch means and a capacitor for extracting a voltage corresponding to a pixel to be displayed among input signals in which the display signals of the respective pixels are arranged in time series are provided. ,
First switch signal supply means for generating a first switch signal to be applied to the switch means for sequentially performing the sampling operation of the sample hold circuit, and for outputting the voltage held by the sample hold circuit to the signal electrode. An output circuit, wherein a second switch signal for instructing to turn on only during a period including a video pixel signal of a display pixel to be displayed in the input video signal and off during another period Gate means for selecting whether to output or inhibit the first switch signal, and a mode for turning on all the switch means of the sample and hold circuit regardless of the output of the gate means to reset the sample and hold circuit. When,
And a mode for passing the output of the gate means to give to the switch means for operating the sample hold circuit.

[0024]

With this structure, by turning on all the switch means of the sample and hold circuit within one horizontal scanning period, the same "Low" level signal voltage can be sampled to all the capacitors of the sample and hold circuit. .

Furthermore, since the gate means outputs the first switch signal only to the pixel to be displayed and prohibits the output to the other pixels, the capacitor of the sample and hold circuit corresponding to the pixel to be displayed is "High". It is possible to sample the signal voltage of the level and keep the signal voltage of the “Low” level held in the capacitors of the sample hold circuits corresponding to other pixels. Therefore, when an OA image is displayed, good display can be obtained in which there is no positional deviation or bleeding of the displayed pixels.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit diagram of a signal electrode drive circuit 6 embodying the present invention is shown in FIG. 1, and its drive waveform is shown in FIG. In FIG. 1, the same parts as those shown and described in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted. FIG. 2A shows the shift pulse C
The waveform of K is shown.

The logic gate circuit 3 includes an OR logic circuit G1,
G2, G3, ..., Gn and AND logic circuits F1, F2,
It is composed of F3, ..., Fn.

AND logic circuits F1, F2, F3, ..., F
n is the switch signal input from the two input terminals,
"Low" if at least one is at "Low" level
It becomes the level, and if both the switch signals input from the two input terminals are at the "High" level, "High"
Switch signals S'1, S'2, S'3, which become levels,
..., S'n is output. AND logic circuits F1, F2, F
One of the input terminals of 3, ..., Fn is connected to the terminal t3. The switch signal COFF is input to the terminal t3.

The OR circuits G1, G2, G3, ..., Gn are
If at least one of the switch signals input from the two input terminals is at "High" level, it becomes "High" level, and if both of the switch signals input from the two input terminals are at "Low" level, "Low" level Level switch signals S "1, S" 2, S "3, ..., S"
Output n. One input terminal of each of the OR circuits G1, G2, G3, ..., Gn is connected to the terminal t4. The switch signal CON is input to the terminal t4.

Description will be made assuming that the display is performed only on the i-th pixel in one horizontal scanning period. Based on a memory (not shown) such as a microcomputer, an external control device (not shown) outputs the pixel sampling shown in FIG. 2 (H) from the shift register 2 for displaying only the i-th pixel. The video signal COFF as shown in FIG. 2 (E) so that the timing and the waveform match the pulse Si.
Is supplied to the input terminal of each AND circuit Fi via the terminal t3.

First, as the first operation procedure, as shown in FIG.
As shown in, switch signal CON is kept "High" for a certain period.
When set to level, each pixel sampling pulse Si (i
Is a natural number less than or equal to n. The following subscript i is equal to this i. ), The switch signal COFF, and the switch signal S'i, the OR circuit Gi causes all the switch signals S "i to be at the" High "level for a certain period of time, and the sources s and drains d of all the sampling switches Ai become conductive. At this time, if the video signal V is set to the "Low" level as shown in FIG. 2C, all the sampling capacitors Ci can hold the "Low" level video pixel signal V'i. .

Next, as the second operation procedure, FIG.
As shown in FIG. 2C, the switch signal CON is set to the “Low” level, and in response to the rise of the horizontal synchronizing pulse S at time T0 as shown in FIG. 2B, as shown in FIG. The video signal V is set to the "High" level until the end of one horizontal scanning period.

Pixel sampling pulses S1, S2, ...
When Si-1, Si + 1, ..., Sn are input, the switch signal COF having the waveform shown in FIG.
F is at "Low" level. Therefore, the AND circuit Fi always outputs the "Low" level switch signal S'i regardless of the pixel sampling pulse Si. The OR circuit Gi also switches the switch signal CON to "Lo".
Since it remains at the w "level, the switch signal S" i at the "Low" level is output. Therefore, at this time, the video pixel signals V'i of "Low" level are still held in all the sampling capacitors Ci.

On the contrary, during the period Ti to T (i + 1) in which the pixel sampling pulse Si is input, the switch signal COFF is at "High" level as described above. During this period Ti to T (i + 1), as shown in FIGS. 2F, 2G and 2H, pixel sampling pulses S1, S2, S3,
..., out of Sn, only the pixel sampling pulse Si is "
Since it is at the "High" level and the others are at the "Low" level, only the switch signal S'i output from the AND circuit Fi shown in FIG. 2 (K) becomes the "High" level, while the other AND circuits. F1, ..., F (i-1), F (i + 1)
, ..., Fn output switch signals S'1, ..., S '
(i-1), S '(i + 1), ..., S'n are all shown in FIG.
As shown in (I) and (J), the level becomes "Low".

Since the switch signal CON remains at the "Low" level, the switch signal S'at the "High" level.
Only the switch signal S "i output from the OR circuit Gi receiving the input of i becomes" High "level, while the other OR
, G (i-1), G (i + 1), ..., Gn output switch signals S "1, ..., S" (i-1), S "(i + 1),
..., S "n are both at" Low "level.

Therefore, only the sampling capacitor Ci corresponding to the pixel to be displayed holds the "High" level video pixel signal Vi, but the other sampling capacitors C1, ..., C (i-1), C. (i + 1), ..., Cn have "Low" level video pixel signals V'1, ..., V '.
Since (i-1), V '(i + 1), ..., V'n are retained, it is possible to obtain a specific image such as accurate and clear characters without misalignment or bleeding.

Not only in the case of reproducing the binary video signal V shown in FIG. 2B obtained from the computer or the like as described above to display the OA image, but the switch signal COFF is set to "Hi".
The GH "level and the switch signal CON are fixed to the" Low "level to easily reproduce the video signal V having a continuous value as shown in FIG. Can also be displayed.

Next, FIG. 3 shows a circuit diagram of the signal electrode drive circuit 6 in the case of performing full color display using the three primary colors embodying the present invention. In FIG. 3, the same parts as those shown and described in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. First,
When full color display is performed only on the i-th pixel within one horizontal scanning period, the operation is performed as described above, but the following points are changed.

As an image signal V corresponding to the image signal V in FIG. 1, since the three primary colors are separately supplied, the image signal V for red is supplied.
The video signal VG for R, the video signal VG for green, and the video signal VB for blue are supplied via terminals t5R, t5G, and t5B, respectively.

Further, the video signals VR, VG and VB are time-divided, and the operation of holding the video pixel signal V'i by the sampling capacitor Ci is surely synchronized. Therefore, it corresponds to the switch signal COFF in FIG. As a thing
Signals COFFR, COFFG, COFFB are supplied via terminals t3R, t3G, t3B.

The switch signals COFFR, COFFG, COFFB and the video signals VR, VG, VB are alternately AND circuits Fi, F (i + 1) 1, F (i + 2), and the sampling switch Ai.
, A (i + 1), A ′ (i + 2) (i is a natural number of n or less).

The shift register circuit 2 outputs the pixel sampling pulse Sj to the AND circuits F3j, F (3j-1) and F (3j-2).
Supply to one of the input terminals at the same time.

[0043]

As described above, according to the present invention,
Both a OA image and an AV image can be displayed on one display device, and switching between them can be easily performed. Moreover, when an OA image is displayed, a good display can be obtained in which the displacement of the pixels to be displayed and the blurring of the image do not occur, and the versatility of the display device can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a signal electrode drive circuit of a liquid crystal display device embodying the present invention.

FIG. 2 is a diagram showing waveforms of respective signals in a signal electrode drive circuit of a liquid crystal display device embodying the present invention.

FIG. 3 is a circuit diagram of a signal electrode drive circuit of another liquid crystal display device embodying the present invention.

FIG. 4 is a block circuit diagram showing a configuration of a general liquid crystal display device.

FIG. 5 is a circuit diagram of a signal electrode drive circuit of a conventional liquid crystal display device.

FIG. 6 is a diagram showing waveforms of respective signals in a signal electrode drive circuit of a conventional liquid crystal display device.

[Explanation of symbols]

1 Sample and Hold Circuit Section 2 Shift Register Circuit 3 Logic Gate Circuit 4 Active Matrix Liquid Crystal Display Device 5 Scanning Electrode Driving Circuit 6 Signal Electrode Driving Circuit 7 Control Circuit 8 Display Panel 9 Thin Film Transistor 10 Signal Electrode 11 Scanning Electrode 12 Pixel Electrodes t1 to t5 , T3R, t3G, t3B, t5R, t5G, t5B terminal L1 to Ln terminal A1 to An sampling switch B1 to Bn hold switch C1 to Cn sampling capacitor D1 to Dn hold capacitor E1 to En output buffer circuit F1 to Fn AND circuit G1 Gn OR circuit CK shift pulse COFF, COFFR, COFFG, COFFB signal CON signal S horizontal sync pulse S1 to Sn pixel sampling pulse S'1 to S'n switch signal S "1 to S" n switch signal V video signal (VR red , VG green, VB blue) V1 to Vn video Motoshingo V'1 ～V'n video pixel signal T line switch signal

Claims (1)

[Claims] 1. In order to input a signal voltage corresponding to the shading of the display of a display pixel to each signal electrode of a matrix type display device, the display signal of the display signals of each pixel is arranged in time series. A plurality of sample and hold circuits corresponding to the number of signal electrodes having a switch means and a capacitor for extracting a voltage corresponding to a pixel to be operated, and a sampling means for sequentially performing the sampling operation of the sample and hold circuits. In a drive circuit of a display device having a first switch signal supply means for generating a switch signal and an output circuit for outputting a voltage held by a sample hold circuit to a signal electrode, a display desired to be displayed in the input video signal A second switch for instructing to turn on only during a period including a video pixel signal of a pixel and off during other periods. Switch means for selecting whether to output or inhibit the first switch signal, and all switch means of the sample and hold circuit regardless of the output of the gate means to reset the sample and hold circuit. A driving circuit for a display device, which has a mode for turning on the switch and a mode for operating the sample-hold circuit to pass the output of the gate means to the switch means.