JPH0324783U - - Google Patents
Info
- Publication number
- JPH0324783U JPH0324783U JP8353489U JP8353489U JPH0324783U JP H0324783 U JPH0324783 U JP H0324783U JP 8353489 U JP8353489 U JP 8353489U JP 8353489 U JP8353489 U JP 8353489U JP H0324783 U JPH0324783 U JP H0324783U
- Authority
- JP
- Japan
- Prior art keywords
- period
- horizontal
- pulse train
- periodic control
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000737 periodic effect Effects 0.000 claims description 6
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
Landscapes
- Transforming Electric Information Into Light Information (AREA)
Description
第1図は本考案のインターレース方式拡大画面
液晶テレビに適用される飛び越し付き周期制御パ
ルス列の形成回路を示し、第2図はパルス列の形
成方法と各パルス列のタイミングの関係を示し、
第3図は液晶テレビのパネルとドライバの相互要
部関係を示す。
1……クロツクパルス列、1′……タイミング
をずらしたクロツクパルス列、1″……スタート
パルス、2……飛び越し付き周期制御パルス列、
2′……タイミングをずらした飛び越し付き周期
制御パルス列、3……デイレイ回路、4……OR
回路、5……パネル、6……ドライバ、7……ソ
ース・ドライバ。
FIG. 1 shows a circuit for forming a periodic control pulse train with interlace applied to the interlaced enlarged screen LCD television of the present invention, and FIG. 2 shows the relationship between the method of forming a pulse train and the timing of each pulse train.
FIG. 3 shows the relationship between the main parts of a liquid crystal television panel and a driver. 1... Clock pulse train, 1'... Clock pulse train with shifted timing, 1''... Start pulse, 2... Periodic control pulse train with skip,
2'... Periodic control pulse train with skipping with shifted timing, 3... Delay circuit, 4... OR
Circuit, 5... Panel, 6... Driver, 7... Source driver.
Claims (1)
なうことにより映像化される液晶テレビにおいて
、パネル5に備え、水平周期Hの制御信号を入力
するゲート・ドライバ6に対して水平周期Hを支
えるクロツクパルスとデイレイ回路を通して時間
差を与えた第2クロツクパルスとをOR回路で組
み合わせた飛び越し付き水平周期制御パルス列2
を入力して、1ゲートおきの水平周期制御を画面
前周期で行う一方、画面後周期では0.5Hずら
した前記飛び越し付き水平周期制御パルス列2を
前記ドライバー6に与えて、前周期で飛び越した
ゲートの水平周期を順次制御することにより液晶
テレビにインターレース方式を適用したことを特
徴とするインターレース方式拡大画面液晶テレビ
。 In a liquid crystal television that displays images by scanning by adding one pulse to 1H every horizontal period, the panel 5 is equipped with a gate driver 6 that supports the horizontal period H to which a control signal of the horizontal period H is input. Horizontal periodic control pulse train 2 with interlacing, in which a clock pulse and a second clock pulse given a time difference through a delay circuit are combined in an OR circuit.
is input, and the horizontal periodic control of every other gate is performed in the pre-screen period, while in the post-screen period, the horizontal periodic control pulse train 2 with skipping is given to the driver 6, which is shifted by 0.5H, and the pulse train is skipped in the previous period. An interlaced enlarged screen LCD television characterized by applying an interlacing method to a liquid crystal television by sequentially controlling the horizontal period of gates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8353489U JPH0324783U (en) | 1989-07-18 | 1989-07-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8353489U JPH0324783U (en) | 1989-07-18 | 1989-07-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0324783U true JPH0324783U (en) | 1991-03-14 |
Family
ID=31631280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8353489U Pending JPH0324783U (en) | 1989-07-18 | 1989-07-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0324783U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63194481A (en) * | 1987-02-07 | 1988-08-11 | Nec Home Electronics Ltd | Display using solid-state display device |
-
1989
- 1989-07-18 JP JP8353489U patent/JPH0324783U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63194481A (en) * | 1987-02-07 | 1988-08-11 | Nec Home Electronics Ltd | Display using solid-state display device |
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