JPH07261713A - Display device - Google Patents

Abstract

PURPOSE:To enable the interlaced driving of a liquid crystal display panel incorporating an individual vertical scanning circuit. CONSTITUTION:An active matrix type liquid crystal display panel is provided with pixels LC arranged in a matrix. a vertical scanning circuit 1 and a horizontal scanning circuit 2. The vertical scanning circuit 1 scans line-sequentially pixel LC in a row unit by outputting successively selection pulses, on the other hand, the horizontal scanning circuit 2 writes a video signal (RGB signals) with respect to pixels of a row selected at every horizontal period and transfers, the signal. The vertical scanning circuit 1 selects successively a pair of pixel rows at every one horizontal peroid (1H) and assigns an effective selection pulse having a wide pulse width to the pixel row of one side to make the writing and transmission of the video signal possible and assigns an ineffective selection pulse having a narrow pulse width to the pixel row of the other side in a horizontal blancking time to perform a vacant transmission. Thus, the interlaced driving of the display panel is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device. More specifically, it relates to the interlaced drive system.

[0002]

2. Description of the Related Art N is the current TV broadcasting standard in Japan.
In the TSC system, one screen (one frame) is composed of two odd and even fields, and the number of scanning lines in one frame is 525 and the frame frequency is 30 Hz. However, most of the small LCD TVs or projection LCDs currently commercialized are
The number of horizontal scanning lines of the liquid crystal panel is 220 to 240.
This corresponds to about half the number of effective scanning lines in the NTSC system.
Therefore, in these LCDs, half-line driving that constitutes one screen by only one field video signal is performed. Although the vertical resolution is reduced in terms of image quality, since non-interlaced scanning is performed in half-line driving, the resolution is improved by about 30% over interlaced scanning when the number of scanning lines is the same. Considering this, the reduction in vertical resolution due to half-line driving is about 35%.

In a small screen of about 3 to 4 inches, the deterioration of the resolution has little influence on the image quality, but in a projection type LCD for displaying a large screen of 40 inches or more, full line driving is strongly desired. It has been actively developed in recent years. For example, in an active matrix type liquid crystal panel having a full frame structure as shown in FIG. 8, the number of horizontal scanning lines is doubled compared to 220 to 240 lines having a half frame structure. In such a liquid crystal panel having a full frame structure, both non-interlace drive and interlace drive can be considered, but usually non-interlace drive is adopted.
When performing non-interlaced driving, there is a drawback that a large-capacity memory is required because the original video signal is double-speed processed and supplied to the liquid crystal panel, and the system configuration becomes large.

[0004]

On the other hand, FIG. 9 shows a structure for interlace driving a liquid crystal panel having a full frame structure. This configuration is, for example, the Journal of the Television Society
Vol.40, No. 10 (1986), two systems of a first V scanner for odd lines and a second V scanner for even lines are used. If a pair of these V scanners are built in the liquid crystal panel, there is a drawback in that the panel size is increased accordingly.

[0005]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to enable interlaced driving of a display device such as an active matrix type liquid crystal panel with one system of V scanner. The following measures have been taken in order to achieve this object. That is, the display device according to the present invention has, as a basic configuration, pixels arranged in rows and columns, a vertical scanning circuit, and a horizontal scanning circuit. The vertical scanning circuit sequentially outputs selection pulses to scan pixels line by line in a row-sequential manner. The horizontal scanning circuit writes and transfers the video signal to the pixels in the selected row every horizontal period. As a feature of the present invention, the vertical scanning circuit sequentially scans a pair of pixel rows for each horizontal period, allocates an effective selection pulse to one pixel row, and enables write transfer of a video signal, and the other Interlace drive is performed by assigning an invalid selection pulse to the pixel row during the blanking time and performing idle transfer.

As a concrete configuration, the vertical scanning circuit is composed of multi-stage connection of flip-flops and outputs a selection pulse by sequentially transferring a rectangular start signal in synchronization with a rectangular clock signal. In this case, the effective selection pulse and the invalid selection pulse can be alternately output by setting the duty ratio of the rectangular clock signal according to the ratio of the retrace time in one horizontal period. The duty ratio of the rectangular clock signal is set between 5% and 17%. Preferably, a masking means is included to prohibit the output of the invalid selection pulse in synchronization with the blanking time. Further, an external timing generator is included, and a rectangular clock signal is supplied to the vertical scanning circuit so that the duty ratio can be switched to enable selection between interlaced driving and non-interlaced driving.

[0007]

In general, the vertical scanning circuit sequentially transfers the rectangular start signal in synchronization with the rectangular clock signal, thereby outputting the selection pulse corresponding to one horizontal period and turning on the pixel driving switching elements on the same line. To do. The video signal for one horizontal period is written and transferred to one line through the switching element in the conductive state. In the present invention, by changing the duty ratio of the rectangular clock signal, a wide effective selection pulse and a narrow invalid selection pulse are generated within one horizontal period. By selecting the duty ratio of the clock signal so that the width of the invalid selection pulse falls within the blanking time (horizontal blanking period) of the video signal,
Performs idle transfer of video signals. Also, the portion of the actual video signal is written and transferred by the effective selection pulse. By this,
In one horizontal period, a video signal can be written and transferred to one of the two lines, and a video signal can be idle transferred to the other one line. By allocating the effective selection pulse to the even lines in the odd field and allocating the effective selection pulse to the odd lines in the even field, it becomes possible to interlace drive the active matrix type display device. Therefore, the duty ratio of the rectangular clock signal must be selected so that the width of the shorter invalid selection pulse falls within the horizontal blanking period of the video signal. Therefore, it suffices if the duty ratio is about 17% or less. When the duty ratio becomes larger than this, a part of the video signal is lost. Theoretically, it may be 17% or less, but about 5% is actually suitable.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a liquid crystal display panel as an example of a display device according to the present invention. As shown in the figure, the liquid crystal display panel has pixels LC arranged in rows and columns. Each liquid crystal pixel LC is configured by sandwiching liquid crystal between a pixel electrode provided on the main substrate side and a counter electrode provided on the counter substrate side. A predetermined counter voltage Vcom is applied to the counter electrode. Individual liquid crystal pixel L
An additional capacitance Cs is connected to C in parallel. Further, a thin film transistor Tr is integrally formed as a switching element for driving each liquid crystal pixel LC. The gate lines X are arranged along the row direction of the liquid crystal pixels LC arranged in rows and columns, and the signal lines Y are arranged along the column direction orthogonal to the gate lines X. The source electrode of each thin film transistor Tr is connected to the corresponding signal line Y,
The drain electrode is connected to the corresponding pixel electrode, and the gate electrode is connected to the corresponding gate line X.

The liquid crystal display panel further includes a vertical scanning circuit (V
It includes a scanner 1 and a horizontal scanning circuit (H scanner) 2. The vertical scanning circuit 1 sequentially outputs a selection pulse to the gate line X, turns on the thin film transistors Tr on the same gate line, and line-sequentially scans the liquid crystal pixels LC row by row. The vertical scanning circuit 1 outputs the above-described selection pulse by sequentially transferring a rectangular vertical start signal VST input from the outside in synchronization with rectangular vertical clock signals VCK1 and VCK2 input from the outside.

On the other hand, the horizontal scanning circuit 2 controls the opening and closing of the horizontal analog switch HSW connected to each signal line Y. A video signal divided into three primary color components of R, G and B is supplied to each signal line Y through the analog horizontal switch HSW. The horizontal scanning circuit 2 is synchronized with the horizontal clock signals HCK1 and HCK2 input from the outside, and the horizontal start signal H is also input from the outside.
The horizontal analog switch HSW is controlled to be opened and closed by sequentially transferring ST within one horizontal period. As a result, the video signal is written and transferred to the liquid crystal pixels LC in the selected row every horizontal period.

Next, the operation of the liquid crystal display panel shown in FIG. 1A will be described with reference to FIG. The vertical scanning circuit 1 described above is composed of multi-stage connection of flip-flops, and is synchronized with a pair of rectangular clock signals VCK1 and VCK2 having opposite phases to each other and a rectangular start signal VST.
To output a selection pulse. As a feature of the present invention, the duty ratio of the rectangular clock signal VCK1 is set according to the ratio of the horizontal blanking period in one horizontal period (1H), and the valid selection pulse and the invalid selection pulse are alternately output. . In the illustrated example, an effective selection pulse having a wide pulse width is supplied to the first gate line X1, and an invalid selection pulse having a narrow pulse width is supplied to the second gate line X2. Similarly, the effective selection pulse is applied to the odd-numbered gate lines,
An invalid selection pulse is supplied to even-numbered gate lines. This even-odd relationship is exchanged for each field.

FIG. 1C shows the phase relationship between each horizontal period of the video signal and the selection pulse. The vertical scanning circuit 1 shown in FIG. 1A sequentially scans a pair of pixel rows (2 lines) every horizontal period of a video signal, and allocates an effective selection pulse to one line of the video signal. Interlace drive is enabled by enabling write transfer and assigning an invalid selection pulse to the other line within the horizontal blanking period to perform idle transfer. As shown in the figure, one horizontal period (1H) is 63.5 μs, and the horizontal blanking period included therein is 10.9 μs. The invalid selection pulse is output in the horizontal blanking period, and its pulse width is narrower than that in the horizontal blanking period. In the illustrated example, the invalid selection pulse is 3.2 μ.
It has a pulse width of s. This corresponds to 5% of one horizontal period, and can be obtained by setting the duty ratio of the rectangular clock signal VCK1 described above to 5%. From the calculation, this duty ratio may be 17% or less, but in practice, about 5% is optimal.

FIG. 2 is a circuit diagram showing a specific configuration example of the vertical scanning circuit 1 shown in FIG. As described above, the vertical scanning circuit (V scanner) 1 outputs a selection pulse for bringing the thin film transistor Tr for driving liquid crystal pixels into a conductive state for one horizontal period, and the horizontal scanning circuit (H scanner).
On the other hand, the line sequential scanning is completed in one field (1 / 60s). The circuit configuration is such that D-type flip-flops 3 having a number of stages corresponding to the number of columns of liquid crystal pixels are connected in series. Two
The start pulse VST is sequentially transferred by the phase clock signals VCK1 and VCK2, and the selection pulse is output. Further, by passing through the NAND gate 4 of the next stage, the start signal VST is sequentially transferred with half the number of stages of the actual liquid crystal pixel column.

The operation of the vertical scanning circuit shown in FIG. 2 will be described in detail with reference to FIG. The timing chart of FIG. 3 shows a case where double-speed non-interlaced driving is performed on an active matrix type liquid crystal display panel having a full frame structure. Vertical clock signals VCK1, VC
K2 is set to a duty ratio of 50%. Moreover, FIG.
The enable signal EN shown in is active low,
It is fixed at a high level in double speed non-interlaced drive. Waveforms a to e shown in the timing chart of FIG.
Represents a signal output from each stage of the D-type flip-flop 3 shown in FIG. As you can see from the figure,
Vertical start signal VST is clock signals VCK1 and VC
The signals are sequentially transferred every half cycle of K2, and the output signals a to e are sequentially obtained from the D-type flip-flops at each stage. These output signals are processed by the NAND gate 4 and select pulse A
~ E are sequentially output. In this non-interlaced driving, selection pulses A, B, C, D, E, ... Are sequentially generated for each line of the liquid crystal display panel, and non-interlaced driving is performed by writing and transferring a video signal corresponding to one line.

FIG. 4 is a timing chart in the case where the liquid crystal display panel having the full frame structure is interlaced driven according to the present invention. In this example VCK
The duty ratio of 1 is set to 5%, and the duty ratio of VCK2 is set to 95%. In this case, the signal b output from the second-stage flip-flop is delayed by the duty ratio of 5% and output with respect to the signal a output from the first-stage flip-flop. The signal c output from the third-stage flip-flop is delayed by an amount corresponding to a duty ratio of 95% with respect to the output signal b of the preceding stage and is output. When these output signals a, b, c, d, e, ... Are respectively processed by the NAND gate 4, selection pulses A, B, C, D, E ,. However, this is a case where the active-low enable signal EN is held at a high level, and a valid selection pulse (A, C, E) having a wide width and an invalid selection pulse (B, D) having a narrow width are provided every other line.
Are output alternately. Here, if the pulse generation time x of VCK1 is selected in advance within the horizontal blanking period, B
The invalid selection pulses D and D are output within the horizontal blanking period. Therefore, no effective video signal is written to the even-numbered lines.

In the present invention, when the above-mentioned interlace drive is performed, the active low enable signal EN is actually supplied to each NAND gate 4. The enable signal EN is synchronized with the horizontal blanking period and prohibits the output of the invalid selection pulses B, D, ...
Therefore, finally, as shown at the bottom of the timing chart of FIG. 4, only the valid selection pulses A, C, and E are sequentially supplied to the odd lines, and the invalid selection pulses are not supplied to the even lines. Interlace driving can be performed by supplying the effective selection pulse for every other line to the odd line in the even field and to the even line in the odd field. In addition, the clock signal V shown in FIG.
CK1 and VCK2 and the clock signal VCK shown in FIG.
By switching between 1 and VCK2 by an external timing generator, non-interlaced driving and interlaced driving can be performed in the same active matrix type liquid crystal display panel.

FIG. 6 shows EN included in the enable signal EN.
It is a waveform diagram which shows the original role of a pulse. As shown in the figure, the EN pulse is originally for cutting the rounding of the waveform generated at the falling portion of the gate pulse (selection pulse), and is used for improving the display image quality. In the present invention, the masking process of the invalid selection pulse is performed using this EN pulse.

FIG. 5 is a system block diagram showing the overall structure of the liquid crystal display device according to the present invention. As shown in the figure, this system has a full-line liquid crystal display panel and 11
, RGB driver 12, decoder 13, main timing generator 14, sub-timing generator 1
It is composed of 5 and. Full line LCD display panel 1
1 has the internal configuration shown in FIG. 1, and is provided with liquid crystal pixels arranged in rows and columns, a vertical scanning circuit, and a horizontal scanning circuit. The decoder 13 processes the externally input composite video signal to separate the horizontal sync signal HSYNC and the vertical sync signal VSYNC. Further, the composite video signal is demodulated to generate RGB image data. The RGB driver 12 performs sample-and-hold according to the S / H pulse, and at the same time, the R of the alternating current according to the alternating signal FRP
The GB video signal is supplied to the full line liquid crystal display panel 11. In this example, AC inversion drive (1H drive) is performed every horizontal period according to FRP. Also, RGB driver 1
2 also supplies the counter voltage Vcom to the full line liquid crystal display panel 11. Full line LCD panel 1
1, the power supply voltage HV for the horizontal scanning circuit in addition to Vcom
The DD, the power supply voltage VVDD for the vertical scanning circuit, and the ground potential GND are supplied.

The main timing generator 14 basically supplies various timing signals necessary for performing non-interlace, and in synchronization with HSYNC and VSYNC, the horizontal start signal HST is supplied to the full line liquid crystal display panel 11. , Horizontal clock signals HCK1, HC
K2, vertical start signal VST, enable signal EN,
A clear signal CLR or the like is supplied. Also, as mentioned above, RG
The S / H pulse is supplied to the B driver 12. Further, the vertical clock signals vck1, vck2, the 1-field inversion signal 1F, and the clear signal CLR having a duty ratio of 50% are supplied to the sub-timing generator 15.

The sub-timing generator 15 is necessary when interlace driving is performed according to the present invention.
Vertical clock signal VCK having a duty ratio of 5%, for example
1 and VCK2 are supplied to the full line liquid crystal display panel 11. Further, in order to perform 1H AC inversion according to the interlace drive, the above-mentioned AC signal FRP is supplied to the RGB driver 12. The sub-timing generator 15 includes two independent 3-circuit 2-to-1 analog multiplexer / demultiplexer (for example, 4053B) 16 and 17. Furthermore, a D-type flip-flop (for example, 74HC)
74) 18 is included. One analog multiplexer / demultiplexer 16 receives the 1-field inverted signal 1F and the clear signal CLR and receives a pair of interlace driving vertical clock signals VCK1 and VCK2.
Is output. The VCK1 and VCK2 are composed of the CLR and the inverted CLR which are alternated every other field and the inverted pulse thereof. In addition, referring to FIG. 7, C
The original role of the LR pulse will be described. The CLR pulse is originally for cutting a part of the gate pulse (selection pulse), and is intended to improve the display image quality. In this embodiment, C input from the main timing generator 14
The LR pulse is processed to obtain vertical clock signals VCK1 and VCK2 for interlace driving. Next, the D-type flip-flop 18 is used as a 1/2 frequency dividing circuit and divides the 1-field inversion pulse 1F to output a 2-field inversion pulse 2F. The 2-field inversion pulse 2F is used to form the interlaced alternating signal FRP. That is, the second analog multiplexer / demultiplexer 17 receives the vck1, vck2 and the 2-field inversion pulse 2F and receives the alternating signal FRP.
Is being output. This FRP is vc every 2 fields
The k1 and vck2 are exchanged.

[0021]

As described above, according to the present invention, the duty ratio of the vertical clock signal is basically used by using the liquid crystal panel for non-interlace including only one vertical scanning circuit. Interlace drive can be performed simply by changing. As a result, it is possible to achieve both non-interlaced drive and interlaced drive. Further, when interlaced driving is performed, since a liquid crystal display panel having only one vertical scanning circuit incorporated therein can be used, there is an effect that the panel size can be reduced and the cost can be suppressed.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a basic configuration and operation of a liquid crystal display panel according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a vertical scanning circuit incorporated in the liquid crystal display panel shown in FIG.

FIG. 3 is a timing chart for explaining non-interlaced driving of the vertical scanning circuit shown in FIG.

FIG. 4 is a timing chart for explaining interlaced driving of the vertical scanning circuit.

FIG. 5 is a system block diagram showing an overall configuration of a display device according to the present invention.

FIG. 6 is a waveform diagram of an EN pulse used as a control signal.

FIG. 7 is a waveform diagram of a CLR pulse which is also used as a control signal.

FIG. 8 is a schematic view showing an example of a conventional active matrix type liquid crystal display panel.

FIG. 9 is a schematic view showing an example of a conventional interlace drive liquid crystal display panel.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Vertical scanning circuit 2 Horizontal scanning circuit 3 D-type flip-flop 4 NAND gate 11 Full line liquid crystal display panel 12 RGB driver 13 Decoder 14 Main timing generator 15 Sub timing generator

Claims (5)

[Claims] 1. A pixel arranged in a matrix, a vertical scanning circuit,
A horizontal scanning circuit, the vertical scanning circuit sequentially outputs a selection pulse to line-sequentially scan pixels on a row-by-row basis, and the horizontal scanning circuit outputs an image to pixels on a selected row every horizontal period. A display device for writing and transferring a signal, wherein the vertical scanning circuit sequentially scans a pair of pixel rows for each horizontal period, assigns an effective selection pulse to one pixel row, and enables writing and transfer of a video signal. A display device characterized by enabling interlace driving by assigning an invalid selection pulse to the other pixel row during a blanking time and performing idle transfer. 2. The vertical scanning circuit comprises a multi-stage connection of flip-flops and outputs a selection pulse by sequentially transferring a rectangular start signal in synchronization with a rectangular clock signal,
2. The display device according to claim 1, wherein the effective selection pulse and the invalid selection pulse are alternately output by setting the duty ratio of the rectangular clock signal according to the ratio of the retrace time in one horizontal period. . 3. The display device according to claim 2, wherein the duty ratio of the rectangular clock signal is set to 5 to 17%. 4. The display device according to claim 1, further comprising a masking means for inhibiting the output of the invalid selection pulse in synchronization with the flyback time. 5. A timing generator is included,
3. The display device according to claim 2, wherein a rectangular clock signal is supplied to the vertical scanning circuit so that the duty ratio can be switched to enable selection between interlaced driving and non-interlaced driving.