JP2000039603A - Driving device for plasma addressed liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a driving device of a display device without generating deterioration in an S/N ratio even when the contrast of a display picture is reduced in a normally black mode plasma addressed liquid crystal display device provided with a first transparent scanning electrode group located on the first plane of the liquid crystal display device and a second scanning electrode group located oppositely to the second plane, forming plasma discharging channels formed plurally in the direction crossing perpendicularly to the first scanning electrode group. SOLUTION: This driving device is provided with a charge and hold type D/A converter 27 supplying driving voltages to a first scanning electrode group, a common anode inversion driving circuit 30 applying common anode inversion driving voltages to invert the driving voltages comparatively to a second scanning electrode group and gain regulators 41, 42 controlling the reduction of contrast by reducing the amplitude of the common anode inversion driving voltage and the amplitude of the driving voltages to the first scanning electrode group while taking tracking simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a plasma addressed liquid crystal display using a plasma addressed liquid crystal display which forms an image by an active matrix system.

[0002]

2. Description of the Related Art In recent years, in order to obtain more powerful images in consideration of, for example, an installation space that can be secured in a home, a large and thin television receiver, a rear projection type Projector devices have become widespread.

[0003] These television receivers and rear projection type projector devices have been realized to be considerably thinner as compared with those of the past in accordance with technological progress. In the case of television receivers, for example, CRT (Cathode Ray) Due to the depth of the tube, and in the case of a projector device, there is a natural limit to the reduction in thickness due to structural conditions such as the angle at which the projection lens is installed.

Further, a TFT (Thin Film Transistor)
A display device using a liquid crystal panel can be configured to be thinner than the above-described television receiver and projector device. However, in order to obtain a large-sized display device, an increase in the number of TFTs formed by IC technology requires higher precision. Along with the demand for manufacturing technology, the production yield is very low and the cost is very high.

Therefore, a plasma-addressed liquid crystal (Plasma Addressed Liquid Crystal) (hereinafter, referred to as a television receiver or a projector) which has a large screen equivalent to that of a projector and has a thickness comparable to that of a TFT liquid crystal panel has been realized.
A display device using the acronym PALC) for a display unit has been proposed.

This plasma-addressed liquid crystal device has a TF
High brightness and high contrast comparable to a T liquid crystal panel can be realized, and a large screen can be realized by a PDP (Plasma Display Panel) manufacturing technique. The plasma addressed liquid crystal device is a normally black plasma addressed liquid crystal device.

Next, the structure of a PALC used in an embodiment of the present invention described later will be described with reference to FIGS. FIG. 2 is an exploded perspective view of a liquid crystal display device using PALC. FIG. 3 is a perspective view showing a part of the structure of the PALC, and a part is shown in a sectional view. As shown in FIG. 2, the PALC 1 has a structure as a transmissive display device for forming an image by selectively transmitting a light beam radiated from a backlight 2 disposed on its back surface by an active matrix system. .

As shown in FIG. 3, a plasma substrate (back glass) 5 is provided with, for example, scanning grooves (cuts) at predetermined intervals which are horizontally partitioned into hollows by partition walls (ribs) 6, 6, 6,. The scanning groove formed by the following is also possible),
Are formed. In these scanning grooves 7, the anode electrodes 8,
, And the cathode electrodes 9, 9, 9,... Are formed at regular intervals so as to form a pair. That is, this scanning groove 7 constitutes a horizontal scanning line corresponding to the effective screen of PALC1, and the number of scanning lines (for example, about 480)
Book) is formed.

By arranging the thin glass substrate 10 on which an insulating layer is formed in front of the partition walls 6, 6, 6,..., The scanning grooves 7, 7, 7,.
The inside thereof is filled with a rare gas such as helium gas or a mixed gas of rare gases as a plasma gas.

The cathode electrode 9 is supplied, for example, with a voltage of about -300 V from a driver circuit for plasma discharge (not shown).
Is applied at a predetermined timing (however, a ground potential is applied to the anode electrode 8), and a plasma discharge is generated between the anode electrode 8 and the cathode electrode 9 as described later in detail. I'm trying to wake them up.

By the plasma discharge, the plasma gas is ionized in the scanning groove 7 and an electric conductor (plasma channel) is formed until the plasma particles are completely extinguished. (Strobe).

In front of the thin glass (insulating layer) 10, a liquid crystal layer (liquid crystal display device) for forming pixels in a matrix is provided.
11, a color filter (layer) 12 composed of striped red, green, and blue filter portions 12R, 12G, and 12B corresponding to each color of red, green, and blue, and striped red and green driving pixels of the liquid crystal layer 11. , Blue drive electrodes 13R, 13G,
13B, transparent electrodes (transparent drive electrodes) (transparent electrode layers) (for example, ITO (Indium Tin Oxide: indium tin oxide) thin film) 13 are arranged at regular intervals in the scanning grooves 7,
Are arranged so as to be orthogonal to 7, 7,..., And each orthogonal portion thereof is configured to be each pixel.

That is, the transparent drive electrode 13 of the PALC 1
By supplying video signals (data) for one horizontal line to R, 13G, and 13B, and sequentially selecting (strobe) and discharging the plasma gas in the scanning groove 7 in the vertical direction, the transparent driving electrodes 13R, 13G, and 13B are discharged. A video signal is applied to the liquid crystal of the pixel where 13G, 13B and the scanning groove 7 intersect,
Since the transmittance of the light emitted from the backlight 2 differs for each pixel, a color image can be displayed.

That is, as shown in FIG.
By arranging the polarization filters 3 and 4 on the incident side and the exit side of the ALC 1, respectively, the transmission amount of the light polarized by the PALC 1 can be controlled, and a color image can be formed by the same principle as that of a normal TFT liquid crystal display device. Will be able to gain.

Next, the switching operation for forming an image for one field will be described in more detail with reference to FIGS. FIG. 4 is a diagram schematically showing a part of the PALC 1 shown in FIG. 3 from a side. In order to explain the switching operation by the plasma channel, a switch SW is shown in FIG. 5A for convenience.

As described above, when a plasma generation pulse of, for example, -300 V is applied to the cathode electrode 9 (a ground potential is applied to the anode electrode 8) to cause a plasma discharge, a plasma channel is formed in the scanning groove 7. But
This plasma channel becomes a virtual electrode and the transparent electrode layer 1
3 (red, green and blue drive electrodes 13R, 13G, 13B) and the anode electrode 8 apply a video signal voltage. That is, the illustrated switch SW is turned ON.

FIG. 4 shows that when a voltage of -300 V is applied to the plasma channel by the switch SW, plasma gas is generated in the scanning groove 7 of the first line, and the strobe is generated.
(1) shows a state where is turned on. This shows a state in which no plasma gas has yet been generated in the scanning groove 7 of the second line, and the strobe remains off. As shown in FIG. 4, when the plasma channel is formed by the plasma discharge, the inside of the scanning groove 7 becomes conductive, which is equivalent to the FET as shown in FIG. 5B.
(Field-effect Transistor) This can be described as an operation of a switching element.

By the switching operation by the plasma channel, a virtual electrode is generated on the inner surface of the thin glass (substrate) 10 shown in FIG.
By applying a video signal voltage for driving pixels to G and 13B, the scanning groove 7 and the driving electrodes 13R,
A drive voltage is applied to each pixel (for one line) of the liquid crystal layer 11 at the intersection of 13G and 13B.

Therefore, the plasma discharge is sequentially applied to the scanning grooves 7.
By scanning so as to occur within (for example, the first line to the 480th line) and forming an image of one field, for example, an image of one field can be displayed.

That is, after selecting which line of an image is to be formed by the plasma channel, a driving voltage for forming an image of the line is applied to the red, green and blue driving electrodes 13R, 13G, 13B. 1 realizes selective scanning of lines constituting one field.
At this time, the light transmitted through the liquid crystal layer 11 is
By transmitting the red, green, and blue filter portions R, 12G, and 12B, a color image can be displayed. As a result, one line is synchronized with the driving of the pixels for one line.
By sequentially applying a drive voltage to the cathode electrodes from the line to the 480th line, an image for one field can be formed.

By configuring a display device using a PALC capable of forming an image with such a structure and operation principle as a display device, a thin, lightweight and large-screen display device can be configured.

Hereinafter, a specific circuit of a driving circuit of a liquid crystal display device having a conventional plasma addressed liquid crystal display device will be described in detail with reference to FIG. In FIG. 21, NT
An SC (National Television System Committee) upstream stage of the demodulation unit 21 is a broadcast receiving unit, such as a U / V tuner or a BS tuner of an NTSC system, not shown.
For example, one or more input terminals for inputting a standard video signal reproduced by an external device such as a VTR are provided.

Then, the standard video signal selected by the broadcast receiving means and the external standard video signal input from one or a plurality of input means are selected in the display device, and the NTS
It is supplied to the C demodulation unit 21.

The NTSC demodulation unit 21 demodulates the standard video signal into a luminance signal and a color difference signal, and supplies the luminance signal and the color difference signal to the double speed conversion unit 22. The demodulation unit 2
1 extracts a synchronizing signal from a luminance signal obtained by demodulation and supplies the synchronizing signal to an LCD (Liquid Crystal Display) controller 28 which will be described later. A clock is generated to synchronize various kinds of signal processing.

A frame memory capable of storing one frame of video signal (luminance signal and color difference signal) is provided in the double speed conversion section 22, and motion components are detected using this frame memory. Then, in the still image area of the video signal written in the frame memory, the video signal of the field at that time and the video signal of one horizontal period one field before are read twice consecutively at twice the writing speed.

In the moving image area of the video signal written in the frame memory, one of the field information at that time is stored.
An interpolated video signal generated by interpolation between the video signal in the horizontal period and the video signals in the upper and lower horizontal periods is read at double speed and converted to a 525H / 60 Hz non-interlace signal.

The video signal that has been subjected to the double speed processing is subjected to color adjustment, hue adjustment, and the like in the video signal processing unit 23, and then red, green, and blue primary color signals are generated by inverse matrix processing. Each of the primary color signals generated by the video signal processing unit 23 is
After the gain is adjusted by the gain adjuster 24 whose gain is adjusted by the control signal from the A / D converter 25, the digital red, green, and blue video data are converted by the A / D converter 25, each of which has an 8-bit quantization accuracy. Converted to V8. The gain adjuster 24 controls the A / D converter 25
By reducing the level of an input signal supplied to the transparent electrode 1 and reducing the number of gradations of video data to be displayed,
3, the driving voltage was lowered to reduce the contrast.

The red, green, and blue video data V8 from the A / D converter 25 is supplied to a white balance adjustment unit 26.
Is supplied to the liquid crystal column driver 27 after the white balance processing is performed.

The liquid crystal column driver 27 latches video data for one horizontal period (for example, 854 pixels), that is, 854 pixels × 3 channels (red, green, blue), that is, video data V8 of 2562 pixels, and stores video data for each pixel. V
8 is held for one horizontal period. When a plasma discharge is generated in a predetermined scanning groove 7 (FIG. 3) by a plasma driver 32 to be described later, the readout is performed for each horizontal line.
Further, the D / A built in the liquid crystal column driver 27
The converter converts the signal to an analog signal,
(Plasma address type liquid crystal display) 36 (1) transparent drive electrode (ITO) 13 (red, green, blue drive electrode 13R,
13G, 13B) (FIG. 3).

The LCD controller 28 is configured to operate with a power supply of 5 V, for example, and counts a clock for driving the ramp waveform generator 29 based on an operation clock generated based on a synchronization signal from the NTSC demodulator 21. Then, an anode inversion pulse (horizontal pulse) H for driving the anode inversion driving circuit 30 and a plasma pulse for driving the plasma driver 31 to cause plasma discharge for each scanning groove 7 (horizontal line) are generated.

The count clock from the LCD controller 28 is supplied to a ramp waveform generator 29. The ramp waveform VR obtained here is supplied to a liquid crystal column driver 27 incorporating a charge and hold type D / A converter described later.
Is supplied to the transparent column electrode 1 of the PALC 36 (1).
3 is driven. Further, the anode drive voltage from the anode inversion drive circuit 30 is applied to the anode electrode 8 of the PALC 36 (1).

The plasma driver 31 shown in FIG.
Here, a horizontal scanning line corresponding to about 480 lines constituting a screen of the NTSC system, that is, PALC as shown in FIG.
The scanning grooves 7 formed in 36 (1) are sequentially selected, a plasma pulse is supplied, and a plasma discharge is generated by a power supply voltage of about -300 V applied to the cathode electrode 9.

That is, in synchronization with the double-speed video data V8 input to the liquid crystal column driver 27, the scanning grooves 7,
, 7,... Are sequentially discharged from the top to the bottom, and the discharge state is repeated for each field,
The PALC 36 (1) can be driven according to the video data described above. As a result, the input video signal can be displayed as a video.

The backlight 35 (2) is arranged as a light source for illuminating the PALC 36 (1) from the back side as shown in FIG. 2, and the emitted light beam passes through predetermined pixels of the PALC 36 (1). Thus, a display image is formed.
Further, picture adjustment can be performed by adjusting the brightness of the backlight 35 (2).

The microcomputer control unit 33 allows the user to operate the operation unit 32.
In accordance with a command input from, various controls such as the above-described tuning of each tuner, image adjustment, and power ON / OFF are performed.
In FIG. 21, the object to be controlled by the microcomputer control unit 33 and the microcomputer control unit 33 are connected by a broken line.

[0036]

In the driving circuit of a liquid crystal display device having a conventional plasma addressed liquid crystal display device described with reference to FIG. 21, an image is formed on a PALC (plasma addressed liquid crystal display device) 36 (1). The contrast of the displayed image is reduced by the gain adjuster 24 inserted between the video signal processing unit 23 and the A / D converter 25.
The drive voltage of the transparent electrode 13 is reduced by reducing the level of the input signal of the / D converter 25 and reducing the number of gradations of the video data to be displayed.

At this time, at the maximum point of the contrast adjustment, the level of the input signal is made one time (100%). At the minimum point of the contrast adjustment, for example, the level of the input signal is reduced to about 1/4 (25%). To be reduced. With the reduction in the level of the input signal, the number of 256 (8 bits) gray levels of the driving voltage becomes about 64 (6 bits), and the S / N of the displayed image decreases. was there.

In view of the above, the present invention provides a first transparent scanning electrode group disposed on a first surface of a liquid crystal display device,
The first liquid crystal display device is disposed so as to face a second surface of the liquid crystal display device.
In a normally black plasma addressed liquid crystal display device including a second scan electrode group forming a plurality of plasma discharge channels formed in a direction orthogonal to the scan electrode group, the contrast of the displayed image is reduced. , S / N
An object of the present invention is to propose a driving device for a plasma addressed liquid crystal display device which does not cause deterioration.

[0039]

According to the present invention, there is provided a driving apparatus for a plasma addressed liquid crystal display device, comprising: a transparent first scanning electrode group arranged on a first surface side of the plasma addressed liquid crystal display device; A pair of an anode electrode and a cathode electrode forming a plurality of plasma discharge channels arranged on the second surface side of the plasma addressed liquid crystal display device and arranged so as to be orthogonally opposed to the first scan electrode group. A charge and hold type D / A converter for supplying a drive voltage to the first operation electrode group; and a second black and white D / A converter for supplying a drive voltage to the first operation electrode group. A common anode inversion drive voltage generating means for applying a common anode inversion drive voltage for relatively inverting the drive voltage to the scan electrode group, and a common anode inversion drive And amplitude of the pressure, the amplitude of the drive voltage to the first scan electrode group, reduces while at the same time takes the track, and has a contrast reduction adjusting means for performing contrast reduction adjustment.

According to the present invention, the charge / hold type D / A converter supplies a drive voltage to the first operation electrode group and a common anode inversion drive voltage for relatively inverting the drive voltage. The generating means applies a common anode inversion drive voltage to the second scan electrode group, and the contrast reduction adjusting means simultaneously adjusts the amplitude of the common anode inversion drive voltage and the amplitude of the drive voltage for the first scan electrode group. Contrast reduction adjustment is performed by reducing while tracking.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a transparent first scanning electrode group disposed on a first surface side of a plasma addressed liquid crystal display device and a second scanning electrode group disposed on the first surface side of the plasma addressed liquid crystal display device.
And a second scan electrode group consisting of a pair of an anode electrode and a cathode electrode forming a plurality of plasma discharge channels arranged so as to be orthogonally opposed to the first scan electrode group. In a normally black type plasma addressed liquid crystal display device provided with a charge and hold type D for supplying a drive voltage to a first operation electrode group,
/ A converter, a common anode inversion drive voltage generating means for applying a common anode inversion drive voltage for relatively inverting the drive voltage to the second scan electrode group, an amplitude of the common anode inversion drive voltage, This is a driving device for a plasma addressed liquid crystal display device having a contrast reduction adjusting means for reducing the amplitude of the driving voltage for the first scan electrode group while simultaneously performing tracking and performing contrast reduction adjustment.

[Specific Example of Embodiment of the Invention] Hereinafter, a specific example of the embodiment of the present invention will be described in detail with reference to the drawings. First, a specific circuit of a driving circuit of a liquid crystal display device including a normally black plasma addressed liquid crystal display device according to a specific example of the embodiment will be described in detail with reference to FIG. In the part corresponding to FIG.
The description is given with the same reference numerals. FIG. 1 is a circuit block diagram showing a part of an image system of a liquid crystal display device using the plasma addressed liquid crystal display device of this embodiment. The specific description of the plasma-addressed liquid crystal display device 36 of FIG. 1 and the liquid crystal display device using the same will use the description given with reference to FIGS.

In FIG. 1, NTSC (National Televis)
In the preceding stage of the demodulation unit 21, for example, a U / V tuner of the NTSC system, a BS (not shown),
A broadcast receiving means such as a tuner and one or more input terminals for inputting a standard video signal reproduced by an external device such as a VTR are provided.

Then, the standard video signal selected by the broadcast receiving means and the external standard video signal input from one or a plurality of input means are selected in the display device, and the NTS
It is supplied to the C demodulation unit 21.

The NTSC demodulation unit 21 demodulates the standard video signal into a luminance signal and a color difference signal, and supplies the luminance signal and the color difference signal to the double speed conversion unit 22. The demodulation unit 2
1 extracts a synchronizing signal from a luminance signal obtained by demodulation and supplies the synchronizing signal to an LCD (Liquid Crystal Display) controller 28 which will be described later. A clock is generated to synchronize various kinds of signal processing.

A frame memory capable of storing one frame of video signal (luminance signal and color difference signal) is provided in the double speed conversion section 22, and motion components are detected using this frame memory. Then, in the still image area of the video signal written in the frame memory, the video signal of the field at that time and the video signal of one horizontal period one field before are read twice consecutively at twice the writing speed.

In the moving image area of the video signal written in the frame memory, one of the field information at that time is stored.
An interpolated video signal generated by interpolation between the video signal in the horizontal period and the video signals in the upper and lower horizontal periods is read at double speed and converted to a 525H / 60 Hz non-interlace signal.

The video signal that has been subjected to the double-speed processing is subjected to color adjustment, hue adjustment, and the like in the video signal processing unit 23, and then red, green, and blue primary color signals are generated by inverse matrix processing. Each of the primary color signals generated by the video signal processing unit 23 is converted into digital red, green and blue video data V8 by an A / D converter 25 having an 8-bit quantization accuracy. .

The red, green, and blue image data V8 from the A / D converter 25 is supplied to a white balance adjusting unit 26.
Is supplied to the liquid crystal column driver 27 after the white balance processing is performed.

The liquid crystal column driver 27 latches video data for one horizontal period (for example, 854 pixels), that is, 854 pixels × 3 channels (red, green, blue), that is, video data V8 of 2562 pixels, and stores video data for each pixel. V
8 is held for one horizontal period. When a plasma discharge is generated in a predetermined scanning groove 7 (FIG. 3) by a plasma driver 32 to be described later, the readout is performed for each horizontal line.
Further, the D / A built in the liquid crystal column driver 27
The converter converts the signal to an analog signal,
(Plasma address type liquid crystal display) 36 (1) transparent drive electrode (ITO) 13 (red, green, blue drive electrode 13R,
13G, 13B) (FIG. 3).

The LCD controller 28 is configured to operate with a power supply of 5 V, for example, and counts a clock for driving the ramp waveform generator 29 based on an operation clock generated based on a synchronization signal from the NTSC demodulator 21. Then, an anode inversion pulse (horizontal pulse) H for driving the anode inversion driving circuit 30 and a plasma pulse for driving the plasma driver 31 to cause plasma discharge for each scanning groove 7 (horizontal line) are generated.

The count clock from the LCD controller 28 is supplied to a ramp waveform generator 29. The ramp waveform obtained here is supplied to a gain adjuster 41 for gain adjustment, and the gain-adjusted ramp waveform VR is adjusted. Is supplied to a liquid crystal column driver 27 including a charge and hold type D / A converter, which will be described later, and a PALC 36 (1)
Of the transparent column electrode 13 is driven.

After the output of the anode inversion drive circuit 30 is supplied to the gain adjuster 42 to adjust the gain, the output of the gain adjuster 42 is applied to the anode electrode 8 of the PALC (plasma address type liquid crystal display device) 36 (1). Supply.

Here, the gains are adjusted by the gain adjusters 41 and 42 so as to adjust the amplitude of the drive voltage (ramp waveform voltage) applied to the transparent electrode 13 and the amplitude of the common anode inversion drive voltage while simultaneously tracking. Lower, and perform contrast reduction adjustment.

The plasma driver 31 shown in FIG. 1 has a horizontal scanning line corresponding to about 480 lines constituting a screen of the NTSC system, that is, a PALC3 as shown in FIG.
6 (1) is sequentially selected to supply a plasma pulse, and a plasma discharge is generated by a power supply voltage of about −300 V applied to the cathode electrode 9.

That is, in synchronization with the double-speed video data V8 input to the liquid crystal column driver 27, the scanning grooves 7,
, 7,... Are sequentially discharged from the top to the bottom, and the discharge state is repeated for each field,
The PALC 36 (1) can be driven according to the video data described above. As a result, the input video signal can be displayed as a video.

The backlight 35 (2) is arranged as a light source for illuminating the PALC 36 (1) from the back side as shown in FIG. 2, and the emitted light beam passes through predetermined pixels of the PALC 36 (1). Thus, a display image is formed.
Further, picture adjustment can be performed by adjusting the brightness of the backlight 35 (2).

The microcomputer control unit 33 allows the user to operate the operation unit 32.
In accordance with a command input from, various controls such as the above-described tuning of each tuner, image adjustment, and power ON / OFF are performed.
In FIG. 1, the object to be controlled by the microcomputer control unit 33 and the microcomputer control unit 33 are connected by a broken line.

Next, the plasma (discharge) driver 32 will be described in detail with reference to FIG. In FIG. 8, PAL
An anode electrode 8 and a cathode electrode 9 of C37 (1) are also shown. For the plasma driver 32, a voltage of, for example, about -300 V from the plasma power supply Ep is used, and this voltage is applied to each line (for example, the first line L1 to L4).
(80th line L480: number of effective scanning lines) is applied to the cathode electrodes 9 (1), 9 (2),..., 9 (480) through the switching means and the current source. The cathode electrodes 9 (1) to 9 (480) are arranged as switching elements for plasma discharge, for example, NMOS.
(N channel MOS) Transistor Tr (1), Tr
(2),..., Connected to the drain of Tr (480).

NMOS transistors Tr (1) to Tr
The source electrodes of (480) are commonly connected, and are further connected to a plasma power supply Ep through a current source Si of, for example, about 100 mA.
And is controlled so that the current at the time of plasma discharge becomes constant, so that stable plasma discharge is performed. Cathode electrode 9 (1), 9
, 8 (480) corresponding to the anode electrodes 8 (1), 8 (2),.
Are commonly connected to the positive electrode of the plasma power supply Ep.
The NMOS transistors Tr (1) to Tr (48)
The positive electrode pulse (plasma discharge pulse) of, for example, about 10 μsec supplied from the LCD controller 28 is sequentially applied to the gate electrode 0) line by line.

NMOS transistors Tr (1) to Tr
When the plasma pulse from the LCD controller 28 is sequentially applied to the gate electrode of (480), first, for example, the anode electrode 8 (1) and the cathode electrode 9 ( A plasma discharge occurs between 1) and thereafter, a plasma pulse is sequentially applied to the cathode electrodes 9 (1) to 9 (480) from the first line L1 to the 480th line L480 in synchronization with the pixel signals for one line. This makes it possible to form an image for one field.

Next, the phase relationship between the video drive signal (write video data) and the plasma discharge pulse supplied to the PALC 1 will be described with reference to FIG. If the scanning period for one line is, for example, 32 μsec, for example, the NMOS corresponding to the first line L1 at the timing shown in FIG. 9B.
When a positive plasma pulse voltage of 10 μsec width is applied to the gate electrode of the transistor Tr (1), the cathode electrode 9 corresponding to the first line L1 as shown in FIG. 9C.
In (1), a negative pulse voltage having a voltage of −300 V and a width of 10 μsec is applied, and a plasma discharge occurs in the first scanning groove 7. In a state where the scanning groove 7 is plasma-discharged, a maximum of 60 V image signal sampled and held for each pixel shown in FIG. 9A is continuously applied to the drive electrode (ITO) 13 for, for example, about 20 μsec. By doing so, the video signal for one line can be written to the PALC 37 (1) (FIG. 1).

Then, in the subsequent second line L2, as shown in FIG. 9D, when a positive plasma pulse voltage of 10 μsec width is applied to the gate electrode of the NMOS transistor Tr (2), as shown in FIG. A negative pulse voltage having a voltage of -300 V and a width of 10 [mu] sec is applied to the cathode electrode 9 (2) corresponding to the line L2, and a plasma discharge occurs in the next scanning groove 7. In the state where the scanning groove 7 is plasma-discharged, as shown in FIG. 9A, sample-and-hold is performed for each pixel, and inverted data of the video signal of the second line up to 60 V is maintained for, for example, about 20 μsec. Then, it is applied to the drive electrode (ITO) 13. Thus, in the first field, the inversion drive is performed alternately for each of the odd-numbered lines and the even-numbered lines, and in the next field, the data is alternately and reversely driven in the opposite phase.
The AC drive of (1) is realized to prevent the deterioration of the liquid crystal molecules due to the continuous application of the DC voltage.

That is, as shown in FIG. 7, in the first field of FIG. 7A, the inversion drive is alternately performed for each of the odd-numbered lines and the even-numbered lines. In the next field of FIG. By driving, AC driving of the liquid crystal display device is realized, and by continuously applying a DC voltage, deterioration of liquid crystal molecules is prevented.

By sequentially writing 480 lines of video signals to the PALC 37 (1) at such timing, an image for one field can be formed and displayed.

FIG. 10 shows a circuit configuration of a charge / hold type D / A converter built in the liquid crystal column driver 27 for holding video data. FIG. 11 shows operation waveforms. Will be described. A shift register (not shown) for sequentially storing one line of video signal for each pixel in the liquid crystal column driver 27 includes:
At the same time as capturing the last video data, the video data is transferred to the video data latch circuit 45 prepared for the number of pixels of one line of the D / A converter. Next, the data A of the up / down count circuit 47 for counting 128 counter clocks and the video data B of the video data latch circuit 45 are compared in the comparator circuit 46. Q1 is turned on to charge the charge capacitor 48 with the ramp waveform voltage VR. Note that this transistor Q1
A diode D1 is connected between the drain and the source of the D1. As shown in FIG. 10, for example, when the video data is 125
In this case, the ramp waveform voltage VR is charged to the charge capacitor 48 until the 126th count clock, and the voltage of the charge capacitor 48 at the moment when the comparator output in FIG. 11C becomes low is held.

The D / A-converted voltage is reduced in output impedance by an NMOS transistor Q2 constituting a buffer output stage, and is applied to each column drive electrode (ITO) 13
Supplied to VDD is a drain power supply. Thus, the operation of the charge and hold type D / A conversion is performed.

By the way, the transmission voltage (VT) of the normally black plasma addressed liquid crystal display device versus the driving voltage.
As shown in FIG. 6, when the driving voltage is 10 V or less, the transmittance is 0, and when the driving voltage exceeds 10 V, the characteristic curve is:
When the transmittance increases substantially linearly and the drive voltage becomes approximately 70 V, the transmittance becomes 100%, and even when the drive voltage exceeds approximately 70 V, the transmittance is saturated at 100%.

Therefore, when the anode electrode 8 is to be driven directly by a video signal of ± 70 V, about 140 Vp
A drive waveform of p is required, and there is a problem that power consumption is greatly increased, including a problem that a semiconductor process becomes expensive. For this reason, in general,
A method called a common anode inversion drive is used.
12 and 13 show the principle of operation.

FIGS. 12A and 12B each show a luminance of 100 IR.
7 shows drive waveforms of ITO and the anode electrode in the case of E. In the case of writing a white signal of ± 70 V with a luminance of 100 IRE, a 60 V video signal is directly applied to the transparent electrode (ITO) 13 on the positive electrode side as shown in FIG.
, A voltage of -10 V (lower limit potential) is simultaneously applied to the common electrode, that is, the common anode electrode.

In the next line, it is necessary to write an inverted black signal of -70 V for inversion driving. As shown in FIG. 12A, first, the video signal is inverted by a 30 V line of the midpoint potential. After being converted to a 0 V video signal, the signal is applied to the transparent electrode (ITO) 13. At the same time, when the inverted signal is being applied, a voltage of +70 V (upper limit potential) is applied to the common anode electrode as shown in FIG. 12B. In other words, when the electrode potential of the common anode is considered as a reference, as shown in the liquid crystal drive voltage waveform when the anode potential is used as a reference in FIG.
This is equivalent to the direct drive of ± 70 Vpp described with reference to FIG.

Next, FIGS. 14 and 15 will be described. FIGS. 12A and 12B show the drive waveforms of the ITO and anode electrodes, respectively, when the luminance is 0 IRE. Brightness is 0I
In the case of writing a black signal of RE, as shown in FIG. 14A, a video signal of 0 V is directly applied to the transparent electrode (IT
O) A voltage of -10 V is applied to the common electrode, that is, the common anode electrode at the same time.

In the next line, it is necessary to write an inverted white signal of -10 V for inversion driving. As shown in FIG. 14A, first, the video signal is applied to the midpoint potential 30 V line. After being converted into an inverted video signal of 60 V, it is applied to the transparent electrode (ITO) 13. As shown in FIG. 14B, at the same time, when this inverted signal is being applied, a voltage of +70 V is applied to the common anode electrode. That is, when the electrode potential of the common anode is considered as a reference, the drive waveform is relatively ± 10 V as shown in the liquid crystal drive voltage waveform when the anode potential is used as a reference in FIG.

In the above-described common anode inversion driving method, 1
In order to reduce the contrast of the white signal of 00IRE to 1/2, conventionally, as shown in FIG.
The level of the video signal is reduced to 1/2 by the gain adjuster 24 in the preceding stage of the converter 25, and as shown in FIG. 22A, the drive voltage for the transparent electrode (ITO) 13 is reduced to 1/2 of 30V.
To be reduced. FIG. 22B shows the anode inversion drive voltage in this case. The conventional liquid crystal driving voltage waveform based on the anode potential in this case is ± 40 V as shown in FIG.

However, in this conventional example, the signal level of 256 steps to reduce the contrast to 1/4 of the minimum value is reduced to 1/4 of 64 gradations, and the S / N of the displayed image is reduced. Deteriorates.

Therefore, in a specific example of the embodiment of the present invention, when the contrast is reduced to, for example, コ ン ト ラ ス ト, the ramp waveform of the charge and hold type D / A converter built in the liquid crystal column driver 27 is used. The amplitude of the ramp waveform (voltage) VR applied to the input terminal is shown in FIGS.
As shown in FIG.
pp, and the output voltage that is D / A converted by the charge and hold type D / A converter built in the liquid crystal column driver 27 is similarly reduced to Ｖ, ie, 30 V.

As a result, the transparent electrode (IT
O) The drive voltage of 13 becomes 1/2 V as shown in FIG. 19A, and the voltage applied to the common anode electrode at this time is -10 V (lower limit potential) as shown in FIG. 19B.
Voltage. 19A, the voltage applied to the common anode electrode at this time is 0 V, which is inverted with the midpoint of 15 V as the axis of symmetry, as shown in FIG. 19A. 40V as shown
(Upper limit potential). The liquid crystal drive voltage waveform based on the anode potential is shown in FIG.
± 40V.

On the other hand, as shown in FIGS. 1 and 16, the anode inversion drive circuit also adjusts the power supply voltage supplied to the drive circuit to a gain adjuster 42, that is, a variable power supply 43 (variable DC voltage is 15 to 60 Vcd). In order to absorb the threshold voltage at which the liquid crystal transmittance rises, the voltage is twice as large as 10 V from the bias power supply 44.
The bias DC voltage of 0 V is added to the variable voltage from the variable power supply 43.

Here, a middle point matching circuit as shown in FIG. 18 is provided so as to obtain a liquid crystal driving voltage having a symmetrical waveform even when the amplitude is reduced, and the middle point matching circuit is used to generate a ramp waveform. The detection of the reference potential of the power supply is varied as shown in the graph of FIG. In FIG. 17, contrast adjustment (%)
The characteristic shows the ramp waveform power supply variable reference potential, the ramp waveform amplitude, and the anode drive power supply voltage with respect to (in the range of 25 to 100%). There is a bias voltage of 20 V between the ramp waveform amplitude and the anode drive power supply voltage.

The midpoint potential matching circuit for generating the upper / lower potential in FIG. 18 will be described. In this midpoint potential matching circuit,
The feedback circuit formed by the operational amplifier (OP amplifier) 55 operates so that the midpoint of the anode inversion drive power supply and this variable potential of the ramp waveform generation power supply match.

That is, regarding the anode inversion drive voltage,
A power supply voltage of 50 Vdc obtained by adding a bias level of 20 V and a power supply voltage of 30 V, which is ２ of the power supply voltage at the time of 100% contrast, has a middle point coincidence circuit with a middle point potential of 15 V as a symmetric axis, an upper potential of 40 V and a lower potential of The side potential is fixed at -10V. The determined voltage is switched by the anode inversion switch (SW) 58 every horizontal cycle (H) and applied to the anode electrode at the timing of FIG. 19B by the H pulse supplied from the input terminal 59.

Therefore, when the contrast of a signal having a luminance of 100 IRE is reduced to 1/2 (50%), the liquid crystal driving voltage based on the anode potential is ± 40 V in both positive and negative directions as shown in FIG. And the contrast can be reduced to 1/2 (50% contrast) while maintaining the resolution of 256 gradations.

The midpoint potential matching circuit for generating the upper / lower potential in FIG. 18 will be further described. This circuit comprises a floating power supply for anode inversion drive and a power supply for ramp waveform. In the anode inversion driving floating power supply, a series circuit of voltage dividing resistors 53 and 54 between power supply terminals 51 and 52, an operational amplifier (OP amplifier) 55, and an NPN
The transistor 56 and the series circuit of the PNP transistor 57 are connected in parallel. The midpoint P between the resistors 53 and 54 is connected to the inverting input terminal of the operational amplifier 55, and its output terminal is connected to each base of the transistors 56 and 57. The voltage from the terminals 51 and 52 is switched every horizontal cycle by the anode inversion switch (SW) 58 by the H pulse (FIG. 19B) supplied from the input terminal 59, and the switching output voltage is supplied to the anode electrode. .

Next, a ramp waveform power supply will be described. A series circuit of a fixed resistor 61, a variable resistor (potentiometer) 62 and a resistor 63 constituting a variable reference potential generator 60 and an NPN transistor 64 are connected between a terminal 66 to which a DC voltage of 60 Vdc is applied and ground. And P
A series circuit of NP-type transistors 65 is connected in parallel, and the movable terminal of the variable resistor 62 is connected to the bases of the transistors 64 and 65 and the non-inverting input terminal of the operational amplifier 55 of the floating power supply for anode inversion driving. Also, a transistor 56 of a floating power supply for anode inversion driving,
Both emitters 57 and the emitters of the transistors 64 and 65 of the ramp waveform power supply are connected to each other.

[0085]

According to the present invention, a transparent first scan electrode group disposed on the first surface side of the plasma addressed liquid crystal display device and the second scan electrode group disposed on the first face side of the plasma addressed liquid crystal display device are provided.
And a second scan electrode group consisting of a pair of an anode electrode and a cathode electrode forming a plurality of plasma discharge channels arranged so as to be orthogonally opposed to the first scan electrode group. In a normally black type plasma addressed liquid crystal display device provided with a charge and hold type D for supplying a drive voltage to a first operation electrode group,
/ A converter, a common anode inversion drive voltage generating means for applying a common anode inversion drive voltage for relatively inverting the drive voltage to the second scan electrode group, an amplitude of the common anode inversion drive voltage, Since there is provided a contrast reduction adjusting means for performing the contrast reduction adjustment by simultaneously reducing the amplitude of the drive voltage for the first scanning electrode group while tracking, even if the contrast of the display image is reduced, the S / N ratio is reduced. A driving device for a plasma addressed liquid crystal display device without deterioration can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a driving device (driving circuit) of a plasma addressed liquid crystal display device according to a specific example of an embodiment of the present invention.

FIG. 2 is an exploded perspective view showing a plasma addressed liquid crystal display device used in a specific example.

FIG. 3 is a partially cutaway perspective view showing a plasma addressed liquid crystal display device used in a specific example.

FIG. 4 is a partially cutaway perspective view showing a plasma addressed liquid crystal display device for explaining generation of a plasma channel by plasma discharge.

FIG. 5 is a circuit diagram showing an A plasma channel. B is a circuit diagram showing an equivalent circuit of the plasma channel.

FIG. 6 is a drive voltage versus transmittance (VT) characteristic curve diagram of a normally black plasma addressed liquid crystal display device (liquid crystal device) in a specific example of an embodiment of the present invention.

FIG. 7 is a polarity diagram of line inversion of a line inversion driving method in a specific example of an embodiment of the present invention.

FIG. 8 is a circuit diagram showing a circuit of a plasma discharge driver used in a specific example of an embodiment of the present invention.

FIG. 9 is a timing chart illustrating a phase relationship between video data written to a liquid crystal display device and a plasma discharge pulse. FIG. 5 is a waveform diagram showing AD / A converted video output data. FIG. 6 is a waveform diagram showing a gate voltage of an NMOS transistor on a B1 line. It is a waveform diagram which shows the cathode waveform of C1 line. FIG. 9 is a waveform chart showing the gate voltage of the NMOS transistor on the D2 line. FIG. 9 is a waveform chart showing a cathode voltage of the NMOS transistor on the E2 line.

FIG. 10 is a circuit diagram showing a charge-and-hold type D / A converter used in a specific example of an embodiment of the present invention.

11 is a timing chart at the time of operation of the D / A converter when the video data is 240. FIG. FIG. 6 is a waveform diagram showing an A count clock. It is a waveform diagram which shows BD / A conversion output. It is a waveform diagram which shows C comparator output.

FIG. 12 is a timing chart showing the operation principle of the common anode inversion driving method, and is a diagram showing actual driving waveforms when the luminance is 100 IRE. A is a waveform of an ITO drive voltage. B is a waveform of an anode inversion drive voltage.

FIG. 13 is a timing chart illustrating the operation principle of the common anode inversion driving method, and is a diagram illustrating a liquid crystal driving voltage waveform based on an anode potential.

FIG. 14 is a timing chart showing the operation principle of the common anode inversion driving method, and is a diagram showing an actual driving waveform when the luminance is 0IRE. A is a waveform of an ITO drive voltage. B is a waveform of an anode inversion drive voltage.

FIG. 15 is a timing chart showing the operation principle of the common anode inversion drive method, and is a diagram showing a liquid crystal drive voltage waveform based on the anode potential.

FIG. 16 is a block diagram showing a drive voltage control circuit according to a specific example of the embodiment of the present invention;

FIG. 17 is a characteristic diagram showing a relationship between contrast and each control voltage.

FIG. 18 is a circuit diagram showing a midpoint potential matching circuit for generating a midpoint potential for generating an upper / lower potential in the anode inversion drive circuit according to a specific example of the embodiment of the present invention;

FIG. 19 shows a luminance of 100I at a contrast of 50%.
FIG. 9 is a diagram illustrating an actual driving waveform in the case of an RE signal. A is a waveform of an ITO drive voltage. B is a waveform of an anode inversion drive voltage.

FIG. 20 shows a luminance of 100I at a contrast of 50%.
FIG. 9 is a diagram showing an actual driving waveform in the case of an RE signal and a liquid crystal driving voltage waveform when the anode potential is used as a reference.

FIG. 21 is a block diagram showing a driving device (driving circuit) of a conventional plasma addressed liquid crystal display device.

FIG. 22 shows a luminance of 100I at a contrast of 50%.
FIG. 9 is a diagram showing a driving waveform of a conventional example in the case of an RE signal. A is a waveform of an ITO drive voltage. B is a waveform of an anode inversion drive voltage.

FIG. 23 shows a luminance of 100I at a contrast of 50%.
FIG. 11 is a diagram showing a liquid crystal drive voltage waveform when the anode signal is used as a reference in the conventional drive waveform in the case of the RE signal.

[Explanation of symbols]

1 PALC liquid crystal display device, 2 backlight, 3, 4
Polarizing filter, 5 plasma substrate (back glass), 6
Partition walls (ribs), 7 scanning grooves (plasma channels), 8
Anode electrode, 9 Cathode electrode, 10 Insulating layer (thin glass), 11 Liquid crystal layer, 12 Color filter, 1
3 Transparent electrode (ITO thin film), 14 front glass, 21
NTSC demodulator, 22 frame double speed conversion circuit, 23
Video signal processing unit, 25 A / D converter, 26 White balance adjustment unit, 27 LCD column driver, 28 L
CD controller, 29 ramp waveform generator, 30 anode inversion drive circuit, 31 plasma driver, 32 operation unit, 33 microcomputer control unit, 34 power supply circuit, 35
Backlight, 36 plasma-addressed liquid crystal display device, 41 gain adjuster (for ramp waveform), 42 gain adjuster (for anode), 43 variable power supply circuit (for anode), 45 video data latch circuit, 46 comparator circuit, 47 Up-down counter circuit.

Claims (1)

[Claims] 1. A first embodiment of a plasma addressed liquid crystal display device.
A transparent first scanning electrode group disposed on the second surface side of the plasma addressed liquid crystal display device, and a transparent first scanning electrode group disposed on the second surface side of the plasma addressed liquid crystal display device. A normally black plasma addressed liquid crystal display device comprising a second scan electrode group comprising a pair of an anode electrode and a cathode electrode forming a plurality of arranged plasma discharge channels, wherein the first operation electrode A charge and hold type D / A converter for supplying a drive voltage to the group; a common anode inversion drive voltage for applying a common anode inversion drive voltage for relatively inverting the drive voltage to the second scan electrode group Generating means for reducing the amplitude of the common anode inversion drive voltage and the amplitude of the drive voltage for the first scan electrode group while simultaneously tracking. And a contrast reduction adjusting means for performing contrast reduction adjustment.