JP3525762B2 - Image signal processing circuit, electro-optical device and electronic apparatus using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing circuit for outputting an image signal to an electro-optical device having a plurality of pixels, and an electro-optical device using the same.

[0002]

2. Description of the Related Art For example, in an active matrix type liquid crystal display device in which a drive circuit (driver) is built in on a liquid crystal panel substrate, image data is sent to the liquid crystal panel via an image signal line and built in the liquid crystal panel. The drive circuit for sampling the pixel data contained in the image data sent to the image signal line. In the liquid crystal panel, the drive circuit sequentially samples the data of each pixel and outputs the sampled image data to the data signal line to write predetermined image data to each pixel of the panel to display an image.

[0003]

However, when the image data amount in the image signal is increased and the writing cycle of the image data is shortened especially due to the high definition of the screen,
For example, due to the capacitance formed in each part of the panel, the resistance of the wiring, etc., the voltage level sent to the image signal line cannot completely follow the image data input to the liquid crystal panel,
There is a problem that the voltage change of the image signal line is delayed and deviates from the target voltage.

If there is such a voltage change delay of the image signal line, the original voltage level of the image data cannot be sampled at the sampling timing of the image data by the drive circuit, and the voltage of the image data applied to the pixel is reduced. Is deviated from the original voltage level, so-called ghost (a phenomenon in which an image is displayed in a thin double display) or the like occurs as an image display, and the image quality of the liquid crystal panel is deteriorated.

An object of the present invention is to provide an image signal processing circuit of an electro-optical device which can obtain a good display image quality without generation of a ghost and the like, and an electro-optical device using the same.

[0006]

[0007]

[0008]

[0009]

[0010]

An image signal processing circuit of an electro-optical device according to the present invention images an electro-optical device including a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning lines. In an image signal processing circuit for transmitting a signal, a means for parallelly outputting a plurality of image signals obtained by sequentially sampling image signals input in time series to a plurality of image signal lines, and outputting to a predetermined image signal line And a correction unit that corrects the image signal output to another image signal line by a correction value based on a change in the value of the image signal.

According to the image signal processing circuit of the electro-optical device of the present invention, when one image signal is corrected, the change of the other image signal is reflected, so that the change of the one image signal is different. It is possible to improve the image quality of the display image of the electro-optical device that influences the value of the image signal.

The image signal processing circuit of the electro-optical device according to the present invention sends an image signal to an electro-optical device having a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning lines. In the processing circuit, a means for parallelly outputting a plurality of image signals obtained by sampling image signals input in time series to a plurality of image signal lines, and the plurality of images output to the plurality of image signal lines A differentiation circuit that outputs a signal corresponding to the sum of the differential components of the signal,
A correction unit that adds a correction value corresponding to a signal corresponding to the sum of the differential components to the plurality of image signals is provided.

According to the image signal processing circuit of the electro-optical device of the present invention, when the plurality of image signals are corrected, the overall change of the plurality of image signals is reflected, so that the image signals affect each other. It is possible to improve the image quality of the display image of the electro-optical device that gives each other. It is particularly effective when the image signals of a plurality of image signal lines are simultaneously output to a plurality of data signal lines.

Further, the image signal processing circuit of the electro-optical device of the present invention sends an image signal to the electro-optical device having a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning lines. An image signal processing circuit,
Means for parallelly outputting a plurality of image signals obtained by sampling the image signals input in time series to a plurality of image signal lines, and a composite signal obtained by combining the plurality of parallel output image signals are input. Differentiating circuit, and the signals output from the differentiating circuit are input to the means for outputting in parallel to correct each of the plurality of image signals.

Also in this image signal processing circuit, when the one image signal is corrected, the change of the other image signal is reflected, so that the change of the one image signal affects the value of the other image signal. It is possible to improve the image quality of the display image of the electro-optical device that gives each other.

An image signal processing circuit for sending an image signal to an electro-optical device having a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning lines, wherein the images are inputted in time series. A plurality of image signals obtained by sampling the signal, a means for parallel output to a plurality of image signal lines, a differentiating circuit to which a composite signal obtained by combining the plurality of parallel output image signals is input, It is characterized in that it is provided with an adder circuit for respectively adding the signal output from the differentiating circuit and the plurality of image signals output in parallel.

According to the image signal processing circuit of the electro-optical device of the present invention, when the plurality of image signals are corrected, the overall change of the plurality of image signals is reflected. It is possible to enhance the image quality of the display image of the electro-optical device that affects each other. It is particularly effective when the image signals of a plurality of image signal lines are simultaneously output to a plurality of data signal lines.

Further, in the electronic equipment using the electro-optical device of the present invention, since the ghost in which the display is doubled is eliminated, the display quality of the electronic equipment can be improved.

[0019]

DETAILED DESCRIPTION OF THE INVENTION (First Embodiment) FIG.
The first embodiment in which the image signal processing circuit of the electro-optical device according to the invention is applied to the active matrix type liquid crystal device will be described with reference to FIGS.

The image signal processing circuit 200 of the first embodiment shown in FIG. 1 produces a parallel image signal from a serial image signal and outputs it as image data to a liquid crystal panel. The serial image signal VID is an analog signal in which data corresponding to each pixel of the liquid crystal panel is arranged in time series, and the image signal processing circuit 200 sequentially outputs the image signal VID in accordance with the timing when the image data of each pixel is input. To sample. Then, this image information is serial-parallel converted into six parallel image signals having a data time length longer than the sampling period of the image signal VID. That is, the image signal processing circuit 200 has a function of extending the data time length of the image information of the serial image signal VID, and a so-called serial-parallel conversion function of converting the serial image signal VID into parallel parallel image signals. It is a thing.

The image signal processing circuit 200 includes six image signal sampling circuits 201a to 201f, a sampling pulse generator 209 for sending sampling pulses SPa to SPf to the image signal sampling circuits 201a to 201f, respectively, and an image. A clamp pulse generator 210 for sending a clamp pulse CP to each of the signal sampling circuits 201a to 201f.

Image signal sampling circuits 201a-20
The image signal VID is input to each of 1f. Then, the six image signal sampling circuits 201a to 201
f sequentially samples the image data of the image signal VID by sampling pulses SPa to SPf in synchronization with the transmission cycle thereof, converts the image data into six parallel image signals, and uses the parallel image signals as image data in parallel image signal lines. Output to Data1 to Data6.

A dot clock DC (clock synchronized with data transmission of the image signal VID) is input from the timing circuit 300 (see FIG. 7) to the sampling pulse generator 209 and the clamp pulse generator 210, respectively. The sampling pulse generation unit 209 and the clamp pulse generation unit 210 respectively divide the sampling clock DC based on the dot clock DC, etc.
SPf and clamp pulse CP are generated.

As shown in FIG. 2, each image signal sampling circuit 201 (201a to 201f) has a control unit 202 for inputting a serial image signal VID and a sampling pulse SP (SPa to SPa to output signal of the control unit 202).
f) A sample and hold circuit 204 for sampling at the timing, an amplifier 205 for amplifying the difference between the output signal of the sample and hold circuit 204 and the reference voltage V _REF, and a differential component of the output signal of the sample and hold circuit 204 are output. A clamp switch 207 provided between the differentiating circuit 206 and the amplifier 205 and the control unit 202.
And a clamp capacitor 208 provided between the control unit 202 and the differentiating circuit 206. Differentiating circuit 206
Is a differential amplifier 2 whose positive-phase input terminal is connected to ground
06a, an input capacitor 206b connected to the negative-phase input terminal, an input resistor 206c inserted and connected between the input capacitor 206b and the output terminal of the sample-hold circuit 204, a negative-phase input terminal of the amplifier 206a, and an output. It is composed of a feedback resistor 206d connected between the terminals. Further, the clamp switch 207 clamps at the timing of the clamp pulse CP. The output terminals of the sample hold circuits 204 of the image signal sampling circuits 201 are connected to the parallel image signal lines Dat.
It is connected corresponding to any of a1 to Data6.

The sample hold circuit 204 of each image signal sampling circuit 201 is shown in FIG. Control unit 2
02, an input buffer 204a for inputting the output signal of 02, an output buffer 204b provided on the output side, a sample hold capacitor 204c connected between the positive phase input terminal of the output buffer 204b and the ground, an input buffer 204a and And a sampling switch 204d inserted between the output buffers 204b. Each buffer is configured by inputting the signal to be amplified to the positive phase input terminal, and connecting the output terminal and the negative phase input terminal. Further, the sampling switch 204d has a sampling pulse SP.
The output of the input buffer 204a is sampled by closing the switch at the same timing. Output buffer 20
The output of 4b becomes the output of the sample hold circuit 204.

Next, the operation of the image signal processing circuit 200 will be described.

The sampling circuit 201 is obtained by adding a differentiating circuit 206 to the conventional sampling circuit 201A shown in FIG. In the conventional sampling circuit 201A, the same elements as those of the sampling circuit 201 are designated by the same reference numerals. Hereinafter, the operation of the sampling circuit 201 will be described together with the operation of the sampling circuit 201A.

The clamp switch 207 of the sampling circuit 201 is periodically, for example, every time when sampling of the image signal for the number of pixels corresponding to one scanning line of the liquid crystal panel is completed (for example, every one horizontal scanning period, more specifically). The clamp pulse CP is input during each horizontal blanking period), and the clamp switch 207 is closed only during that period. While the clamp switch 207 is closed, the clamp capacitor 208 is charged by the amplifier 205, and the control unit 20
The terminal voltage of the clamp capacitor 208 on the side connected to 2 becomes the same voltage as the output voltage of the amplifier 205. The output voltage of the amplifier 205 is the parallel image signal lines Data1 to Data1.
It is a monitor voltage for canceling the offset between Data6 and is a difference voltage between the reference voltage V _REF and the output voltage of the sample hold circuit 204.

In the control unit 202, the reference voltage of the image signal output from the sampling circuit is the reference voltage of the clamp capacitor 208 of the image signal output from the sampling circuit during the period when there is no AC component of the image signal and the DC component is input as the image signal VID, such as the horizontal blanking period. The DC voltage level of the image signal is offset controlled so as to change according to the terminal voltage, and the offset-controlled image signal is output to the sample hold circuit 204. By performing the offset control operation by the clamp in the control unit 202, feedback control is performed so that the reference voltage V _REF and the reference voltage of the image signal have the same value. As a result, the reference voltages for reversing the polarities of the image signals output to the parallel image signal lines Data1 to Data6 are controlled to be V _REF , so that the offset between the parallel image signal lines can be removed.

The specific configuration of the control unit 202 is the same as that of the offset control unit 211 of FIG. 8 described later. Figure 8
The control unit 202, like the control unit 211 of FIG.
The bipolar transistor 211a having the ID input to the base terminal and the differential component combining unit 211b connected to the emitter side of the transistor 211a are provided. The differential component combiner 211b is a current source that changes the current value according to the output voltage of the clamp capacitor 208. The bipolar transistor 211a and the differential component combiner 211b form an inverting amplifier circuit for the image signal VID. The differential component combiner 211b variably controls the amount of current flowing from the bipolar transistor 211a according to the output voltage of the clamp capacitor 208. The DC level of the image signal output from the control unit 202 to the sample hold circuit 204 can be changed by changing the amount of current in the differential component synthesis unit 211b. Therefore, the output signal superimposed on the image signal VID can be output from the control unit 202 using the DC voltage level component corresponding to the output voltage of the clamp capacitor 208 as a correction value. The differential component combiner 211b is configured as a variable current source, for example, the clamp capacitor 20.
The base is variably controlled according to the voltage obtained by adding or subtracting the voltage from 8 to the constant voltage, and the current source transistor changes the current value. The differential component synthesizing unit 211b reduces the current value when the DC voltage output from the sample hold circuit 204 in the horizontal blanking period increases, and reduces the current value.
The voltage value input to 04 is increased. On the other hand, when the fall of the output voltage is differentiated, the current value is increased to decrease the voltage value input to the sample hold circuit 204.
Since the voltage value of the clamp capacitor 208 is held during the horizontal scanning period, the differential component synthesizing unit 211b continues to supply the constant current according to the voltage value during the next horizontal scanning period.

The image signal VID may be provided with a polarity reversing circuit for reversing the changing direction of the image signal for each image data or each scanning line. In this case, the reference voltage of the image signal can be used as the amplitude center voltage of the polarity inversion (inversion of the signal voltage changing direction) of the image signal, and in this case, the polarity of the image signal is inverted around the reference voltage V _REF by the clamp. Can be output. Further, the reference voltage of the image signal can be set near the intermediate voltage of the voltage range in which the image signal can be gradation. in this case,
In accordance with the polarity inversion of the image signal, the voltage range in which gradation can be performed switches between the positive side and the negative side. Therefore, as the reference voltage V _REF , the intermediate voltage of each voltage range is changed according to the polarity inversion switching. Therefore, it is necessary to switch the setting. As a result, the voltage of each image signal can be changed from each intermediate voltage between the positive voltage range and the negative voltage range, so that the change to the intermediate gradation voltage level is facilitated and the intermediate gradation is easily produced.

The clamp switch 207 is a period during which a DC voltage without an effective image signal is output during the horizontal blanking period, the output value of the sample hold circuit 204 does not change, and the output voltage of the differentiating circuit 206 is 0. The operation is controlled so that the clamp switch 2 is closed during the period.
When 07 is closed, the terminal of the clamp capacitor 208 on the output end side of the differentiating circuit 206 is equivalently grounded. Note that the clamp switch 207 is opened during the period in which the image signal is present during the horizontal scanning period during which the image signal is sampled.

The sampling switch 204d shown in FIG. 3 includes a sampling pulse SP from the sampling pulse generator 209 at a cycle of once every six dot clocks.
(SPa to SPf) and sampling pulse S
While P is input, the sampling switch 204d is closed. The sample and hold capacitor 204c is charged while the sampling switch 204d is closed. As a result, the output value of the control unit 202 is sampled as the charging voltage value of the sample hold capacitor 204c. The charge voltage value of the sample hold capacitor 204c is output via the output buffer 204b.

Six sampling circuits 201a to 201
By sequentially applying the sampling pulses SPa to SPf to the six sample and hold circuits 204 of f at a timing shifted by one image data in synchronization with the dot clock DC, as shown in FIG.
It is possible to sequentially capture six pieces of image data shifted by 1 pixel in 1a to 201f and obtain a parallel image signal having a data time length of 6 pixels.

As shown in FIG. 5, the parallel image signal line D
A parallel image signal obtained by extending the time length of the (6N + 1) th image data is output to data1 and a parallel image signal obtained by extending the time length of the (6N + 2) th image data to the parallel image signal line Data2. The parallel image signal is obtained by expanding the time length of the (6N + 3) th image data on the parallel image signal line Data3 and the time of the (6N + 4) th image data is obtained on the parallel image signal line Data4. The parallel image signal obtained by extending the length is the parallel image signal obtained by extending the time length of the (6N + 5) th image data on the parallel image signal line Data5.
A parallel image signal obtained by extending the time length of the (6N + 6) th image data is output to the parallel image signal line Data6. “N” is an integer of 0 or more.

Parallel image signal lines Data1 to Data
6 parallel image signals are dot clock DC
It switches sequentially every 6 cycles. In FIG. 5, the parallel image signal obtained by sampling and the original image data VID
Corresponding relationships are indicated by attaching the same image data number to and.

The differential circuit 206 shown in FIG. 2 outputs the differential component of the output value of the sample hold circuit 204, and changes the voltage at one end of the clamp capacitor 208. While the clamp switch 207 is open, the voltage (the amount of accumulated charge) between both terminals of the clamp capacitor 208 is maintained at a substantially constant value, so the other end of the clamp capacitor 208 (the terminal connected to the control unit 202). If the voltage at one end of the clamp capacitor 208 fluctuates due to the differential component,
The voltage changes by the same amount accordingly. The differential component synthesis unit 211b (see FIG. 8) of the control unit 202 decreases the current value when the voltage from the clamp capacitor 208 increases, and increases the voltage level of the image signal output to the sample hold circuit 204. The voltage level of the image signal sampled and held by the sample and hold circuit 204 is shifted in the direction of increasing the voltage level if the voltage change direction from the previous image signal is a voltage increase, and the change is emphasized. Like On the other hand, the differential component synthesis unit 211b decreases the voltage level of the image signal output to the sample hold circuit 204 by increasing the current value when the voltage from the clamp capacitor 208 decreases, and as a result, the sample hold circuit 204 performs sampling. The voltage level of the held image signal is shifted in the direction of decreasing the voltage level if the voltage change direction from the previous image signal is voltage decrease, and the change is emphasized. Therefore, the image signal output from the control unit 202 of the sampling circuit 201 is the differential circuit 20.
The differential component fed back via 6 is superposed.

As described above, in the portion where the voltage value of the image signal VID rises, the voltage higher than the original image signal and in the portion where the voltage value of the image signal VID falls lower than the original image signal, respectively. By sampling the output signal of the control unit 202 and the output signal of the control unit 202 by the sample hold circuit 204, the output value of the sample hold circuit 204 reflects the superposition of the differential waveform. In particular, since the differential component is extracted, if the change amount of the image data is large, the differential component also shows a corresponding change. Therefore, the larger the change, the larger the shift amount of the image signal.

In FIG. 6, the data time length of the image signal VID and the parallel image signal line Da are shown in order from the top to the bottom.
The data time length of the image signal output to ta1, the waveform example of the image signal Data1 when the conventional sampling circuit 201A (see FIG. 4) is used, the image signal D when the sampling circuit 201 of the present invention is used
Each waveform example of ata1 is shown. In the conventional waveform example and the waveform example of the present invention, the same image signal VID is input to the sampling circuit 201 shown in FIG.
3A and 3A are waveforms obtained by sampling by the sampling circuit 201 shown in FIG.

As shown in FIG. 6, in the first embodiment of the present invention, the voltage value of the image signal Data obtained by sampling a new image signal is the same as the previous image signal Data.
When it becomes higher than the voltage value of a (change of the image data 1 and 7), the increase amount based on the differential component is added to the voltage of the new image signal. For example, in the period T1 of FIG.
Image signal Dat output from the sampling circuit 201
The voltage of a becomes higher than the voltage of the image signal Data output from the sampling circuit 201A that does not have the differentiating circuit 206 shown in FIG.

When the voltage value of the image signal Data becomes low due to the sampling of the new image signal (change of the image data 19 and 25), the new image signal Data is changed.
The voltage value of drops by a voltage corresponding to the differential component. For example, in the period T2 of FIG. 6, the voltage of the image signal Data output from the sampling circuit 201 becomes lower than the voltage of the image signal Data output from the sampling circuit 201A.

On the other hand, when the value of the new image signal Data is almost or completely the same as the immediately preceding image signal Data (image data 7 to 19), the differential component is extremely small or disappears. No difference appears in the waveform between the sampling circuit 201 and the sampling circuit 201A. That is, in the period T3 in FIG. 6, the image signal D output from the sampling circuit 201
The voltage value of ata substantially or completely matches the voltage value of the image signal Data output from the sampling circuit 201A.

The amount of change of the original image signal with respect to the voltage level changes according to the value obtained by differentiating the amount of change.

Although FIG. 6 shows the parallel image signal output to the image signal line Data1, the sampling circuits 201b to 20 also for the waveforms of the parallel image signal output to the image signal lines Data2 to Data6.
The same operation is performed in 1f.

As described above, in the image signal processing circuit 200,
By feeding back the differential component of the parallel image signal output from the differentiating circuit 206, the voltage value of the parallel image signal output is corrected.

In the image signal processing circuit 200, the correction amount of the parallel image signal can be adjusted by changing the time constant of the differentiating circuit 206 or the feedback amount of the differential component, for example. These time constants and feedback amounts can be set in accordance with the characteristics of the electro-optical device connected to the image signal processing circuit 200, for example, to values that minimize the ghost of the image. Adjustment of time constant In this case, the input resistor 206c and the feedback resistor 206d in FIG. 2 may be variable resistors and adjustment may be performed while monitoring the image display by the liquid crystal panel. The amount of feedback is the differentiation circuit 2
The amplification factor of the No. 06 amplifier 206a is preferably adjustable.

Hereinafter, the parallel image signal D from the image signal processing circuit 200 to the liquid crystal panel as the electro-optical device.
The operation of outputting data 1 to Data 6 and displaying an image will be described.

FIG. 7 shows an example of a liquid crystal panel which receives the parallel image signals Data1 to Data6 from the image signal processing circuit 200 and displays an image. As shown in FIG. 7, the substrate 100 of the liquid crystal panel includes a plurality of scanning lines 110 extending in parallel with each other and a plurality of data signal lines extending in a direction intersecting with the scanning lines 110. 1
12, and the pixels 120 are arranged in a matrix corresponding to each intersection of the scanning lines 110 and the data signal lines 112. The substrate 100 and another substrate (not shown) are adhered by a seal so as to be opposed to each other with a predetermined gap, and a liquid crystal layer is sealed in the gap between the substrates to form a liquid crystal panel.

At the position of each pixel 120 on the substrate 100, a switching element such as a thin film transistor 114 and a pixel electrode 116 are connected in series, and
When the thin film transistor 114 is turned on, the pixel electrode 11
Storage capacitor 115 for storing the voltage applied to
Are provided respectively. Thin film transistor 114
Has a gate electrode connected to the scanning line 110, a source electrode connected to the data signal line 112, and a drain electrode connected to the pixel electrode 116. Note that a large number of capacitor lines 117 are provided over the substrate 100 in parallel with the scan lines 110, and the drain electrode and / or the pixel electrode 116 of the thin film transistor 114 is provided.
And the capacitance line 117 overlap with each other with the insulating film interposed therebetween to form the storage capacitor 115. The pixel electrode 116 of each pixel is
A voltage corresponding to the image data is applied from the data signal line 112 through the thin film transistor 114 which is made conductive by receiving the selection voltage applied to the scanning line 110, and is formed on the inner surface of another substrate that faces the liquid crystal layer. Between the common electrode,
An electric field corresponding to image data is formed. The alignment of the liquid crystal molecules changes according to this electric field, and the polarization axis of the light passing through the liquid crystal layer is modulated. The storage capacitor 115 is the thin film transistor 1
This is for holding the voltage applied to the pixel electrode 114 when 14 is non-conductive. In addition, TN (Tw
If isted Nematic) type liquid crystal is used, polarizing plates are arranged on both sides of a pair of substrates of the liquid crystal panel. Note that FIG. 7 shows a detailed configuration of only one pixel, and illustration of pixels corresponding to the intersections of the other scanning lines 110 and the data signal lines 112 is omitted, but the same applies to other pixels. It is a composition. .

The scanning side driving circuit 102 has a shift register, and sequentially shifts the first shift start pulse supplied in each vertical scanning period, so that each scanning line 110a, 110b ... One line at a time. By outputting a scanning signal (selection voltage) in sequence, the scanning line 110 of the pixel to be written is selected. These drive circuits are composed of thin film transistors and the like formed on the substrate 100.

The data signal line 112 is connected to the parallel image signal lines Data1 to D through the sampling switch 106.
It is connected to ata6. That is, the first data signal line 112a is connected to the first parallel image signal line Data1 through the sampling switch 106a, and the second data signal line 112a is connected to the second parallel image signal line Data1.
The second data signal line 112b is the sampling switch 1
The second parallel image signal line Data through 06b
Similarly, the third to sixth data signal lines 112c to 112f are connected to the third to sixth parallel image signal lines Data3 to Data6 via the sampling switches 106c to 106f, respectively. ing. Similarly, the data signal line 112 is repeatedly connected to the parallel image signal lines Data1 to Data6 by six lines via the sampling switch 106.

The sampling switches 121a and 12a
Each of 1b, ... Can be composed of a semiconductor switching element such as a thin film transistor formed on a substrate. The thin film transistor of the sampling switch 121 is configured such that a sampling signal is input to a gate electrode, a source electrode is connected to any of the image signal lines Data1 to Data6, and a drain electrode is connected to the data signal line 112. Timing of the sampling signal Conduct with,
The image data of the image signal line is sampled and supplied to the data signal line 112.

The data side drive circuit 104 has a shift register, and sequentially shifts the first shift start pulse supplied in each horizontal scanning period according to the shift clock. This shift clock is used for the parallel image signal line Da.
It is synchronized with the transmission timing of the image data of ta1 to Data6. The data side drive circuit 104 sequentially outputs sampling signals to each sampling switch 106 in response to this shift operation, and the sampling switch 106 which receives the sampling signal samples the image data. These drive circuits are composed of thin film transistors and the like formed on the substrate 100.

The timing circuit block 300 sends timing pulses based on the dot clock DC reference to the scanning side driving circuit 102, the data side driving circuit 104 and the image signal processing circuit 200. As a result, the operations of the scan side drive circuit 102, the data side drive circuit 104, and the image signal processing circuit 200 can be synchronized.

Next, the operation of displaying an image on the liquid crystal panel will be described.

The scanning side drive circuit 102 includes one scanning line 1
A scanning signal is output to 10, and a scanning line is selected by this.

From the image signal processing circuit 200, the parallel image signals Data1 to Data are output at the timings shown in FIG.
6 is output. On the other hand, each sampling switch 106
Are sequentially closed in accordance with the timing of the output parallel image signal. That is, in FIG. 5, the sampling switch 106a is closed according to the parallel image signal of pixel number 1, and the sampling switch 106b is closed according to the parallel image signal of pixel number 2. Similarly, the sampling switch 106 is sequentially closed in accordance with the output of the parallel image signal. When the sampling switch 106 is closed, the corresponding data signal line 112 changes the parallel image signal lines Data1 to Data6.
, And a parallel image signal is supplied to the data signal line 112.

As a result, the selected scan line 110,
The thin film transistors 114 of the pixels corresponding to the intersections with the data signal lines 120 in which the respective sampling switches 112 are closed are sequentially turned on, and writing to each pixel can be performed.

When the writing of the selected scanning line 110 to the pixel is completed, the adjacent scanning line 110 is then selected and the above writing operation is repeated. Scan line 11
By sequentially selecting 0 and sequentially executing the above writing operation, writing can be performed for all pixels of the liquid crystal panel.

By the way, as the ideal performance of the liquid crystal panel, it is desirable that the voltage of the data signal line 112 completely matches the voltage of the image signal Data when the sampling switch 106 is closed. However, in an actual liquid crystal panel, the parallel image signal lines Data1 to Data
When the voltage of the image signal fluctuates significantly due to the influence of a6 and the resistance and capacitance formed on the data signal line 112 (affected by the time constant), the voltage of the data signal line 112 is not completely changed. Cannot follow voltage changes.

For example, as shown in FIG. 6, assuming that the image signal of the parallel image signal line Data1 suddenly rises when the image data 1 is switched to the image data 7, even if the sampling switch 106g of FIG. 7 is closed,
The voltage of the data signal line 112g does not completely follow the image signal, and its voltage value becomes dull and takes a voltage value lower than the voltage value of the image signal. On the contrary, when the image signal sharply decreases, for example, when the data of the image data 19 of FIG. 6 is switched to the image data 25, the voltage of the corresponding data signal line 112 changes dullly to change the image data 25. It does not completely fall to the voltage value.

If such a deviation of the voltage value of the data signal line 112 is left as it is, a ghost or the like occurs in the displayed image, and the image quality is deteriorated.

However, in the image signal processing circuit 200 according to the first embodiment of the present invention, as shown in the lower part of FIG.
The voltage value of the changed image signal is shift-corrected in accordance with the change of the image signal in the changing direction, and the direction of the shift correction is based on the performance of the liquid crystal panel.
It is supposed to cancel the deviation of the voltage value of 2. That is, the image signal processing circuit 200 shifts and corrects the voltage value of the image signal in a direction in which the change is emphasized and outputs the image signal.
In particular, if the voltage change of the image signal is large, the shift amount increases accordingly, so that the influence of the delay due to the wiring in the liquid crystal panel is canceled well.

Therefore, by appropriately setting the correction amount of the voltage value of the image signal in the image signal processing circuit 200, the voltage value of the data signal line 112 can be maintained at an appropriate value and the ghost can be reduced or eliminated. it can.

Although the number of parallel image signals and the number of image signal lines thereof are six in this embodiment, the present invention is not limited to this. The number can be increased or decreased according to the switching response of the sampling switch 106. According to the number, the image signal sampling circuit 201
The number of will also increase or decrease. Sampling switch 10
If the responsiveness of 6 is good, the number of image signal lines Data may be one. Even in the case of one line, it is advantageous to employ the configuration of the present invention because it is possible to compensate for the delay of the voltage change due to the resistance or capacitance of the wiring.

Further, in this embodiment, the image data Da output from the image signal sampling circuit 201 is output.
ta1 to Data6 are output at timings sequentially shifted in synchronization with the dot clock DC cycle, and sampling by the sampling switch 106 is also performed at timings sequentially shifted in synchronization with the dot clock DC. It is not limited. The parallel image data Data1 to Data6 output from the plurality of image signal sampling circuits 201 are simultaneously output at synchronized timings, and the sampling switch 106 also samples the parallel image signals at the same time and simultaneously outputs them to the corresponding data signal lines 116. It may be configured to supply image data.

(Second Embodiment) A second embodiment of the image signal processing circuit of the electro-optical device according to the present invention will be described below with reference to FIG. The parts that are not described in the present embodiment are the same as those in the first embodiment, so the description thereof will be omitted.

In the first embodiment, the image signal VID supplied to the image signal sampling circuit 201 is clamped for a predetermined period (every blanking period) to obtain the image signals Data1 to Data6.
Clamp circuit (205, 20) that keeps the reference voltage value of
7 and 208), the image signal sampling circuit 201 shown in FIG. 8 in which the clamp circuit is omitted is used instead of the image signal sampling circuits 201a to 201f in the second embodiment.

FIG. 8 shows each image signal sampling circuit 201a provided in the image signal processing circuit of the second embodiment.
It is a circuit diagram which shows-201f. The image signal sampling circuit 201 includes an offset control unit 211 that receives the serial image signal VID, a sample hold circuit 212 that samples the output signal of the offset control unit 211, and a differentiation circuit 213 that outputs a differential component of the output signal of the sample hold circuit 212. With. The output signal of the differentiating circuit 213 is input to the offset control unit 211. The sample hold circuit 212 performs the same operation as that of FIG. 3, and its output terminal has parallel image signal lines Data1 to Data6.
Is connected according to either of.

The offset control unit 211 uses the image signal VID
Is input to the base terminal of the bipolar transistor 21
1a and a differential component synthesizing unit 211b that is connected to the emitter side of the transistor 211a and generates a voltage according to the output signal of the differentiating circuit 213, and an output obtained by superimposing the output signal of the differentiating circuit 213 on the image signal VID. Output a signal. The configuration and operation of this offset control unit 211 are the same as those described in the first embodiment. The differential component synthesizing unit 211b is configured as a variable current source, and includes, for example, a current source transistor whose base is variably controlled according to the voltage obtained by adding or subtracting the voltage of the differential component from the differentiating circuit 213 to change the current value. The differential component synthesizer 211b includes a sample hold circuit 21.
When the differentiating circuit 213 differentiates the rising edge of the output voltage of 2, the current value is reduced according to the magnitude of the differential component to increase the voltage value input to the sample hold circuit 212. On the other hand, when the fall of the output voltage is differentiated, the current value is increased according to the magnitude of the differential component, and the voltage value input to the sample hold circuit 212 is decreased.

Next, the operation of each image signal sampling circuit shown in FIG. 8 will be described.

As in the case of FIG. 2, by inputting the sampling pulse SP to the sampling switch 212a of each sample-hold circuit 212, the sampling switch 212a is closed and the sample-hold capacitor 212b is charged to sample the image signal VID. Is done. In the image signal sampling circuit 201 of FIG. 8, when the image signal has a higher voltage level than the previous image signal due to the sampling of the image signal VID and the output value rises, the offset control is performed according to the differential component output from the differentiating circuit 213. The output voltage of the part 211 increases. Therefore, in this case, the output voltage value of the image signal Data after the image signal rises becomes higher than the original image data according to the amount of change. On the contrary, when the image signal becomes a voltage level lower than that of the previous image signal by the sampling of the image signal VID and the output value falls, the output voltage of the offset control unit 211 changes according to the differential component output from the differentiating circuit 213. To descend. Therefore, when the image signal has a lower voltage level than the previous image signal and the output value falls, the voltage value of the new image signal Data becomes lower than the original image data according to the amount of change. .

As described above, the image signal sampling circuit of FIG. 8 emphasizes the change in the image signal Data when the image signal Data changes, like the image sampling circuit 201 of the image signal processing circuit of the first embodiment. The voltage value is shifted and corrected to be output. Therefore, the image signal processing circuit according to the second embodiment can improve the image quality by compensating for the performance of the electro-optical device, as in the first embodiment.

In the image signal processing circuit 200, the correction amount of the image signal Data can be adjusted by changing the time constant of the differentiating circuit 213 or the feedback amount of the differential component. These time constants and feedback amounts can be set in accordance with the characteristics of the electro-optical device connected to the image signal processing circuit 200, for example, to values that minimize the ghost of the image. In this case, the time constant may be adjusted by changing the resistor in the differentiating circuit 213 of FIG. 8 to a variable resistance and monitoring the image display by the liquid crystal panel. The amount of feedback is differentiating circuit 213
It is advisable to adjust the amplification factor of the internal amplifier.

(Third Embodiment) The third embodiment of the image signal processing circuit of the electro-optical device according to the present invention will be described below with reference to FIG. The parts that are not described in the present embodiment are the same as those in the first embodiment, so the description thereof will be omitted.

In the third embodiment, each of the image signal sampling circuits 201a to 201 used in the first embodiment.
Instead of f, the image signal sampling circuit 20 shown in FIG.
1 is used respectively.

As shown in FIG. 9, each image signal sampling circuit 201a to 201f used in the third embodiment.
Is an input buffer 22 that receives the serial image signal VID.
1 and parallel image signal lines Data1 to Da
Output buffer 22 that outputs corresponding to any one of ta6
2 and the sample-hold capacitor 223 connected between the positive-phase input terminal of the output buffer 222 and the ground.
And a sampling switch 224 placed between the sample and hold capacitor 223 and the output terminal of the input buffer 221. In addition, the sampling switch 22
4 in series with the peaking coil 225 and the resistor 22.
6 is connected.

Next, the operation of each image signal sampling circuit in FIG. 9 will be described.

The serial image signal VID is input to each input buffer 221, and the same waveform as the image signal VID is output to the output terminal of the input buffer 221. When the sampling pulse SP is input to the sampling switch 224 as in the configuration of FIG.
4 is closed, but at this time, peaking due to the action of the peaking coil 225 and the sample hold capacitor 223 occurs.

That is, the output voltage value of the buffer 221
That is, when the voltage value of the newly sampled image data is larger than the previous holding voltage held in the sample hold capacitor 223, a larger current than in the case without the peaking coil 225 (when short-circuited) is generated. It flows into the sample hold capacitor 223. Therefore, the holding voltage of the sample-hold capacitor 223 increases, and the voltage value of the image signal Data output from the output buffer 222 is corrected to increase. On the contrary, the voltage value of the image data to be newly sampled is the sample hold capacitor 22.
When the voltage is smaller than the previous holding voltage held in No. 3, a larger current is drawn from the sample hold capacitor 223 to the buffer 221 than in the case where the peaking coil 225 is not present (shorted). Therefore, the holding voltage of the sample-hold capacitor 223 becomes smaller, and the voltage value of the image signal Data output from the output buffer 222 is corrected so as to decrease. The resistor 226 acts so as to appropriately suppress the peaking effect. Therefore, the voltage value of the new image signal input to the output buffer 222 is shifted so as to emphasize it in the direction of change by the peaking effect according to the amount of change between the previous image signal and the new image signal. Is corrected. The voltage shift amount corresponds to the change amount of the image signal VID.

Therefore, the image signal sampling circuit of FIG. 9 has a function of correcting a new image signal in accordance with the difference between the voltage value of the previous image signal and the voltage value of the new image signal. The direction of is the same as in the first and second embodiments.

As described above, the image signal sampling circuit of FIG. 9 operates similarly to the image sampling circuit 201 of the image signal processing circuit of the first embodiment, and the image signal Dat
The voltage value of a is corrected. Thereby, the image signal processing circuit of the third embodiment can improve the image quality by compensating for the performance of the electro-optical device as in the first and second embodiments.

In the present embodiment, the differentiating circuit and the clamp circuit as in the first and second embodiments are not provided, but the clamp circuit is as shown in FIG. 4 if necessary. The amplifier 205, the clamp capacitor 208, and the control unit 202 may be provided. In this case, the control unit 202 is arranged on the input side of the image signal VID, the amplifier 205 inputs the output of the output buffer 222, and the DC level of the image signal becomes the reference voltage V _REF via the clamp capacitor 208. Control unit 202
Feedback control.

In the image signal processing circuit 200, the image signal Da is changed by changing the peaking amount, for example.
The correction amount of ta can be adjusted. These correction amounts can be set according to the characteristics of the electro-optical device connected to the image signal processing circuit 200, for example, to values that minimize the ghost of the image. In this case, the values of the peaking coil 226 and the resistor 224 can be adjusted.

(Fourth Embodiment) The fourth embodiment of the image signal processing circuit of the electro-optical device according to the present invention will be described below with reference to FIGS. The parts that are not described in the present embodiment are the same as those in the first embodiment, so the description thereof will be omitted.

In the fourth embodiment, the image signal sampling circuits 201a to 201f used in the first embodiment are used.
Instead of the image signal sampling circuit 20 shown in FIG.
1 is used respectively.

This image signal sampling circuit 201 is
A first sampling circuit 231 for sampling the serial image signal VID, and a first sampling circuit 231.
Circuit 232 that creates a differential component of the output signal of the first sampling circuit 231, and the output signal of the first sampling circuit 231 and the differentiation circuit 2
An adder circuit 233 that adds the output signals of 32 and a second sampling circuit 234 that samples the output signals of the adder circuit 233 are provided.

As shown in FIG. 10, the first sampling circuit 231 is an input buffer 23 for receiving the image signal VID.
1a and an output buffer 2 that outputs a sampling voltage value
31b and the sample hold capacitor 2 connected between the positive phase input terminal of the output buffer 231b and the ground
31c and a sampling switch 231d connected between the sample-hold capacitor 231c and the output terminal of the input buffer 231a.

The differentiating circuit 232 includes a buffer 232a composed of an amplifier whose output is fed back to the negative phase input, an input capacitor 232b connected between the output terminal of the first sampling circuit 231 and the input terminal of the buffer 232a, and a buffer. And a resistor 232c connected between the input terminal of 232a and the ground.

The adder circuit 233 includes an amplifier 233a, an output terminal of the first sampling circuit 231, and the amplifier 23.
Dividing resistor 233 connected between the positive phase input terminals of 3a
b, a dividing resistor 233c connected between the output terminal of the differentiating circuit 232 and the positive phase input terminal of the amplifier 233a,
The resistor 233d and the resistor 233e are connected in series between the output terminal of the amplifier 233a and the ground.
The connection point between the resistor 233d and the resistor 233e is the amplifier 2
It is connected to the negative phase input terminal 33a.

The adder circuit 233 is the first sampling circuit 2
The output signal of 31 and the output signal of the differentiating circuit 232 are added, and the addition ratio thereof depends on the resistance value ratio of the dividing resistors 233b and 233c, and the gain of the adding circuit 233 is the resistor 233d. And resistor 233e
It is possible to adjust each by the resistance value ratio of.

The second sampling circuit 234 includes a buffer 234a and a sample hold capacitor 234b connected between the input terminal of the buffer 234a and the ground.
And a sampling switch 234 connected between the output terminal of the adder circuit 233 and the input terminal of the buffer 234a.
and c. This output is the parallel image signal line Dat
It is connected corresponding to any of a1 to Data6.

The sampling switch 231d provided in the first sampling circuit 231 and the sampling switch 23 provided in the second sampling circuit 234.
The same sampling pulse SP is input to 4c.

Next, the operation of the image signal sampling circuit of FIG. 10 will be described.

By applying the sampling pulse SP at the cycle T shown in FIG. 11, the first sampling circuit 23
When the image signal VID is sampled at 1, the image signal that has not been corrected, that is, the image signal as shown in FIG. 11A is output from the first sampling circuit 231. In FIG. 11, a period T indicates one cycle of a sampling pulse SP for sampling the input image signal VID, and the image signal is sampled every period T. As described above, this sampling pulse SP is
It is substantially equal to the period of the dot clock DC divided by the number of image signal signal sampling circuits 201. When the image signal output from the first sampling circuit 231 is input to the differentiating circuit 232.
The differential component of the image signal as shown in (b) is output.
The operation of outputting the differential component of the image signal from the differentiating circuit 232 is the same as that of the differentiating circuit 206 in FIG. 2 and the differentiating circuit 213 in FIG.

A signal obtained by adding the output signal of the first sampling circuit 231 and the output signal of the differentiating circuit 232 is applied to the positive-phase input terminal of the amplifier 233a of the adding circuit 233, and the signal from the output terminal of the amplifier 233a is applied. A signal obtained by combining the signals of FIGS. 11A and 11B is output as shown in FIG. 11C.

In the second sampling circuit 234, as shown in FIG.
1 (c), the sampling pulse S
Sampling will be performed according to the timing of P.
Therefore, the output signal of the second sampling circuit 234 has a waveform corrected by shifting the voltage level in the direction in which the change of the image signal is emphasized (the change direction of the image signal) as shown in FIG. 11D. . Then, the image data as shown in FIG. 11D is obtained by the image signal line Da of the electro-optical device.
It is supplied to ta1 to Data6.

As described above, in the image signal sampling circuit of FIG. 10, after sampling the image signal VID to obtain the image signal, the differential component of the voltage change of the image signal is superimposed on this image signal. Further, by sampling the image signal on which the differential component is superimposed, the image signal Data with the desired correction is obtained.

In the fourth embodiment, the common sampling pulse SP is given to the first sampling circuit 231 and the second sampling circuit 234, but different sampling pulses may be input to both. For example, the timing of the sampling pulse given to the second sampling ring circuit 234 can be arbitrarily selected as long as it is within a range in which the voltage value according to the differential component can be output.

As described above, the image signal processing circuit according to the fourth embodiment compensates for the performance of the electro-optical device by correcting the image signal Data, as in the first to third embodiments. The image quality can be improved.

Therefore, the image signal processing circuit of the fourth embodiment can improve the image quality by compensating the performance of the electro-optical device, as in the first to third embodiments.

In the present embodiment, the clamp circuit as in the first embodiment is not provided, but if necessary, the amplifier 205, the clamp capacitor 208, and the control unit 202 as shown in FIG. May be provided. In this case, the control unit 202 is arranged on the input side of the image signal VID, and the amplifier 205 is connected to the second sampling circuit 2.
The output of 34 is input, and the control unit 202 is feedback-controlled via the clamp capacitor 208 so that the DC level of the image signal becomes the reference voltage V _REF .

Further, in the image signal processing circuit 200, by changing the addition ratio and gain of the addition circuit 233,
The correction amount of the image signal Data can be adjusted. These correction amounts can be set according to the characteristics of the electro-optical device connected to the image signal processing circuit 200, for example, to values that minimize the ghost of the image. In this case, the addition ratio is determined by the dividing resistors 233b and 233.
The resistance value ratio of c can be made variable, and the gain of the adding circuit 233 can be adjusted by making the resistance value ratios of the resistors 233d and 233e variable.

(Fifth Embodiment) The fifth embodiment of the image signal processing circuit of the electro-optical device according to the present invention will be described below with reference to FIG. The parts that are not described in the present embodiment are the same as those in the first embodiment, so the description thereof will be omitted.

In the fifth embodiment, the image signal sampling circuits 201a to 201f used in the first embodiment are used.
Instead of the image signal sampling circuit 20 shown in FIG.
1 is used respectively.

This image signal sampling circuit includes an input buffer 241 for receiving the image signal VID and an image signal VI.
Differentiating circuit 242 for outputting a differential component of D, first sampling circuit 243 for sampling the output signal of input buffer 241, second sampling circuit 244 for sampling the output signal of differentiating circuit 242, and first sampling An addition circuit 245 that adds the output signal of the circuit 243 and the output signal of the second sampling circuit 244 and outputs the added signal as an image signal corresponding to any of the image signal lines Data1 to Data6. First
The same sampling pulse SP is input to the sampling circuit 243 and the second sampling circuit 244.

As shown in FIG. 12, the differentiating circuit 242 is
Buffer 24 consisting of an amplifier whose output is fed back to the negative phase input
2a, the terminal to which the image signal VID is input, and the buffer 2
A capacitor 242b connected between the input terminals of 42a.
And a resistor 242c connected between the input terminal of the buffer 242a and the ground.

The first sampling circuit 243 has a buffer 243a for outputting a sampling voltage value, a sample hold capacitor 243b connected between the input terminal of the buffer 243a and the ground, a sample hold capacitor 243b and an output terminal of the buffer 241. And a sampling switch 243c connected between the two.

The second sampling circuit 244 includes a buffer 244a which outputs a sampling voltage value, a sample hold capacitor 244b connected between the input terminal of the buffer 244a and the ground, a sample hold capacitor 244b and an output terminal of the buffer 242a. And a sampling switch 244c connected between the two.

The adder circuit 245 includes an amplifier 245a and a first
Terminal of sampling circuit 243 and amplifier 245
a dividing resistor 245b connected between the positive-phase input terminals of a
A dividing resistor 245c connected between the output terminal of the differentiating circuit 244 and the positive-phase input terminal of the amplifier 245a, and a resistor 245d and a resistor 245e connected in series between the output terminal of the amplifier 245a and the ground. Equipped with. The connection point between the resistor 245d and the resistor 245e is the amplifier 24.
5a is connected to the negative phase input terminal.

The sampling switch 243c provided in the first sampling circuit 243 and the sampling switch 24 provided in the second sampling circuit 244.
The sampling pulse SP is input to 4c.

Next, the operation of the image signal sampling circuit of FIG. 12 will be described.

Since the buffer 241 outputs a signal having the same waveform as the image signal VID, the first sampling circuit 243 outputs an uncorrected image signal corresponding to FIG. 11A. It

On the other hand, from the differentiating circuit 242, FIG.
The differential component of the image signal corresponding to (b) is output. The operation of outputting the differential component of the image signal from the differentiating circuit 242 is the same as that of the differentiating circuit 206 of FIG. 2 and the differentiating circuit 213 of FIG. Then, the second sampling circuit 244 outputs a pulse having a voltage value level corresponding to the differential component by sampling the differential component. Since the common sampling pulse SP is applied to the first sampling circuit 243 and the second sampling circuit 244, the uncorrected image signal and the pulse are output at the same timing.

The adder circuit 245 adds the output signal of the first sampling circuit 243 and the output signal of the second sampling circuit 244 to emphasize the voltage change of the image signal VID as shown in FIG. 11 (d). The image signal Data corrected by shifting the voltage level in the direction (direction of change of the voltage level) is output. Then, this image signal is supplied corresponding to one of the image signal lines Data1 to Data6 of the electro-optical device. That is, in the fifth embodiment, the signal obtained by sampling the image signal and the signal obtained by sampling the differential component of the image signal are added and supplied to the electro-optical device.

In the fifth embodiment, the common sampling pulse SP is given to the first sampling circuit 241 and the second sampling circuit 242, but different sampling pulses may be input to both. For example, the timing of the sampling pulse given to the second sampling ring circuit 242 can be arbitrarily selected as long as it is within a range in which the voltage value according to the differential component can be output.

In this embodiment, the clamp circuit as in the first embodiment is not provided, but if necessary, the amplifier 205, the clamp capacitor 208, and the controller 202 as shown in FIG. May be provided. In this case, the control unit 202 is arranged on the input side of the image signal VID, and the amplifier 205 inputs the output of the adding circuit 245 so that the DC level of the image signal becomes the reference voltage V _REF via the clamp capacitor 208. Control unit 2
02 is feedback controlled.

As described above, the image signal processing circuit according to the fifth embodiment compensates the performance of the electro-optical device by correcting the image signal Data, as in the first to fourth embodiments. The image quality can be improved.

In the image signal processing circuit 200, the fourth
The correction amount of the image signal Data can be adjusted by changing the addition ratio and the gain of the adder circuit 233 as in the embodiment. Further, the correction amount of the image signal Data can be adjusted by changing the time constant or the buffer amplification factor of the differentiating circuit 232 as in the first embodiment. These correction amounts are calculated by the image signal processing circuit 20.
According to the characteristics of the electro-optical device connected to 0, for example, it can be set to a value that minimizes the ghost of the image. The configuration for this adjustment is similar to that of the previous embodiment.

(Sixth Embodiment) A sixth embodiment of the image signal processing circuit of the electro-optical device according to the present invention will be described below with reference to FIGS. 13 and 14. The parts that are not described in the present embodiment are the same as those in the first embodiment, so the description thereof will be omitted.

In the sixth embodiment, the image signal sampling circuits 201a to 201f used in the first embodiment are used.
Instead of the image signal sampling circuit 20 shown in FIG.
1 is used respectively.

This image signal sampling circuit 201
A sampling circuit 251 that samples the serial image signal VID, a differentiation circuit 252 that outputs a differential component of the output signal of the sampling circuit 251, and an addition circuit 253 that adds the output signal of the sampling circuit 251 and the output signal of the differentiation circuit 252. Prepare

As shown in FIG. 13, the sampling circuit 2
51 is an input buffer 251a for receiving the image signal VID.
And an output buffer 251 that outputs the sampling voltage value
b, the sample-hold capacitor 251 connected between the positive-phase input terminal of the output buffer 251b and the ground.
c, and a sampling switch 251d connected between the sample-hold capacitor 251c and the output terminal of the input buffer 251a.

The differentiating circuit 252 includes a buffer 252a composed of an amplifier whose output is fed back to the negative phase input, a capacitor 252b connected between the output terminal of the sampling circuit 251 and the input terminal of the buffer 252a, and the buffer 25.
A resistor 2 connected between the input terminal of 2a and ground
52c.

The adding circuit 253 includes an amplifier 253a, a dividing resistor 253b connected between the output terminal of the sampling circuit 251 and the positive phase input terminal of the amplifier 253a, an output terminal of the differentiating circuit 252 and the positive phase input of the amplifier 253a. The dividing resistor 253c connected between the terminals and the amplifier 2
The resistor 253d and the resistor 253e are connected in series between the output terminal of 53a and the ground. Resistor 2
The connection point of 53d and the resistor 253e is connected to the negative phase input terminal of the amplifier 253a.

Next, the operation of the image signal sampling circuit of FIG. 13 will be described.

FIG. 14 shows, from the top, the image signal VID input, the image signals Data1 to Data6 output from the image signal processing circuit 200, and the parallel image signal line D.
Image signal sampling circuits 201a to 201 connected to the respective data1 to Data6 and outputting image signals
The signals in each part of 1f are shown. The horizontal axis represents the data time length of each image signal. Note that the signals of the image signal sampling circuits 201 in FIG. 14 are drawn with the rising timings of the output signals from the image signal sampling circuits 201 aligned, and are not displayed on a common time axis.

The sampling circuit 251 causes the image signal VI
When D is sampled, the image signal without correction, that is, the image signal shown in FIG. 14A is output from the sampling circuit 251. Sampling circuit 25
When the image signal output from 1 is input to the differentiating circuit 252, the differentiating circuit 252 outputs the differential component of the image signal shown in FIG. The operation of outputting the differential component of the image signal from the differentiating circuit 252 is performed by the differentiating circuit 206 in FIG.
And the differentiating circuit 213 of FIG.

A signal obtained by adding the output signal of the sampling circuit 251 and the output signal of the differentiating circuit 252 is applied to the positive phase input terminal of the amplifier 253a of the adding circuit 253,
The image signal Data shown in FIG. 14C is output from the output terminal of the amplifier 253a. A differential component that emphasizes a change in the parallel image signal is superimposed on the parallel image signal. Then, the image signal Data is supplied to the image signal lines Data1 to Data6 of the electro-optical device.

Image signals Data1 to Data1 shown in FIG.
When Data6 is supplied to the liquid crystal panel shown in FIG. 7, for example, the voltage of the data signal line 112 connected to any of the parallel image signal lines Data1 to Data6 by the sampling switch 106 (see FIG. 7) is a differential component. to be influenced.

In this case, the parallel image signal line Data1
In the data signal line 112 connected to the data signal line 1 to Data3, the data signal line 1 connected to the parallel image signal lines Data5 to Data6 in the direction in which the voltage increases due to the differential component.
In 12, the voltage is shifted in the direction in which the voltage drops due to the differential component, and the change is emphasized and corrected.

Therefore, the performance of the liquid crystal panel can be complemented by adjusting the ratio of the differential components to be superimposed or adjusting the time constant of the differentiating circuit 252. As a result, it is possible to suppress or eliminate the ghost of the image displayed on the liquid crystal panel.

In the present embodiment, the clamp circuit as in the first embodiment is not provided, but the clamp circuit may include an amplifier 205 and a clamp capacitor 208 as shown in FIG. The control unit 202 may be provided. In this case, the control unit 202 is arranged on the input side of the image signal, and the amplifier 205 is the addition circuit 2
The output of 53 is input, and the control unit 202 is feedback-controlled via the clamp capacitor 208 so that the DC level of the image signal becomes the reference voltage V _REF .

(Seventh Embodiment) A seventh embodiment of the image signal processing circuit of the electro-optical device according to the present invention will be described below with reference to FIG. The parts that are not described in the present embodiment are the same as those in the first to sixth embodiments, and the description thereof will be omitted.

In the first to sixth embodiments, the six parallel image signals Data1 to Data6 are voltage-corrected by performing a voltage shift according to the width of change in the voltage level of each image signal Data itself. I try to
In the seventh embodiment, each parallel image signal D
The data 1 to Data 6 are corrected by performing a voltage shift according to the average of the change widths of the voltage levels of the six parallel image signals Data 1 to Data 6.

As shown in FIG. 15, the image signal processing circuit according to the seventh embodiment has the parallel image signal lines D respectively.
The control unit 261 for data1 to Data6, respectively.
a-261f and sampling circuits 262a-262f
And all parallel image signal lines Dat
A differentiating circuit 264 common to a1 to Data6 is provided. As in FIG. 1, sampling pulses SPa to SPf are sequentially input to the sampling circuits 262a to 262f at timings sequentially shifted by one image data in synchronization with the dot clock DC, and the image signals are sequentially sampled, while the image signal lines are Parallel image signals are output to Data1 to Data6 in synchronization with the same timing pulse OUT. The pulse OUT is supplied to the sampling circuits 262a-26.
2f is a panel which is input when image signals are sequentially sampled, and has a period obtained by dividing the period of the dot clock DC by the number of sampling circuits.

A more detailed block configuration of the sampling circuit 262 of this embodiment is shown in FIG. The sampling circuits 262a to 262f have the same configuration, and the first sampling circuits 262a-1 to 262f have the same configuration.
-2 and the second sampling circuits 262a-2 to 262f.
-2 is provided. First sampling circuits 262a-1 and 262a-2
62f-1 may use the sample hold circuit 204 described in detail in FIG. 3, the circuit 212 in FIG. 8, the circuits 231 and 234 in FIG. 10, the circuits 243 and 244 in FIG. 12, and the circuit 251 in FIG. The sampling pulse generator 209 sequentially inputs the sampling pulses SPa to SPf formed in synchronization with the dot clock DC, and samples and holds the image signal. Sampling pulse SPa
As described in the first embodiment, to SPf are pulses sequentially shifted by one image data cycle of the input serial image signal VID, and consecutive six image data are sequentially sampled by the first sampling. This is a pulse to be taken into the circuit. The first sampling circuits 262a-1 to 262
The image data sample-held at f-1 corresponds to the corresponding second sampling circuits 262a-2 to 262.
It is supplied to f-2, sampled and held by the same pulse OUT, and simultaneously output in synchronization with the pulse OUT. Second sampling circuits 262a-2 to 262f-2
The configuration of 204 is shown in FIG. 3, 212 in FIG. 8, and 2 in FIG.
31 and 234, 243 and 244 in FIG. 12, 25 in FIG.
A circuit such as 1 may be used. The pulse OUT
Is preferably generated in synchronization with or slightly delayed from the sixth sampling pulse SPf.

The composite signal of the output signals of the sampling circuits 262a to 262f is input to the differentiating circuit 264 via each resistor of the resistor group 263, and the differentiating circuit 264 controls the differential component of this composite signal to the control unit 261a. To 261f. The specific configuration of the differentiating circuit may use the differentiating circuit 206 of FIG. In this case, the input resistor 206c in 206 is replaced with the resistor group 263 in FIG. That is, it is preferable that the input resistance of the resistor group 263 be commonly connected to the input capacitor 206b and input. However, the differentiating circuit is not limited to this configuration, and the output terminals of the resistor group 263 may be commonly connected and commonly input to the differentiating circuit 213 in FIG. With this configuration, the differentiating circuit 264
The signal voltages of the image signals Data1 to Data6 simultaneously output from the sampling circuits 262a to 262f are added by the resistor group 263 to be input to the. Therefore, from the differentiating circuit 264, the parallel image signal Data
Since an output obtained by differentiating the sum of the voltage changes of 1 to Data 6 appears, a differential component corresponding to the average change of the entire parallel image signal can be obtained.

Since the same differential component is input to the control units 261a to 261f, the common voltage shift correction is applied to the six parallel image signals in the control units 261a to 261f, and the parallel image signal lines Data1 are added. ~ Da
The corrected image signal is output at ta6. The configuration of the control unit 261 is the same as that of the offset control unit 211 of FIG. 8 described above, and the operation thereof also changes the voltage level of the image signal by the output voltage of the differentiating circuit.

For example, when the average voltage value of the six parallel image signals increases, all the image signals Data1
-Data6 is subjected to positive correction, and the voltage level of each image signal Data rises. On the other hand, when this average voltage value decreases, all the image signals Data
Negative correction is applied to 1 to Data 6, and the voltage level of each image signal Data decreases. This operation becomes clear by referring to FIG.

FIG. 16A shows the image signals of the parallel image signal lines Data1 to Data6 when the image signal processing circuit of the seventh embodiment for directly outputting the signal on which the differential component is superimposed to the electro-optical device is used. Is shown. 16A shows parallel image signals Data1 to Data6 before correction obtained by sampling the image signal, and FIG.
16B shows the parallel image signals Data1 to Data1 of FIG.
This is a differential component of the sum of the voltage changes of Data6.

As shown in FIG. 16B, the image signal line D
The respective differential waveforms corresponding to data1 to Data6 are the same, and this differential waveform is the differential waveform of the combined signal obtained by combining all parallel image signals in the differentiating circuit 264. And the parallel image signal lines Data1 to Data
6 shows the image signal VID shown in FIG.
A parallel image signal on which the differential waveform of is superimposed is output.

Depending on the type of electro-optical device, the parallel image signals Data may influence each other,
It may not be possible to sufficiently supplement the performance of the electro-optical device by independently performing correction for each parallel image signal Data. In particular, the sampling circuits 262a-26
The output of the image signal Data from 2f is simultaneously output, the parallel image signals of the plurality of parallel image signal lines Data1 to Data6 are simultaneously sampled by the sampling switches 106a to 106f of FIG. When it is configured to output at the same time,
Image signal lines Data1 to Data6 wired in parallel
The phenomenon that parallel image signals transmitted to each other interfere and influence each other is likely to occur. For example, the image signal Data
The image data of No. 3 rises greatly, and the adjacent image signal D
When the image data of data4 changes downward, Data4
Voltage does not drop to the original voltage level.

In such a case, as in the seventh embodiment, when the voltage level of one parallel image signal is corrected, a change in the voltage level of another parallel image signal is reflected. , Effectively eliminate ghosts,
The quality of the displayed image can be improved. That is, if there is a significantly changed image signal, by shifting the voltage in a direction (voltage change direction) in which the change of the other image signal is emphasized so as to cancel the influence of the image signal on the other image signal, It is possible to compensate for voltage changes of other image signals.

In the present embodiment, the clamp circuit as in the first embodiment is not provided, but the clamp circuit may include an amplifier 205 and a clamp capacitor 208 as shown in FIG. May be provided corresponding to each control unit 261 and the sampling circuit 262. In this case, each amplifier 205 inputs the output of each sampling circuit 262 and charges each clamp capacitor 208 as in the configuration of the first embodiment shown in FIG. The output of the differentiating circuit 264 of FIG. 15 is commonly connected to the other end of each clamp capacitor 208 as in the configuration of FIG. Therefore, each clamp capacitor 2
08 has a configuration in which the other end is connected to the common differential circuit 264 output, and one end is connected to the output of each amplifier 205 and the control input end of each control unit 261. The DC level of each image signal is the reference voltage V _REF. The feedback control of the control unit 202 is performed so that the offset between the image signal lines can be canceled.

(Eighth Embodiment) An eighth embodiment of the image signal processing circuit of the electro-optical device according to the present invention will be described below with reference to FIG. The parts that are not described in the present embodiment are the same as those in the first to seventh embodiments, and the description thereof will be omitted.

In the seventh embodiment, as shown in FIG. 15, the signals on which the differential components are superimposed are once sampled by the sampling circuits 262a to 262f, and the sampled signals are output to the parallel image signal lines Data1 to Data6. However, in the eighth embodiment, the differential component is added to the image signal and the image signal line Data1 of the electro-optical device is added.
~ Output to Data6.

As shown in FIG. 17, the image signal processing circuit of the eighth embodiment has the parallel image signal lines D
sampling circuits 262a to 262f and addition circuits 275a to 275 for data1 to Data6, respectively.
f and all sampling circuits 262
A differentiating circuit 264 common to a to 262f is provided. Similar to FIG. 1, sampling pulses SPa to SPf are sequentially input to the sampling circuits 262a to 262f at a timing shifted by one image data in synchronization with the dot clock DC, image signals are sequentially sampled, and the same timing pulse OUT is output. A parallel image signal is simultaneously output in synchronism with. The pulse OUT is sent to the sampling circuit 262.
The panels a to 262f are sequentially input when the image signals are sampled, and have a cycle obtained by dividing the cycle of the dot clock DC by the number of sampling circuits.

A more detailed block configuration of the sampling circuit 262 of this embodiment is shown in FIG. The sampling circuits 262a to 262f have the same configuration, and the first sampling circuits 262a-1 to 262f have the same configuration.
-2 and the second sampling circuits 262a-2 to 262f.
-2 is provided. First sampling circuits 262a-1 and 262a-2
62f-1 may use the sample hold circuit 204 described in detail in FIG. 3, the circuit 212 in FIG. 8, the circuits 231 and 234 in FIG. 10, the circuits 243 and 244 in FIG. 12, and the circuit 251 in FIG. The sampling pulse generator 209 sequentially inputs the sampling pulses SPa to SPf formed in synchronization with the dot clock DC, and samples and holds the image signal. Sampling pulse SPa
As described in the first embodiment, the symbols ~ SPf are pulses sequentially shifted by one image data cycle of the input serial image signal VID, and consecutive six image data are sequentially sampled by the first sampling. This is a pulse to be taken into the circuit. The first sampling circuits 262a-1 to 262
The image data sample-held at f-1 corresponds to the corresponding second sampling circuits 262a-2 to 262.
It is supplied to f-2, sampled and held by the same pulse OUT, and simultaneously output in synchronization with the pulse OUT. Second sampling circuits 262a-2 to 262f-2
The configuration of 204 is shown in FIG. 3, 212 in FIG. 8, and 2 in FIG.
31 and 234, 243 and 244 in FIG. 12, 25 in FIG.
A circuit such as 1 may be used. The pulse OUT
Is preferably generated in synchronization with or slightly delayed from the sixth sampling pulse SPf.

The combined signal of the output signals of the sampling circuits 262a to 262f is input to the differentiating circuit 264 via each resistor of the resistor group 263, and the differentiating circuit 264 adds the differential component of this combined signal to the adder 275a. Output to ~ 275f. The specific configuration of the differentiating circuit may use the differentiating circuit 206 of FIG. In this case, the input resistor 206c in 206 is replaced with the resistor group 263 in FIG. That is, it is preferable that the input resistance of the resistor group 263 be commonly connected to the input capacitor 206b and input. However, the differentiating circuit is not limited to this configuration, and the output terminals of the resistor group 263 may be commonly connected and commonly input to the differentiating circuit 213 in FIG. With this configuration, the differentiating circuit 264
The signal voltages of the image signals Data1 to Data6 simultaneously output from the sampling circuits 262a to 262f are added by the resistor group 263 to be input to the. Therefore, from the differentiating circuit 264, the parallel image signal Data
Since an output obtained by differentiating the sum of the voltage changes of 1 to Data 6 appears, a differential component corresponding to the average change of the entire parallel image signal can be obtained.

The adder circuits 275a to 275f have the same configuration, and add the image signals simultaneously output from the corresponding sampling circuits 262a to 262f and the differential component output from the differential circuit 264, respectively. As the adder circuits 275a to 275f, adder circuits such as 233 in FIG. 10, 245 in FIG. 12, and 253 in FIG. 13 may be used.

FIG. 16A shows the image signals of the parallel image signal lines Data1 to Data6 when the image signal processing circuit of the eighth embodiment for directly outputting the signal on which the differential component is superimposed to the electro-optical device is used. Is shown. 16A shows parallel image signals Data1 to Data6 before correction obtained by sampling the image signal, and FIG.
16B shows the parallel image signals Data1 to Data1 of FIG.
The differential component superimposed on Data6 is shown.

As shown in FIG. 16B, the image signal line D
The respective differential waveforms corresponding to data1 to data6 are the same, and this differential waveform is shown in FIG. 15 of the seventh embodiment.
Is a differential waveform of the combined signal obtained by combining all the parallel image signals in the differentiating circuit 264. The parallel image signal lines Data1 to Data6 are shown in FIG.
16B is added to the parallel image signal of FIG. 16B to output the superimposed parallel image signal.

As described above, in the image signal processing circuit of the eighth embodiment, when correcting one parallel image signal, the change of the other parallel image signal is reflected, as in the seventh embodiment. Therefore, it is possible to improve the image quality of the display image of the electro-optical device in which the parallel image signals influence each other.

Depending on the type of electro-optical device, the parallel image signals Data may affect each other,
It may not be possible to sufficiently supplement the performance of the electro-optical device by independently performing correction for each parallel image signal Data. In particular, the sampling circuits 262a-26
The output of the image signal Data from 2f is simultaneously output, the parallel image signals of the plurality of parallel image signal lines Data1 to Data6 are simultaneously sampled by the sampling switches 106a to 106f of FIG. When it is configured to output at the same time,
Image signal lines Data1 to Data6 wired in parallel
The phenomenon that parallel image signals transmitted to each other interfere and influence each other is likely to occur. For example, the image signal Data
The image data of No. 3 rises greatly, and the adjacent image signal D
When the image data of data4 changes downward, Data4
Voltage does not drop to the original voltage level.

In such a case, as in the eighth embodiment, when the voltage level of one parallel image signal is corrected, the change in the voltage level of another parallel image signal is reflected. , Effectively eliminate ghosts,
The quality of the displayed image can be improved. That is, if there is a significantly changed image signal, by shifting the voltage in a direction (voltage change direction) in which the change of the other image signal is emphasized so as to cancel the influence of the image signal on the other image signal, It is possible to compensate for voltage changes of other image signals.

Although the clamp circuit as in the first embodiment is not provided in this embodiment, the clamp circuit may be provided with an amplifier 205 and a clamp capacitor 208 as shown in FIG. May be provided corresponding to each control unit 261 and the sampling circuit 262. In this case, each amplifier 205 inputs the output of each sampling circuit 262 and charges each clamp capacitor 208 as in the configuration of the first embodiment shown in FIG. The output of the differentiating circuit 264 of FIG. 15 is commonly connected to the other end of each clamp capacitor 208 as in the configuration of FIG. Therefore, each clamp capacitor 2
08 has a configuration in which the other end is connected to the common differential circuit 264 output, and one end is connected to the output of each amplifier 205 and the control input end of each control unit 261. The DC level of each image signal is the reference voltage V _REF. The feedback control of the control unit 202 is performed so that the offset between the image signal lines can be canceled.

(Modification of Image Signal Processing Circuit) The image signal processing circuit according to the present invention based on each of the above embodiments may be formed on a substrate which constitutes a liquid crystal panel. It may be formed as another external circuit (external IC).

In each of the above embodiments, each pixel is driven by using a thin film transistor (TFT), but an active element such as TFD (thin film diode) other than TFT can be used. It is also possible to configure the liquid crystal device as a passive matrix type liquid crystal device. Further, the image signal processing circuit according to the present invention effectively functions for electro-optical devices other than liquid crystal devices. By correcting the signal according to the characteristics of each electro-optical device, the performance of the electro-optical device can be complemented and its image quality can be improved.

In each of the above embodiments,
There are six parallel image signals and their image signal lines,
The present invention is not limited to this. The number can be increased or decreased according to the switching response of the sampling switch 106. The number of image signal sampling circuits 201 also increases or decreases according to the number. If the responsiveness of the sampling switch 106 is good, the number of the image signal lines Data may be one. Even in the case of one
Adopting the configuration of the present invention is advantageous because it can compensate for delay due to resistance and capacitance of wiring. However, the image signal line is 1
The book-based embodiment cannot be applied to the seventh and eighth embodiments.

In each of the above embodiments,
The image data Data1 to Data6 output from the image signal sampling circuit 201 are output at timings sequentially shifted in synchronization with the dot clock cycle, and sampling by the sampling switch 106 is also performed at timings sequentially shifted in synchronization with the dot clock. However, the present invention is not limited to this. The parallel image data Data1 to Data6 output from the plurality of image signal sampling circuits 201 are output at the synchronized timing, and the sampling switch 106 also samples the parallel image data at the same time, and simultaneously images the corresponding data signal lines 116. It may be configured to supply data.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the gist of the present invention. For example, in the above embodiment, each switch is composed of a TFT, but the substrate may be a semiconductor substrate and each switching element may be a MOS transistor formed on the surface of the semiconductor substrate. In this case, the pixel electrode serves as a reflective electrode and is configured as a reflective liquid crystal device. Further, the present invention is not limited to being applied to the above-mentioned various liquid crystal devices, but can be applied to electroluminescence and plasma display devices.

(Embodiment of Electronic Equipment) Next, an embodiment of electronic equipment provided with the electro-optical device of the present invention described in detail above will be described with reference to FIGS. 19 to 21.

First, FIG. 19 shows a schematic configuration of an electronic apparatus including the above-mentioned electro-optical device. In FIG. 19, the electro-optical device described above is represented as a liquid crystal device 200.

The electronic apparatus shown in FIG. 19 includes a display information output source 1000, an image signal processing circuit 1002, a drive circuit 1004 including the scan line drive circuit 102 and the data line drive circuit 104 described above, a liquid crystal panel block 10, a clock generation circuit. 1008 and a power supply circuit 1010 are provided. The display information output source 1000 is a ROM (ReadOnly
Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit, and the like, and based on a clock from a clock generation circuit 1008, image information such as an image signal of a predetermined format is converted into an image signal processing circuit 1.
Output to 002. The image signal processing circuit 1002 is the image signal processing circuit according to the present invention, and includes an amplification / polarity inversion circuit,
It includes various known processing circuits such as a rotation circuit, a gamma correction circuit, and a clamp circuit, and further includes the sampling circuit of the present invention described above. The drive circuit 1004 drives the liquid crystal panel block 10 by the above-described drive method by the scanning line drive circuit 102 and the data line drive circuit 104 of FIG. 7. The power supply circuit 1010 supplies a predetermined power supply to each of the above circuits. The drive circuit 1004 may be mounted on the TFT array substrate that constitutes the liquid crystal panel block 100, or the image signal processing circuit 1002 may be mounted in addition to this.

Next, with reference to FIGS. 20 and 21, specific examples of the electronic apparatus thus configured will be shown.

(Liquid Crystal Projector) In FIG. 20, a liquid crystal projector 1100, which is an example of electronic equipment, is a projection type liquid crystal projector, and includes a light source 1110, dichroic mirrors 1113 and 1114, and a reflection mirror 111.
5, 1116, 1117, an entrance lens 1118, a relay lens 1119, an exit lens 1120, liquid crystal light valves 1122, 1123, 1124 composed of the image signal processing circuit and electro-optical device of the present invention, and a cross dichroic prism 1125. , Projection lens 112
6 is provided. Liquid crystal light valve 112
Reference numerals 2, 1123, and 1124 are prepared by preparing three electro-optical devices of the present invention described above and using them as liquid crystal light valves. The light source 1110 includes a lamp 1111 such as a metal halide and a reflector 1112 that reflects the light from the lamp 1111.

In the liquid crystal projector 1110 configured as described above, the dichroic mirror 1113 that reflects blue light and green light transmits red light of the white light flux from the light source 1110 and also transmits blue light and green light. To reflect. The transmitted red light is reflected by the reflection mirror 1117 and enters the red light liquid crystal light valve 1122. On the other hand, of the color light reflected by the dichroic mirror 1113, green light is reflected by the green light reflecting dichroic mirror 1114 and is incident on the green light liquid crystal light valve 1123. The blue light also passes through the second dichroic mirror 1114. For blue light,
In order to prevent light loss due to a long optical path, the incident lens 111
8, a relay lens 1119, a light guide means 1121 including a relay lens system including an emission lens 1120,
Blue light is emitted through the liquid crystal light valve 112 for blue light.
It is incident on 4. The three color lights modulated by the respective light valves enter the cross dichroic prism 1125. This prism is formed by laminating four right-angled prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed on the inner surface thereof in a cross shape. Three color lights are combined by these dielectric multilayer films to form light representing a color image. The combined light is projected onto the screen 1 by a projection lens 1126 which is a projection optical system.
The image is projected on 127 and the image is enlarged and displayed.

(Laptop type personal computer) Referring to FIG. 21, a laptop type personal computer 1200 which is another example of an electronic apparatus is a liquid crystal panel block 100 using the above-described image signal processing circuit and electro-optical device of the present invention. Inside the top cover case 1206
Main body 1 which is equipped with a CPU 120, a memory, a modem, and the like, and in which a keyboard 1202 is incorporated.
It is equipped with 204. When the electro-optical device of the present invention is used in such a laptop personal computer 1200, it is possible to display a high-quality image without uneven brightness and uneven color, and compared with a desktop personal computer using a CRT or the like. It is possible to provide a comparable use environment.

In addition to the electronic devices described with reference to FIGS. 19 to 21, a head mounted display, a liquid crystal television, a viewfinder type or monitor direct-view type video tape recorder, a car navigation device, an electronic notebook,
A calculator, a word processor, a workstation, a mobile phone, a videophone, a POS terminal, a device equipped with a touch panel, and the like are examples of the electronic device shown in FIG.

As described above, according to the present invention, the electro-optical device 2 capable of displaying a high quality image without a ghost.
It is possible to realize various electronic devices including 00.

[0172]

The image signal processing circuit of the electro-optical device according to the present invention corrects the image data so as to compensate the performance of the electro-optical device and outputs the corrected image data to the electro-optical device. Ghosting can be suppressed and the image quality can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image signal processing circuit of an electro-optical device according to a first embodiment.

FIG. 2 is an electric circuit diagram showing an image signal sampling circuit.

FIG. 3 is an electric circuit diagram showing a sampling circuit.

FIG. 4 is an electric circuit diagram showing a conventional sampling circuit.

FIG. 5 is a timing chart showing an operation of phase expansion.

FIG. 6 is a timing chart showing a correction operation of a parallel image signal.

FIG. 7 is a diagram showing a configuration of a liquid crystal panel connected to the image signal processing circuit according to the first embodiment.

FIG. 8 is an electric circuit diagram showing a sampling circuit provided in the image signal processing circuit according to the second embodiment.

FIG. 9 is an electric circuit diagram showing a sampling circuit provided in the image signal processing circuit according to the third embodiment.

FIG. 10 is an electric circuit diagram showing a sampling circuit provided in an image signal processing circuit according to a fourth embodiment.

11 is a diagram showing a signal waveform of each part of the sampling circuit of FIG.

FIG. 12 is an electric circuit diagram showing a sampling circuit provided in an image signal processing circuit according to a fifth embodiment.

FIG. 13 is an electric circuit diagram showing a sampling circuit provided in an image signal processing circuit according to a sixth embodiment.

14 is a diagram showing a signal waveform of each part of the sampling circuit of FIG.

FIG. 15 is an electric circuit diagram showing an image signal processing circuit according to a seventh embodiment.

FIG. 16 is a diagram showing the correction processing of the parallel image signal in the image signal processing circuit according to the eighth embodiment by the waveform of each part.

FIG. 17 is an electric circuit diagram showing an image signal processing circuit according to an eighth embodiment.

FIG. 18 is a block diagram showing details of a sampling circuit according to seventh and eighth embodiments.

FIG. 19 is a schematic configuration diagram of an electronic device of the invention.

FIG. 20 is a configuration diagram of a liquid crystal projector showing an example of an electronic apparatus of the invention.

FIG. 21 is a schematic view of a personal computer showing an example of an electronic apparatus of the invention.

[Explanation of symbols]

110 scan lines 112 data signal line 204 sampling circuit 206 Differentiation circuit Data1 to Data6 parallel image signal lines

Claims (6)

(57) [Claims] 1. An image signal processing circuit for sending an image signal to an electro-optical device comprising a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning lines, images input in time series Means for parallelly outputting a plurality of image signals obtained by sequentially sampling the signals to a plurality of image signal lines, and a correction value based on a change in the value of the image signal output to the predetermined image signal line, An image signal processing circuit, comprising: a correction unit that corrects the image signal output to the image signal line. 2. An image signal processing circuit for transmitting an image signal to an electro-optical device comprising a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning lines, images input in time series A plurality of image signals obtained by sampling the signal, means for parallel output to a plurality of image signal lines, and a signal corresponding to the sum of the differential components of the plurality of image signals output to the plurality of image signal lines An image signal processing circuit comprising: a differentiating circuit for outputting; and a correcting means for adding a correction value corresponding to a signal corresponding to the sum of the differential components to the plurality of image signals. 3. An image signal processing circuit for sending an image signal to an electro-optical device comprising a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning lines, the image signal processing circuits being inputted in time series. A plurality of image signals obtained by sampling the image signal, the means for parallel output to a plurality of image signal lines, a differentiating circuit to which a composite signal obtained by combining the plurality of parallel output image signals is input, An image signal processing circuit, comprising: a signal output from the differentiating circuit, wherein the plurality of image signals are respectively corrected by inputting the signals to the parallel output unit. 4. An image signal processing circuit for sending an image signal to an electro-optical device comprising a plurality of pixels formed by intersections of a plurality of data signal lines and a plurality of scanning lines, the image signal processing circuits being inputted in time series. A plurality of image signals obtained by sampling a plurality of image signals, and a means for parallelly outputting the plurality of image signal lines, and a differentiating circuit to which a composite signal obtained by combining the plurality of parallel output image signals is input. An image signal processing circuit, comprising: an adding circuit that adds each of the signals output from the differentiating circuit and the plurality of image signals output in parallel. 5. An electro-optical device comprising the image signal processing circuit according to claim 1. Description: 6. An electronic apparatus comprising the electro-optical device according to claim 5.