JP3421564B2 - Display device driving method and driving circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a driving circuit of a display device, and more particularly to a waveform shaping of an original image signal in consideration of distortion of a pixel signal finally supplied to a display pixel. is there.

[0002]

2. Description of the Related Art Flat panel displays such as liquid crystal display (LCD), organic electroluminescence (EL) display, and plasma display have been actively developed. Among them, LCDs are excellent in thinness and low power consumption, and have become the mainstream of monitor displays in the fields of AV equipment and OA equipment.

The LCD has a liquid crystal sealed between a pair of opposing substrates. A large number of electrodes for applying an electric field to the liquid crystal to drive the liquid crystal are formed on the opposing inner surfaces of each substrate, and a display pixel is configured as a capacitor having the liquid crystal as a dielectric layer. The display pixels are arranged in a matrix (matrix), and in particular, a display element in which a thin film field effect transistor (TFT) is connected and formed as a switching element to each is arranged in a matrix is an active matrix type. be called. In the active matrix type, the display pixel voltage is sequentially applied and the display pixel voltage can be held during the non-selection period to continue the display, and a high-quality display screen can be obtained.

In recent years, as a TFT, a polycrystalline semiconductor, particularly polysilicon (p-Si) has been used instead of an amorphous semiconductor, especially amorphous silicon (a-Si), which has been used as an active layer until then. The switching operation speed has increased, and along with this, the effective display area has been expanded due to the small size of the TFT, or the high definition has been achieved due to the downsizing of the display element, resulting in extremely high image quality. Further, the driver circuit for driving the display element is required to operate at a higher speed than the display element, but it becomes possible to form a CMOS by the p-Si TFT, and the driver circuit is integrally formed on the same substrate. be able to. Such an LCD with a built-in driver has advantages such as a low manufacturing cost and a small frame portion around the display screen, and thus mass production is desired.

FIG. 12 shows the structure of the LCD module. The signal processing circuit (1) is supplied with R, G, B video signals VIDEO from the outside, and creates predetermined original image signals VDR, G, B. This original image signal is passed through the buffer circuit (2) to L
It is supplied to the drain driver (6) of the CD (4).
On the other hand, the timing controller (3) is supplied with a synchronization signal SYNC from the outside to generate various timing control signals. Further, in the signal processing circuit (1), based on the sample hold signal generated by the timing controller (3), as will be described later in detail, the original image signals VDR, G, B
Is divided and expanded into multiple phases. Drain driver (6)
Performs sampling of the original image signals VDR, G, B based on the horizontal shift clock and horizontal start pulse created by the timing controller (3) to control the sampling operation, as described later. Also LCD (4)
The gate driver (5) is mainly composed of a vertical shift register, and a vertical shift clock and a vertical start pulse are supplied from the timing controller (3).

The LCD (4) has a large number of gate lines (4
1) and the drain line (42) are arranged vertically and horizontally, and at the intersection thereof, the TFT (4
3) and the liquid crystal capacitance (4
3) and the auxiliary capacitance (44) for storing charges are formed to form a display element. The gate driver (5) performs row scanning to sequentially select the gate lines (41).
The drain driver (6) sequentially supplies pixel signals sampled from the original image signal in order to drive each display element during the row selection period. Here, the TFT (43) is a p-Si TFT, and the gate driver (5) and the drain driver (6) also have the same structure as the p-Si TFT.
CMOS composed of TFT, LCD (4)
The gate driver (5) and the drain driver (6) are integrated into a driver built-in type.

FIG. 13 shows the structure of the drain driver. The upper stage of the figure is a horizontal shift register (61), the middle stage is an original image signal line (62), and the lower stage is a sampling switch (63). The horizontal shift register (61) has two series, and each set of sampling switches (63) controlled by the same output stage S / R is alternately connected to different series. These horizontal shift registers (6
The horizontal start pulse STH1,2 and the horizontal shift clock CKH1,2 are sent from the timing controller (3) to 1), the sampling pulse SP is generated from each output stage S / R, and the sampling switch (63) is turned on. Turn on in order. The horizontal start pulses STH1 and STH2 and the horizontal clock pulses CKH1 and CKH2 are different in phase by 90 °, and the output stage from each horizontal shift register (61) is different.
The sampling pulse SP output from S / R has a phase difference of 90 ° between sequences. That is, they overlap for a 1/2 cycle period. The original image signals VDR, G, B of R, G, B are sent from the buffer circuit (2) to the original image signal line (62), and the sampling switch (63) is turned on.
To the drain line (42) via the original signal VDR, G, B
Is transmitted and the voltage at the time when the sampling switch (63) is turned off is sampled as the pixel signal PX. The original image signals VDR, G, B are processed by the signal processing circuit (1) into R, G, B.
Each of the signals is divided and expanded into four-phase signals and supplied to the original image signal line (62).

Here, the original image signal VD divided and expanded into four phases
Each of R, G, and B includes every four pixel signals for each of R, G, and B, and is configured to sample these at the same time. In this way, by dividing and expanding into a plurality of sequences, the period of each original image signal is lengthened, the influence of signal distortion is suppressed, and the operating speed of the sampling switch (63) composed of p-SiTFT is compensated. .

Moreover, in the example given here, the period of the sampling pulse SP outputted from each output stage S / R of the horizontal shift register (61) consisting of two series is divided into four phases of the original picture signal and expanded. It is four times more. That is, the sampling switch (63) is turned on for 16 dots. Therefore, the operation speed required for the horizontal shift register (61) and the sampling switch (63) can be reduced, and the p-Si TFT can be adopted.

[0010]

However, the original image signal is distorted in waveform due to the integrating circuit composed of the parasitic resistance and the parasitic capacitance in the drain driver (6), and as a result, the amplitude of the pixel signal voltage decreases, There is a problem that the brightness or the contrast ratio is lowered. Further, regarding the same series, the pixel signal supplied to the previous column affects the pixel signal supplied to the subsequent column. As a result, in the configuration shown in FIG. 13 in which the same series corresponds to every several columns, the influence of a certain column affects the columns adjacent to the several columns and is recognized as a ghost, which adversely affects the display.

Such a problem is as shown in FIG.
The original image signal is divided into a plurality of phases and expanded, and the frequency is lowered, so that it can be solved to some extent. However, the effect is diminished due to the shortening of the sampling time due to the high definition and the increase of the capacitive load and the resistive load on the signal path due to the large screen. Further, although the number of divisions can be increased in order to solve such a problem, the signal processing circuit (1) and the drain driver (6) are complicated and the cost is increased.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, in which display elements, which are display pixels, are arranged in a matrix, and a pixel signal is sampled from an original image signal and supplied to the display element. Thus, in the driving method of the display device for driving the display element, the first predetermined period in each pixel period of the original image signal is a pixel period of the display element to be driven and a plurality of pixel periods before the fixed period. The amplitude is amplified or attenuated according to the difference from the original image signal in.

Further, a display device for driving the display elements by arranging display elements which are display pixels in a matrix and sampling pixel signals from an original image signal by a sampling switch and supplying the sampled pixel signals to the display elements. In the drive circuit, the input original image signals are input to n, 2n,
..., mn (n is a natural number, m is an integer of 2 ≦ m ≦ n−1) pixel periods, and the first, second, ..., Mth delay circuits and the first, second ,. The first, second, ..., Mth difference signals output from the mth delay circuit and the mth delay signal and the input original image signal are taken, and the first, second, ..., Mth difference signals are generated. , The second, ..., The m-th subtraction circuit, and the first,
A correction operation circuit for generating an amplitude adjustment signal based on the second, ..., Mth difference signals, and the input original image signal n for each pixel.
The signal is divided into a series of signals, and its cycle is expanded by n times, and the amplitude of the original predetermined period of each pixel signal thus divided / expanded in the first predetermined period is set to a desired width based on the amplitude adjustment signal. This is a configuration including a control circuit that amplifies or attenuates and supplies the amplified sampling switch.

As a result, the beginning portion of each pixel signal period of the original image signal is shaped into a convex shape as compared with the pixel signal period immediately before, so that the convex portion is absorbed by the signal distortion, Signal distortion is suppressed. Further, the correction amount that is such a convex portion is the difference from the immediately preceding pixel signal, and
The optimum pixel signal voltage can be supplied to each display element because the pixel signal voltage is optimally adjusted according to the difference from the plurality of pixel signals before that.

[0015]

1 is a block diagram of a signal processing circuit for realizing a method for driving a display device according to a first embodiment of the present invention. The configuration of the signal processing circuit described here is the same for R, G, and B. A first delay circuit (11) including four flip-flops (191),
Second to third delay circuits (121, 122), correction amount calculation circuit (13), addition / subtraction circuit (14) and first to fourth
The division / decompression circuit (151, 152, 153, 154) of FIG. First to third delay circuits (11, 121, 12
2) are connected in series. Dividing / expanding circuit (151,
152, 153, 154) includes a first sample-hold circuit (16), a second sample-old circuit (17), and a selection circuit (18). Digital signals R and G
Alternatively, the original pixel data VD of B is the first delay circuit (11).
Is supplied to. The first delay data DL1 output from the first delay circuit (11) is supplied to the correction amount calculation circuit (13) and the second delay circuit (121), and output from the second delay circuit (121). The generated second delay delay data DL2 is supplied to the correction amount calculation circuit (13) and the third delay circuit (122), and the third delay data DL3 output from the third delay circuit (122) is corrected. It is supplied to the quantity calculation circuit (13). That is, the original original pixel data VD, the delay data DL1 delayed by 4 pixel periods (dots), the second delay data DL2 delayed by 8 dot periods, and the third delay data DL3 delayed by 12 dot periods are included. It is supplied to the correction amount calculation circuit (13).

The correction amount calculation circuit (13) examines the original pixel data VD and the first to third delay data DL1,2,3, as described later in detail, and thereby the original pixel data corresponding to the original pixel is obtained. The difference between the pixel data VD and the original pixel data 4 dots before is determined by the absolute value of the difference and the size of the original pixel data 8 dots before the pixel and the original pixel data 12 dots before. Amplify or attenuate accordingly to create the amplitude adjustment data ED. Here, 4 dots before, 8 dots before and 1
The original pixel data of 2 dots before is the original pixel data of 1 dot before, 2 dots before, and 3 dots before after being divided and expanded into 4 series. The amplitude adjustment data ED is supplied to the adder / subtractor circuit (14) via the flip-flop (194). The original pixel data VD whose timing is adjusted by way of the flip-flop (192) is also supplied to the adder / subtractor circuit (14), and the amplitude adjustment data ED is added or subtracted to this original pixel data VD. By doing so, the correction data RD is created.

The original pixel data VD and the correction data RD are
The first to fourth division / expansion circuits (15) are synchronized with each other through the flip-flops (193) (195).
1, 152, 153, 154) and a second sample and hold circuit (16) and a second sample and hold circuit (1)
7). The first to fourth division / expansion circuits (151, 152, 153, 154) include pixel signals for every 4 dots which are different from each other, as will be described later.
Corrected original image signal data VDD1,2,3,4 having a doubled cycle and optimally corrected are created. These four series of corrected original image signal data VDD1, 2, 3, 4 are similarly created for R, G, and B. The corrected original pixel data VDD1,2,3,4 obtained for R, G, and B thus obtained are sent to the buffer circuit (2) shown in FIG. 12, where D / A conversion and amplitude amplification are performed. , Corrected original image signal VDR1,2,3,4, VDG1,2,3,4, VDB1,2,3,4
Is supplied to the corresponding original image signal line (62) of the drain driver (6).

FIG. 2 is a configuration diagram of the correction amount calculation circuit (13) according to the embodiment of the present invention. The first to third subtraction circuits (21, 22, 23), the first address generation circuit (24) forming the correction value generation circuit, and the correction value memory (2
5), a second address generation circuit (26), a magnification memory (27) and a multiplication circuit (28). The original original pixel data VD and the first delay data DL1 are supplied to the first subtraction circuit (21), and the first difference data DF1 is generated from this, and the first address generation circuit (24) is generated. Supply to.
The first address generation circuit (24) uses the first difference data
An address is generated based on DF1, and the correction value is read from the correction value memory (25). This correction value becomes larger as the difference between the original pixel data VD concerned and the original pixel data VD four dots before that becomes larger. For this,
It will be described in detail later. This correction value is supplied to the multiplication circuit (28).

Further, second to third subtraction circuits (22, 2)
3) is supplied with the original original pixel data VD and the second and third delay data DL2,3, respectively, and generates the second and third difference data DF2,3 based on this, It is supplied to the second and third address generation circuits (26, 27). The second address generation circuit (26) generates a row address based on the second address generation circuit (26), the third address generation circuit (27) generates a column address, and reads the magnification value from the magnification memory (28) to multiply it. Supply to (29). The magnification memory (28) holds the magnification with the difference between the original pixel data VD and the original pixel data 8 dots before it and the difference between the original pixel data 12 dots before it and the matrix position. Has been done. That is,
The read magnification value is a value corresponding to the difference between the original pixel data VD and the original pixel data 8 dots before and the original pixel data 12 dots before. The magnification values held in the magnification value memory (28) are arranged with a larger interval in the row direction than in the column direction. This is because, as will be described later in detail, the difference from the data of 8 dots before has a greater effect on the original pixel data than the difference from the data of 12 dots before. When the cost is emphasized, the difference data DF2,3 supplied to the second address generation circuit (26) and the third address generation circuit (27) is reduced to only a predetermined number of high-order bits, and the scaling factor is increased. The number of bits of the memory (28) can be reduced. In this case, the number of bits of the correction amount decreases.

The correction value and the magnification value are multiplied by the multiplication circuit (29), and as a result, the original pixel data
The difference between the VD and the original pixel data 4 dots before is the magnitude of the difference, and the difference between the original pixel data VD and the original pixel data 8 dots before and the original pixel data 12 dots before Amplitude adjustment data ED adjusted according to is created.

FIG. 3 is a more detailed block diagram of the first division and expansion circuit (151) shown in FIG. The two D-FFs (31) and (32) forming the first sample hold circuit (16) for the original pixel data VD, and the correction data RD
For configuring a second sample and hold circuit (17) for
D-FFs (33) (34) and a selection circuit (1
8) and two AND circuits (35) (36) and O
It consists of an R circuit (37).

Further, a horizontal synchronizing pulse HSYNC and a dot clock DCK are supplied to the clock frequency dividing circuit (38) to divide the dot clock DCK by 1/4, and a 1/4 duty whose phase is different by 90 °. 4 sample-and-hold clocks CK1, 2, 3, and 4 are created. The first to third division / expansion circuits (151, 152, 153) are shown in FIG.
The first sample-hold circuit (151) includes a sample-hold clock CK1 and a sample-hold clock CK4 from the clock divider circuit (38).
Is supplied, and the sample hold clock CK1 is D-FF.
The sample-hold clock CK4 is supplied to the clock inputs of (31) and (33) to the D-FFs (32) and (34). Further, the sample hold clock CK4 is supplied to the switching timing control circuit (39) together with the other clock CK5 created by the clock frequency dividing circuit (38). For example, the sample hold clock CK4 selected by the switching control timing circuit (39) is used as an AND circuit (3) as the selection switching clock SEL and its inverted clock.
6) and one input terminal of the AND circuit (35). In addition, four division / expansion circuits (151, 152,
153, 154), a clock divider circuit (38)
The switching timing control circuit (39) is common.

The original pixel data VD is the D of the D-FF (31).
It is input to the terminal and its Q output LV1 is the next D-FF (3
It is input to the D terminal of 2). On the other hand, the correction data RD is D
It is input to the D terminal of the -FF (33), and its Q output LR1 is input to the D terminal of the next D-FF (34). In this way, the original pixel data VD and the correction data RD are sampled and held by the sample and hold clock CK1 and divided and expanded, and the phases are aligned with the other divided and expanded circuits (152, 153, 154) by the sample and hold clock CK4. The Q outputs of these D-FFs (32) are AND circuit (35) as original pixel data vd1 which is divided and expanded.
The Q output of the D-FF (33) is supplied to the other input terminal of the AND circuit (3
6) is supplied to the other input terminal.

Either one of the AND circuits (36) and (35) is selected based on the selected clock SEL and its inverted clock. That is, the original pixel data vd1 or the correction data rd1 is switched and selected and output via the OR circuit (37). The output of the OR circuit (37) is divided and expanded, and is output as corrected original pixel data VDD1 whose amplitude is adjusted in the first ¼ period of each pixel signal period.

The second and third division / expansion circuits (152,
153), instead of the sample and hold clock CK1, the sample and hold clocks CK2 and CK having different phases are provided.
3 is supplied, and corrected original pixel data VDD2 and VDD3 respectively corresponding to columns different from the first division / expansion circuit (151) are created. FIG. 4 is a block diagram of the fourth division expansion circuit (154). D-FF (31) forming the first sample-hold circuit (16) for the original pixel data VD, D-FF forming the second sample-hold circuit (17) for the correction data, and selection circuit Two AND circuits (35) and (36) and an OR circuit (37) that form (18)
Consists of. The sample-hold clock CK4 is supplied to the clock inputs of the D-FFs (31) and (33).
This sample-hold clock CK4 is common to division expansion and phase alignment.

5 and 6 respectively show the original pixel data in the sample hold circuits (16) and (17).
FIG. 7 is a timing diagram showing how VD and amplitude adjustment data RD are divided and expanded. In addition, FIG. 7 shows original pixel data vd1,2,3,4 and amplitude adjustment data rd1,2,3,4 which are divided and expanded.
The four corrected original pixel data VDD1,2,
FIG. 6 is a timing diagram showing how 3, 4 are created.

First, referring to FIGS. 5 and 6, original pixel data VD in which pixel data VDn corresponding to each pixel are arranged in series
And the correction data RD corresponding thereto are taken in every four pixels for each series by the sample and hold clocks CK1, 2, 3, 4 and divided and expanded into four phases (LV1, 2, 3, vd4, LR).
1,2,3, rd4), and the sample-and-hold clock CK4 aligns them in the same phase (vd1,2,3,4, rd1,2,3,4). The sample and hold clock CK4 serves both to fetch the fourth series of original pixel data VDn and to match the phase (v
d4, rd4). These divided and expanded original pixel data vd1,2,
3, 4 and the correction data rd1, 2, 3, 4 have a cycle of 4 dot periods.

In FIG. 7, by switching by the AND circuits (35, 36) shown in FIGS. 3 and 4, the original pixel data vd1, 2, 3, 4 at the beginning of the divided / expanded pixel data vd1, 2, 3, 4
The correction data rd1, which is similarly divided and expanded for four periods,
Replaced by 2,3,4. The corrected original pixel data VDD1,2,3,4 thus obtained is the correction data RDn in which the data corresponding to one pixel is divided and expanded in the 4-dot period and the amplitude of the first 1-dot period is adjusted. Yes,
The subsequent 3-dot period is the original pixel data VDn.

In particular, the corrected original pixel data VDD1, 2, 3, 4 is 4
Since it is double-expanded and the amplitude adjustment period is a 1/4 cycle period, that is, the base 1 dot period, the sample hold clock CK4 is used as it is as the selection clock SEL, and the data correction of 1: 3 is performed. There is. Therefore, signal processing is realized with a relatively simple configuration. other,
For example, when performing a 1: 1 correction, a 1/2 duty clock CK created by the clock divider circuit (38)
5 is switched in the switching timing control circuit (39) instead of the sampling clock CK4, and the selected clock
It is realized by using SEL.

FIG. 8 is a timing chart for explaining the operation of the drain driver (6) in the present invention, showing the relationship between the corrected original image signals VDD1, 2, 3, 4 and the sampling pulses SP1, 2. Each of these four corrected original image signals VDD1, 2, 3, and 4 is an original pixel signal (..N-4, N, N + 4, ..) (. -3
N + 1, N + 5, ..) (.., N-2, N + 2, N +
6, ..) (.., N-1, N + 3, N + 7, ..). Sampling pulse S alternately output from each output stage S / R of the first and second horizontal shift registers (61)
P1,2 has an ON period that is four times the cycle of the corrected original image signals VDD1,2,3,4. That is, for each series, the sampling period starts three pixels before the pixel signal to be supplied to the column, and the sampling switch (63) is on during this period.

FIG. 9 is a waveform diagram comparing the respective cases of the original image signal supplied to the drain driver (6). Figure 9
(A) is a conventional waveform which is the original image signal immediately before being supplied to the drain driver (6) without any shaping, and FIG. 9 (b) is an original image signal waveform when this signal is actually supplied to the display element. 9 (c) shows the waveform of the corrected original image signal waveform-shaped according to the present invention immediately before being supplied to the drain driver (6), and FIG. 9 (d) shows the time when this signal is actually supplied to each display element. It is the original image signal waveform. Further, FIGS. 9E and 9F are comparative examples, and are original image signal waveforms when the original image signals up to immediately before the same series influence the original image signal.

The conventional original image signal shown in FIG. 9 (a) is used for amplitude amplification after D / A conversion in the buffer circuit (2).
Alternatively, a signal load due to a capacitive load of the original image signal line (62) in the drain driver (6), an ON resistance of a sampling switch (63) including a p-SiTFT, and a signal due to a capacitive load of the drain line (42). Conventional signal processing circuit due to distortion (1)
The original image signal created in 1 is considerably distorted, and the waveform of the original image signal actually supplied to the display pixel is as shown in FIG. 9B. Therefore, the sampled pixel signal does not reach the desired pixel signal voltage value PX.

In the present invention, in the digital processing stage in the signal processing circuit (1), as shown in FIG. 9 (c), one of the same series in the beginning predetermined period of the data signal N corresponding to the pixel. Data signal N corresponding to the previous pixel
-4, the waveform is shaped into a convex shape by adjusting the amplitude according to the difference between the data signal N-8, the data signal N-8 immediately before, and the difference between the data signal N-12 three times before. , The edge with the previous data signal is emphasized. That is, when the data signal N is larger than the previous data signal N-4, the amplitude is larger (convex upward), and when the data signal is smaller than the previous data signal, the amplitude is smaller. (Convex facing downward). As a result, as shown in FIG. 9D, the distortion of the signal is alleviated by absorbing this convex correction portion, and at the sampling time at the end of the data signal corresponding to each pixel, the predetermined pixel signal The voltage value PX is reached.

In particular, as shown in FIG. 8, in such a signal distortion, in a configuration in which the sampling period is longer than that of each pixel signal, the pixel period (preceding that period included in the sampling period) ( N-8, N-12). That is, during the sampling period,
The previous data signal applied to the drain line (42) affects the pixel signal in question. For example, in FIG.
In (e), although not shown, the second and third previous data signals have relatively small values, and the data signals are affected by the signal delay, and the desired pixel signal voltage PX is not reached. ing. Further, in FIG. 9F, conversely, the data signals two and three before have relatively large values, which exceed the desired pixel signal voltage PX. As described above, it is still insufficient to correct the data signal based on the difference between the data signal and the immediately preceding signal.
With the configuration shown in FIG. 2, the difference between the data signal in question and the immediately preceding data signal is determined based on not only the magnitude of the difference but also the magnitude of the difference between the second previous data signal and the third previous data signal. By correcting, such a problem is solved.

FIG. 10 is a configuration diagram of another correction amount calculation circuit (13) according to the embodiment of the present invention. Compared with the correction amount calculation circuit shown in FIG. 2, instead of the second and third address generation circuits (26, 27) and the magnification memory (28), fourth and fifth address generation circuits (41, 43) are used. ),
Second and third magnification memories (42, 44) and an adder circuit (45) are provided. With this configuration, the second and third
Second and third output from the subtraction circuit (22, 23) of
Difference data DF2,3 are supplied to the fourth and fifth address generation circuits (41, 43) to generate addresses, and the second and third magnification memories (42, 44) are respectively generated.
The magnification value is read out. For these magnification values, the interval between the values held in the second magnification memory (42) is smaller than the interval between the values held in the third magnification memory (44) for the same reason as in the configuration shown in FIG. Has also been made larger. The magnification values read from the second and third magnification memories (42, 44) are added by the adder circuit (45). As a result, the magnification value output from the adder circuit (45) is as shown in FIG.
The same as the magnification value output from the magnification memory (28). The output from the addition circuit (45) is the multiplication circuit (29).
Is supplied to.

FIG. 11 shows a signal processing circuit for realizing the driving method of the display device according to the second embodiment of the present invention. In the present embodiment, the amplitude adjustment data ED output from the correction calculation circuit (13) is directly fed to the division / expansion circuit (1
51, 152, 153, 154) to the second sample and hold circuit (17). Further, each division / expansion circuit (151, 152, 153, 154) has a first and second
Sample hold circuit (16, 17), adder / subtractor circuit (141), and second sample hold circuit (1)
7) and a mask circuit (171) provided between the adder / subtractor circuit (141).

With this configuration, the amplitude adjustment data ED supplied to the second sample hold circuit (17) is the original pixel data VD supplied to the first sample hold circuit (16).
Together with this, it is divided and expanded into four series. The divided and expanded amplitude adjustment data ED is masked by the mask circuit (17) controlled by the same selection switching clock SEL as in the first embodiment.
According to 1), the original pixel data vd1,2, which are supplied to the addition / subtraction circuit (141) and are divided and expanded in a predetermined period, for example, in a form in which the amplitude is eliminated except for the first dot period of each pixel signal period, It is added to or subtracted from 3,4. As a result, the same corrected original pixel data VDD1,2,3,4 as in the above-described embodiment is obtained.

[0038]

As is apparent from the above description, the original image signal to be supplied to the display device or the like is divided and expanded into a plurality of series, and the signals corresponding to the display pixel in a plurality of previous pixel periods in the same series. By correcting the original image signal according to the difference from the original image signal, distortion at the time of signal change was alleviated, contrast ratio and brightness were improved, and good display was obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a signal processing circuit according to a first embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a main part of the signal processing circuit according to the exemplary embodiment of the present invention.

FIG. 3 is a partial detailed configuration diagram of a signal processing circuit according to the exemplary embodiment of the present invention.

FIG. 4 is a partial detailed configuration diagram of the signal processing circuit according to the exemplary embodiment of the present invention.

FIG. 5 is a timing chart of signal processing according to the exemplary embodiment of the present invention.

FIG. 6 is a timing chart of signal processing according to the exemplary embodiment of the present invention.

FIG. 7 is a timing chart of the signal processing according to the embodiment of the present invention.

FIG. 8 is a waveform diagram of signals according to the exemplary embodiment of the present invention.

FIG. 9 is a waveform diagram of signals according to the exemplary embodiment of the present invention.

FIG. 10 is a main part configuration diagram of another signal processing circuit according to the first exemplary embodiment of the present invention.

FIG. 11 is a configuration diagram of a signal processing circuit according to a second embodiment of the present invention.

FIG. 12 is a configuration diagram of a conventional LCD module.

FIG. 13 is a configuration diagram of a drain driver.

[Explanation of symbols]

11,121,122 delay circuit 13 Correction amount calculation circuit 14,141 adder / subtractor circuit 151, 152, 153, 154 Split expansion circuit 16,17 Sample and hold circuit 18 selection circuit 19 flops flops 21,22,23 Subtraction circuit 24, 26, 27 address generation circuit 25 Correction value memory 28 magnification memory 29 Multiplier circuit 171 mask circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-4-307592 (JP, A) JP-A-10-274968 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 H04N 5/66-5/74

Claims (9)

(57) [Claims] 1. A method of driving a display device, comprising display elements, which are display pixels, arranged in a matrix, and driving the display element by sampling a pixel signal from an original image signal and supplying the sampled signal to the display element. , The first predetermined period in each pixel period of the original image signal,
A method of driving a display device, wherein an amplitude is amplified or attenuated according to a plurality of differences between a pixel period of the display element to be driven and a plurality of original image signals in a plurality of pixel periods before a certain period of time. 2. The amplitude of the original image signal is amplified or attenuated by being greatly affected by the difference from the original image signal in the pixel period before the certain period closer to the pixel period of the display element to be driven. The method for driving a display device according to claim 1, wherein the display device is driven. 3. A display device for driving a display element, wherein display elements which are display pixels are arranged in a matrix, and a pixel signal is sampled from an original image signal by a sampling switch and is supplied to the display element. In the drive circuit, input original image signals are delayed by n, 2n, ..., Mn (n is a natural number, m is an integer of 2 ≦ m ≦ n−1) pixel periods, and the first, second and second delays are performed. ..., m-th delay circuit and first, second, ..., first-th output from the m-th delay circuit
The first, second, ..., Mth difference signals are generated by taking the difference between the second, ..., Mth delay signal and the input original image signal. An m-th subtraction circuit, a correction calculation circuit that generates an amplitude adjustment signal based on the first, second, ..., M-th difference signals, and the input original image signal for each pixel n
The signal is divided into a series of signals and its cycle is expanded by n times, and the amplitude of the first predetermined period in the pixel period of each original image signal thus divided and expanded into n pixel periods is used as the amplitude adjustment signal. A drive circuit for a display device, comprising: a control circuit which amplifies or attenuates a desired width based on the above and supplies the sample switch with the control signal. 4. The amplitude adjusting circuit adjusts the amplitude by amplifying or attenuating the amplitude of the first difference signal in a desired width according to the amplitude of the second, ..., Mth difference signals. The drive circuit of the display device according to claim 3, wherein the drive circuit generates a signal. 5. The original image signal is the h-th signal (h is 2 ≦ h).
4. The drive circuit for a display device according to claim 3, wherein the desired width is amplified or attenuated by being influenced by the (h-1) th differential signal more than the differential signal of (.ltoreq.m). 6. The control circuit adds and subtracts the amplitude adjustment signal and the input original image signal to generate a correction signal, and the input original image signal and the correction signal are n-series for each pixel. And a selection circuit for switching between the n-series original image signals and the correction signals thus divided and expanded. The drive circuit of the display device according to claim 3. 7. The control circuit divides the input original image signal and the amplitude adjustment signal into n series signals for each pixel,
Further, a division / expansion circuit for expanding the period by n times, and addition / subtraction for adding or subtracting similarly divided / expanded amplitude adjustment signals to each of the n series of original image signals thus divided / expanded only during the predetermined period. a drive circuit for a display device according to claim 3 in any one of claims 5, characterized in that it comprises a circuit. Wherein said predetermined time period, the driving circuit of a display device according to claim 3 in any one of claims 7, characterized in that one pixel period. 9. The sampling switch comprises n. (M
9. The drive circuit of the display device according to claim 3, wherein the drive circuit is conductive for +1) pixel period.