JP2005037711A - Driving circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the degradation in luminance, the deterioration of vertical contrast, etc., by correcting the distortion of a driving waveform of a matrix type display device. <P>SOLUTION: A clock CKL 2 of a frequency of N times the clock of a frequency of 1H is used. A correction value formed by a configuration of a digital differentiating circuit is added to data B in a row direction of absence of correction (at the time of no load) of a display panel. The driving waveform D formed from the row direction data added with the correction value is subjected to correction of distortion and is made steep in a front edge and rear edge. Consequently, the degradation in the luminance of each pixel can be corrected and the deterioration in the vertical direction contrast can be corrected without sacrificing the resolution in a level direction. Also, the amount of correction is regulated based on the correction data stored in a memory and therefore the difference in the light emission characteristics of the pixels can be corrected as well and uniform light emission of the respective pixels is made possible. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a driving circuit and a display device applied to a matrix type display device in which a plurality of pixels are formed in a matrix.

  A plasma display panel display (PDP), a field emission display (FED), an electroluminescence (EL) display, a liquid crystal display (LCD), etc. have a plurality of pixels. It has pixels formed in a matrix. In such a matrix type display device, luminance unevenness unique to each device occurs, and the brightness of each pixel does not reach a value as designed, and they vary. As one method of correcting these (hereinafter referred to as uniformity correction), a correction method using a drive circuit has been proposed.

  This method basically stores correction data (for example, gain) for each display pixel in an external memory or the like, and reflects the data on a drive signal at the time of display. At this time, since the amount of memory depends on the image size and increases, for example, the following Patent Document 1 describes storing data at certain intervals and calculating a correction amount between data. ing.

JP-A-11-113019

  However, uniformity correction by such signal processing has a problem in that the level of resolution in the level direction is deteriorated as a result of changing the input level to the drive circuit by calculation.

  In most of the display devices currently in practical use in the conventional matrix display devices, the drive circuit for driving each display element is installed in the peripheral portion of the display device or the display device. For this reason, the distance between each pixel and the driver is different for each pixel, and since there is a wiring capacitance, there is a problem that not only the actual voltage to be applied varies but also the response characteristics fluctuate.

  There are mainly four reasons why this problem occurs. First, with respect to the column direction (vertical direction), each pixel displaying an image has a different distance from the drive circuit (column driver), and the value of the wiring resistance (column wiring resistance) is different for each pixel. Different. The load on the drive circuit becomes smaller as the distance is shorter. When the load is small, bright light emission is possible. Secondly, in the row direction (horizontal direction), the distance between the drive circuit (low driver) and each pixel is different, and therefore the value of the wiring resistance (low wiring resistance) is different for each pixel. The load on the drive circuit becomes smaller as the distance is shorter. When the load is small, bright light emission is possible. Third, each pixel has a resistance component, and the value of the resistance value for driving the pixel varies due to manufacturing variations, so that the applied voltage value in each pixel is different. Fourthly, each pixel has a capacitance component at a position where the electrodes in the row direction and the column direction intersect, and the load of the drive circuit varies depending on the distance from the drive circuit, as with the wiring resistance, due to the capacitance component.

  For example, even if the row direction data is a pulse waveform, the drive waveform when the display panel is connected is a waveform with no rising and falling edges. For example, in the case of FED, the luminance is determined by integrating current values flowing through each pixel. Accordingly, when the voltage waveform input to each pixel is distorted, a light emission characteristic is further added to the distortion, and the light emission characteristic is different from the design intention, that is, lower than the design value. In the case of LCD, it affects the ON time of pixel drive TFT (Thin Film Transistor). In the case of a PDP, as a result of affecting the pulse amplitude of the subfield drive, the luminance is affected. Thus, the distortion component of the drive waveform causes a reduction in luminance. In addition, when the distortion varies from pixel to pixel, there may be disturbances related to shading and uniformity according to the distance from the drive circuit.

  In a conventional driving circuit, in driving with an XY matrix, each pixel to be subjected to pulse amplitude modulation driving selects a row with a signal of 1 clock step processing in the row direction, and signals to the pixel with a signal of 1 clock step processing in the column direction. Is entered. In the case of driving with a pulse width modulation driving circuit, processing of 1 clock is assigned to driving 1 LSB (Least Significant Bit) which is the minimum unit to be driven.

  Such a conventional driving method always gives a DC signal that fluctuates on the time axis when one pixel is considered. Therefore, in this conventional driving method, in order to correct the luminance decrease due to the distortion of the driving waveform, when viewed from the pixel, the correction of the direct current component, that is, the output signal is not corrected, the level of the input signal is changed, As a result of integration, there was only a method for correcting the luminance.

  In this method, in order to vary the input signal level, it is necessary to amplify the level at the drive circuit input stage. In order to realize this, the signal is amplified by signal processing. In the case of amplitude modulation, since the drive circuit output is a fixed bit, the resolution in the level direction, that is, the bit is sacrificed. In the case of pulse width modulation, in order to increase the amplitude, an increase in power consumption or panel There were side effects such as improved pressure resistance performance. It is a problem to achieve the luminance as designed without causing these side effects, and to correct the variation in pixels. In addition, in the case of amplitude modulation, pixel data may affect one line below due to a load, and there is a problem that the contrast in the vertical direction is deteriorated.

  In the present invention, in consideration of the above-described problems, attention is paid to the fact that the minimum driving for each pixel is one clock step processing, that is, direct current. In contrast, the present invention provides a driving circuit and a display device that can add not only direct current but also alternating current components.

  According to the present invention, it is possible to perform luminance correction without sacrificing the resolution in the level direction. In the case of amplitude modulation, it is possible to improve the deterioration of contrast in the vertical direction caused by distortion due to a load.

  In order to solve the above-described problem, the invention according to claim 1 is a drive circuit for driving a matrix display device in which a plurality of pixels are formed in a matrix, and a plurality of processes of output data of at least one of columns and rows are performed. It is a drive circuit that can be processed in the clock step. According to a fourth aspect of the present invention, there is provided a display device including a driving circuit configured to process output data of at least one of a column and a row in a plurality of clock steps.

  According to a second aspect of the present invention, in a driving circuit for driving a matrix type display device in which a plurality of pixels are formed in a matrix, output data processing of at least one of a column and a row is an integral multiple of a minimum unit clock for driving the pixel. It is a drive circuit which processes with the frequency of. According to a fifth aspect of the present invention, there is provided a display device comprising a driving circuit configured to process output data processing of at least one of a column and a row at a frequency that is an integral multiple of a minimum unit clock for driving a pixel.

  According to a third aspect of the present invention, in a drive circuit for driving a matrix type display device in which a plurality of pixels are formed in a matrix, a DC component and an AC component correction signal can be added to at least one of the output data in columns and rows. It is a drive circuit. A sixth aspect of the present invention is a display device including a drive circuit configured to be able to add a DC component and an AC component correction signal to at least one of column and row output data.

  According to a seventh aspect of the present invention, there is provided a driving circuit for driving a matrix type display device in which a plurality of pixels are formed in a matrix. The driving circuit includes a distortion correcting circuit for correcting distortion of at least one of the driving waveforms in columns and rows. The circuit is a drive circuit configured to add correction values at a plurality of clock steps to data of one pixel from which a drive waveform is output or data of a minimum unit constituting the one pixel. According to a tenth aspect of the present invention, the drive circuit includes a distortion correction circuit that corrects distortion of at least one of the driving waveform of the column and the row, and the distortion correction circuit receives data of one pixel from which the driving waveform is output or the one pixel. This is a display device configured to add correction values to the minimum unit data to be configured at a plurality of clock steps.

  In the present invention, processing of at least one of the row and column drive signals can be performed in a clock step obtained by dividing one reference clock from which the drive signal is output into a plurality of clock steps. As a result, a correction value can be added to the drive signal at a clock step, and distortion correction can be performed without sacrificing the number of bits of drive data. The present invention can be applied not only to the amplitude direction but also to the case of generating a drive waveform by pulse width modulation.

  In the present invention, a method for generating a correction signal that can correct a variation in waveform distortion due to an output load in the drive circuit, from a method in which a drive circuit by amplitude modulation is driven at a single clock step to a method that is driven at a plurality of clock steps. Is provided. According to the present invention, the following effects can be obtained.

  First, the luminance of each pixel may have become lower than the design value due to output distortion of the driving circuit. However, in order to enable driving in a plurality of steps, the signal of one pixel is corrected. A signal can be added, and for this reason, each pixel can emit light with a luminance as designed. In other words, since the distortion component is corrected by the present invention, the luminance of each pixel is improved. Then, luminance unevenness can be improved by controlling the correction component of each pixel.

  Second, if the signal processing unit in the previous stage tries to correct, the resolution (number of bits) in the level direction is sacrificed. In the case of the present invention, the correction is made without sacrificing the resolution in the level direction. Is possible.

  Third, for example, when a differentiation circuit is used as the correction signal generation unit, a correction signal corresponding to the input level can be automatically generated.

  Fourth, when attention is paid to the distortion in the vertical direction, it is possible to remove the influence on the pixel below one line by the present invention, and it is possible to reduce or prevent the vertical contrast deterioration.

  Hereinafter, a first embodiment in which the present invention is applied to an FED (Field Emission Display) will be described with reference to the drawings. In the FED structure, a vacuum space is formed, and electrons are emitted by field emission from a cathode having a structure such as a microtip with a sharp tip or a carbon nanotube due to a voltage difference between the cathode and the gate electrode. , And collides with the phosphor on the way to emit light.

FIG. 1 shows the overall configuration of the first embodiment of the present invention. Reference numeral 1 denotes an input video signal to the display system, which is NTSC (National Television System).
An SD (Standard Definition) signal such as Committee) or an HD (High Definition) signal is input.

  The input video signal is subjected to processing such as digitization and decoder in the A / D / input data processing unit 2. Thereafter, the image format conversion unit 3 changes the format to an image size adapted to the display panel 9. For example, when the display panel 9 is an HD display panel and the input video signal is an SD signal, format conversion is performed by interpolation processing or the like. The memory 11 is used for the format change. A signal changed to a format suitable for the panel 9 is serially captured by a pixel clock in a time series signal / H unit signal conversion (serial / parallel conversion) unit (hereinafter simply referred to as a timing conversion unit) 4. A timing conversion process that is output in parallel in units of (horizontal period) is received.

  A signal for each pixel in one row converted into a parallel signal in the timing conversion unit 4 is supplied to the column driver 6 via the column (column direction) correction unit 14. The column correction unit 14 has a configuration to which the present invention is applied. The column driver 6 has a line memory. For example, 8-bit data is output from the line memory in a 1H cycle, output data is D / A converted, and a column drive signal converted to an analog signal is output from the column driver 6. A column driving signal is applied to the signal line of the display panel 9. The column driver 6 has a configuration in which correction circuits equal to the number of pixels in one line are provided in parallel, and a column drive signal corresponding to the number of pixels in one line of the display panel 9 is generated.

  Basic timing signals such as a synchronization signal and a clock are input from the image format conversion unit 3 to the timing generation unit 5, and basic timing signals of the column driver 6 and row (column direction) driver 7 necessary for panel driving are input. appear. A timing signal is supplied to the column correction unit 14 and the row correction unit 15. The row correction unit 15 is applied with the present invention, and corrects the row driving waveform. The corrected low drive signal is supplied to the low driver 7, and the low drive waveform is applied from the low driver 7 to the signal line of the display panel 9. The number of signal lines is equal to the number of horizontal scanning lines of the display panel 9. Each row is selectively driven sequentially by the row driver 7, and all the pixels in that row are driven by a drive signal latched in the column driver 6.

  Reference numeral 8 is a high pressure applied to the anode of the FED. Reference numeral 10 denotes a luminance meter, which is composed of, for example, an image sensor. All the pixels of the display panel 9 are driven with the same level of data, and the luminance value of each pixel is detected by taking an image of the display panel 9 with the luminance meter 10. Then, in the initialization unit 13 constituted by a personal computer or the like, the difference between the luminance value of the design value and the actually detected luminance value is detected, and correction data that eliminates the difference, that is, the display panel 9 Correction data for eliminating the non-uniform brightness of each pixel is calculated, and the correction data is written in the correction storage memory 12.

  Processing for obtaining such correction data is performed at the time of factory shipment. Therefore, when performing a normal display operation, the luminance meter 10 and the initialization unit 13 are unnecessary, and the display device used by the user does not need to include these, and includes an interface for writing correction data in the memory 12. It should be. Further, the memory 12 is constituted by a nonvolatile memory in order to retain the correction data even when the power is turned off.

  The correction data stored in the memory 12 is input to the column correction unit 14 and the row correction unit 15 in accordance with the timing of the display format, and is converted into correction data in the column and row directions. The column correction unit 14 is provided with correction circuits equal to the number of pixels in one line in parallel, and corrects output waveform distortion for each pixel and generates a correction signal that achieves luminance as designed. . The column correction unit 14 performs pixel-by-pixel correction for each of a plurality of pixels in one line and line-by-line correction for each of a plurality of pixels equal to the number of effective lines in each column. Therefore, the column correction unit 14 causes a load variation according to the vertical distance from the column driver 6 to the pixel, variation in the drive circuit for each pixel, variation in wiring capacitance / resistance between each drive circuit and the pixel on the same line, In addition, it is possible to correct the luminance variation caused by the load variation according to the distance between the low driver 7 and the pixel.

  Further, the row correction unit 15 generates a correction signal that corrects the output waveform distortion for each row (line) so that the row can be selected as designed. That is, a correction signal is generated so as to correct the luminance variation due to the wiring resistance and the wiring capacitance in line units. However, the row correction unit 15 cannot correct a change in luminance due to a change in wiring resistance and wiring capacitance depending on the distance between the row driver 7 and the pixel. The column driver 6 and the row driver 7 drive each pixel and each row based on the corrected row direction drive signal and column direction drive signal. Although the column driver 6 and the row driver 7 are provided in the first embodiment, it is effective to provide only one of them.

  Each column and row driving circuit outputs a signal with such a correction value and drives each pixel. As a result, each pixel has data with a different correction value added to each pixel and a driving signal in the column direction. Is applied. The light emission luminance of each pixel can realize a brighter light emission characteristic in which the waveform deterioration due to the wiring resistance component and the capacitance component is corrected by the drive voltage to which the correction value is added, as compared with before the correction.

  FIG. 2 shows, for reference, waveforms of respective parts according to a conventional driving method for one row. FIG. 2A shows the row direction clock CLK1 supplied to the row driver. The clock CLK1 has a horizontal period H. In the case of a matrix display device, one line of data is once latched in the column driver, and one line of data is supplied to the line selected by the row driver, so that a signal of a desired level can be turned on. . Therefore, the clock CLK1 is usually one horizontal cycle unit.

  FIG. 2B shows the row direction data without distortion that occurs when there is no load. One line with high data is driven. FIG. 2C shows a row direction driving waveform when the display panel is connected. For example, in the case of a system having a sampling frequency of 13.5 MHz, the low driver 7 is connected with a load of 720 pixels × 3 (RGB). The waveform is distorted. Therefore, in the case where there is no correction, as shown in FIG. 2C, the drive waveform is a rounded row direction drive waveform by one step in the row direction CLK1. When receiving such distortion, a difference occurs in the driving conditions for each row to be driven, and as a result, the luminance of each row does not become uniform in the vertical direction. Also, when viewed in the horizontal direction (low direction), the line resistance and capacitance of each pixel differ from the drive circuit, so even if the drive from the column direction is ideally uniform, the luminance of each pixel in the horizontal direction is It will not be uniform. Thus, conventionally, each pixel is driven by a direct current value by one clock step process.

  FIG. 3 shows the waveform of each part according to the driving method of the first embodiment for one row. As shown in FIG. 3A, the row direction clock CLK2 supplied to the row correction unit 15 has a frequency N times, for example, 4 times the horizontal frequency. FIG. 3B shows the data in the row direction without correction (no load) as in FIG. 2B.

  FIG. 3C shows the row direction data corrected by the row correction unit 15. As shown by the dotted line, the row direction data has a higher level on the side closer to the front edge than the uncorrected data, and more after the rear edge than the uncorrected data. The level is low. That is, in the example of FIG. 3C, the first level is set to be higher than the level indicated by the dotted line in the period immediately after the front edge, and is substantially lower than the first level and higher than the level indicated by the dotted line after the H / 4 interval. The second level is set, and the third level indicated by a dotted line in the subsequent H / 2 section. The fourth level is lower than the level indicated by the dotted line in the period immediately after the rear edge, and is set to the fifth level that is higher than the fourth level and lower than the level indicated by the dotted line after approximately H / 4. This is the sixth level indicated by the dotted line in the section.

  The row correction unit 15 uses the clock CLK2 having a quadruple frequency to generate the above-described corrected row direction data by digital signal processing, for example, the configuration of a digital differentiation circuit. Further, based on the correction data stored in the memory 12, the correction amount (level increase amount or decrease amount) of the row direction data is adjusted for each line. The drive waveform in the row direction generated from the correction data in the row direction is as shown in FIG. 3D. As can be seen by comparing the drive waveforms in FIGS. 2C and 3D, in the first embodiment, the rounding of the row direction drive waveform can be corrected, and the leading edge and the trailing edge can be made steep. Thus, in the first embodiment, each line can be driven by a plurality of clock step processes. Therefore, it becomes possible to add a correction signal from a direct current to an alternating current signal to one line of drive signals. That is, although it is possible to correct the luminance non-uniformity in the vertical direction of each pixel, the above-described horizontal luminance non-uniformity cannot be corrected by the low correction unit.

  The correction of the distortion of the driving waveform is aimed at achieving the luminance as designed, and therefore the goal is to drive the signal of the level input to the driving unit accurately in each pixel. Therefore, for example, when an AC component is added to correct the output distortion, the resolution in the level direction is not sacrificed, and each line can be driven as designed. Since the correction amount is adjusted based on the correction data stored in the memory 12, it is possible to correct a difference in light emission characteristics in units of lines and drive each line as designed.

  Next, driving in the column direction by the column driver 6 will be described. FIG. 4 shows the waveforms of the respective parts according to the conventional driving method for reference. FIG. 4A shows a data clock which is a column direction clock supplied to the column driver. In the case of a matrix display device, one line of data is once latched in the column driver, and one line of data is supplied to the line selected by the row driver, so that a signal of a desired level can be turned on. . The data clock is in units of pixels, and FIG. 4B shows data synchronized with the clock, for example, (D0, D1,..., D719) in the case of 1 line 720 samples.

  The data for each pixel is latched once by the horizontal cycle timing signal shown in FIG. 4C in the column drive circuit (timing conversion unit, column driver), and converted into a signal of one horizontal cycle unit as shown in FIG. 4D. Are output in parallel from the column driver. In FIG. 4D, only D0 and D1 of D0 to D719 are shown for simplicity. Therefore, for example, in the case of an image with 480 effective lines, 480 loads are connected to one drive circuit.

  For example, in the case of an image with 480 effective lines, 480 loads are connected to the driver in the column direction. Depending on the load capacity and wiring resistance, the driver's presence or absence or the load weight The output waveform is distorted as shown in FIG. 4E. FIG. 4E shows a drive waveform when one of the signals output from the column driver, for example, data D0 is output. When receiving such distortion, a difference occurs in the driving condition for each pixel to be driven, and as a result, the luminance of each pixel does not become uniform in the horizontal direction. Further, since the wiring resistance and wiring capacitance of each pixel as viewed from the driver are different, the luminance (luminance in the vertical direction) also becomes non-uniform according to the distance from the driver.

  FIG. 5 shows the waveforms of the respective parts according to the driving method in the column direction in the first embodiment of the present invention. 5A and 5B show data clocks and data similar to those shown in FIGS. 4A and 4B, respectively. Further, it is latched in the timing converter 4 by a latch pulse of one horizontal period (1H) shown in FIG. 5C, and a latched signal as shown in FIG. 5E is obtained. The column correction unit 14 corrects each latched data. As shown in FIG. 5D, the drive waveform is corrected as shown in FIG. 5F by a clock having a frequency M times, for example, 8 times the horizontal frequency.

  Similar to the row direction data described with reference to FIG. 3D, this correction adds a positive correction amount to the front rising edge and adds a negative correction amount to the rear falling edge. is there. As a result, as shown in FIG. 5G, the drive waveform in the row direction is corrected to a steep waveform rather than a distorted waveform. The correction amount for each pixel is based on the correction data stored in the memory 12. In order to perform appropriate correction on each of the 720 samples in one line, and to perform appropriate correction on the 480 pixels in each column, the column correction unit 14 includes a correction circuit equal to the number of pixels in one line in parallel. These data are updated to appropriate values for each line. 5F and 5G show driving waveforms when one of the signals output from the column driver 6, for example, data D0 is output.

  In the above-described correction examples in the row direction and the column direction, the primary differential waveform is basically used as the correction signal, but it can be changed to another waveform in accordance with the light emission characteristics of each pixel. Further, depending on the pixel characteristics, correction can be performed only on one of the plus side and the minus side.

  Next, an example of the low correction unit 16 will be described with reference to FIGS. 6 and 7. However, the column correction unit 14 can have the same configuration as the row correction unit 16 described below. FIG. 7A of the timing chart shows a quadruple row direction clock CLK2. FIG. 7B shows the input row direction data DT0. Input data DT0 is supplied to the series connection of delay elements 20 and 21. The delay element operates with the clock CLK2 and gives a delay of one period to the data.

  7C shows the output data DT1 of the delay element 20, and FIG. 7D shows the output data DT2 of the delay element 21. Data DT0 is subtracted from data DT0 in the synthesizer 22 to generate data DT3 shown in FIG. 7E. Further, the DT2 is subtracted from the data DT1 in the synthesizer 25, and the data DT4 shown in FIG. 7F is generated. Data DT3 is supplied to the synthesizer 23 via the gain control unit 24, and data DT4 is supplied to the synthesizer 23 via the gain control unit 28. The combiner 23 is supplied with input data DT0. The synthesizer 23 adds the output data of the gain control units 24 and 28 to the input data DT0. Output data DT5 (FIG. 7G) is output from the synthesizer.

  The gain of the gain control unit 24 is set to G1 by the control signal from the gain control signal generation unit 26. The gain of the gain control unit 28 is set to G2 by the control signal from the gain control signal generation unit 27. The gain control signal generators 26 and 27 are supplied with correction data from the correction value storage memory 12 and generate a control signal for setting an appropriate gain based on the correction data.

  As described above, at the time of factory shipment or the like, an image of the display panel 9 is captured by the luminance meter 10, non-uniformity of each pixel is detected, and correction data for correcting the non-uniformity is obtained by the initialization unit 13, Correction data is stored in the memory 12 for each line and each pixel. The memory 12 is supplied with an address that designates a line that is the object of current processing. Therefore, when a predetermined row is driven by data including the correction value shown in FIG. 7G, variation in luminance due to variation in wiring capacitance and wiring resistance of each line can be corrected. The output data shown in FIG. 7G has a word length of about 4 bits, for example. The row driver 7 drives the row direction as an analog signal by D / A conversion.

  The column correction unit 14 can have the same configuration as that shown in FIG. 6 except that the clock frequency is different and the data word length is longer (for example, 8 to 9 bits).

  The above-described first embodiment of the present invention can be realized not only by hardware but also by hardware and software. FIG. 8 and FIG. 9 are flowcharts for explaining the operation of the hardware configuration. However, when the present invention is realized by software processing, it represents the flow of software processing. First, the processing flow of the first embodiment will be described with reference to FIG.

  In step S1, image data is input to the system. In step S2, the image data is digitized by an A / D converter. In step S3, the format of the image signal is converted in accordance with the resolution of the display panel 9. The timing of the column direction drive circuit (column driver 6) is generated in accordance with the horizontal sync signal after the format conversion (step S4). Further, the timing of the row direction driving circuit (row driver 7) is generated in accordance with the vertical synchronization signal after the format conversion (step S5).

  In step S6, the column direction data is captured with a clock having a frequency M times the horizontal frequency. In step S7, the row direction data is captured with a clock having a horizontal frequency N times. Next, in each of steps S14 and S15, it is determined whether the operation is an initialization operation or a normal operation. At the time of initialization, in step S8, the signal input to the column driver is converted into a signal in units of one horizontal period (1H) to drive each pixel. At the time of initialization, in step S9, the signal input to the row driver drives all the pixels of each line as they are.

  Although the displayed image has a decrease in brightness and non-uniformity due to wiring resistance, capacitance, etc., at the time of initialization, for example, a display image is captured by a camera, and the display unit uses the display image as a digital signal. (Step S10). In step S11, the initialization unit 13 calculates correction data for correcting the level non-uniformity due to the position on the panel from the fetched data. In step S <b> 12, the calculated correction data for each position is written in the memory 12. The initialization process ends (step S21).

  If it is determined in steps S14 and S15 that the operation is normal, processing in steps S16 and S17 is performed. In step S13, the correction data written in the memory 12 at the time of initialization is read out in synchronism with the timing of writing to the pixels in each column direction or driving and selecting each row. In step S16, the column direction correction data read in step S13 is added to the input data of the column correction unit 14 in units of pixels. In step S17, the row direction correction data read in step S13 is added to the input data of the row correction unit 15.

  In step S18, a signal to which correction data of each pixel is added in the column direction in step S16 is output from the column driver 6, and each pixel is driven so as to correct deterioration due to the cause of the display panel 9. In step S19, a signal to which correction data for each row is added in the row direction in step S17 is output from the row driver 7, and each row is driven so as to correct deterioration caused by the panel. In step S20, panel driving with corrected driving distortion is performed. That is, by the above-described processing, a signal in which the influence of the wiring resistance, capacitance, etc. is corrected is displayed on the panel, the luminance is improved and the non-uniformity is improved as compared with the case without correction.

  With reference to FIG. 9, the process in the case of automatically calculating correction data will be described. As in the flowchart of FIG. 8, image data is input to the system (step S1). In step S2, the image data is digitized by an A / D converter. In step S3, the image data is matched with the resolution of the display panel 9. The format of the received image signal is converted. The timing of the column driver 6 is generated according to the horizontal synchronization signal after the format conversion (step S4), and the timing of the row driver 7 is generated according to the vertical synchronization signal after the format conversion (step S5).

  In step S6, the column direction data is captured with a clock having a frequency M times the horizontal frequency. At the same time, a correction value in the level direction is automatically calculated in step S6. In step S7, the row direction data is captured with a clock having a horizontal frequency N times. At the same time, a correction value in the level direction is automatically calculated in step S6. In the case of a differential waveform, the correction value depends on the level of the data. When the data is large, the correction amount is large, and when the data is small, the correction amount is small. At this time, since the amount of distortion corresponding to the distance from the row and column drive circuits can be predicted in advance as the panel characteristics, it is possible to generate a correction value in consideration of this amount of distortion by adding a few circuits. The point that this correction value is automatically calculated is different from the process of the flowchart shown in FIG. Other processes are the same as those in the flowchart of FIG.

  At the time of initialization, the driving process of each pixel in step S8, the driving process of all pixels in each line in step S9, the display image capture in step S10, the correction data calculation in step S11, and the calculated calculations in step S12 are performed. The position correction data is written into the memory 12. The correction signal generated in steps S6 and S7 realizes a fixed correction for the drive waveform distortion. However, the variation for each pixel remains. The luminance nonuniformity for each pixel is corrected from the data obtained by the initialization process. When the correction data is written to the memory 12, the initialization process is completed (step S21).

  In normal operation, correction data is read from the memory 12 (step S13), the column direction correction data read in step S16 is added to the input data of the column correction unit 14 in units of pixels, and the input of the row correction unit 15 is performed. The row direction correction data read in step S13 is added to the data (step S17). A signal to which correction data for each pixel is added is output from the column driver 6 to drive each pixel (step S18), and a signal to which correction data for each row is added is output from the row driver 7 to drive each row. (Step S19). By such processing, a signal in which influences such as wiring resistance and capacitance are corrected is displayed on the panel, and the luminance is improved and non-uniformity is improved as compared with the case without correction.

  Next explained is the second embodiment of the invention. In the first embodiment described above, the drive signal is amplitude-modulated at a plurality of clock steps in the level direction. In the second embodiment, for example, the drive characteristics of an FED are improved by applying the present invention to pulse width modulation.

  FIG. 10 shows an example of a column direction driving circuit when the pulse width to be modulated is 1 LSB (Least Significant Bit). FIG. 10A shows a horizontal synchronization pulse of a video signal of one horizontal period (1H). In amplitude modulation, data is latched in units of 1H. In the case of pulse width modulation, a pulse according to a modulation amount to be driven is used. A width signal is output. For example, in the case of modulation with 8 bits (256 gradations), a signal having a pulse width obtained by dividing a 1H section into 256 equals corresponds to a modulation signal of 1 LSB.

  In the second embodiment, signal processing is performed with a clock (FIG. 10D) having a cycle that is 1/4 times the pulse width of 1/256 of 1H, that is, 1/1024 of 1H. Using this clock, as shown in FIG. 10C, a correction waveform that is amplitude-modulated in units of a pulse width that is 1/4 of the pulse width shown in FIG. 10B is generated. The correction waveform is generated in the same manner as in the first embodiment described above. By driving the display panel with this correction waveform, it is possible to eliminate the influence of the panel load.

  A correction method when the pulse width is 1LSB or more will be described with reference to FIG. FIG. 11A shows a horizontal synchronization pulse of a video signal having one horizontal period (1H). FIG. 11D shows a pulse width modulation clock with a period t of 1/256 of 1H, and FIG. 11F shows a clock with a period of 1/1024 of 1H. Now, as shown in FIG. 11B, an attempt is made to drive a pixel with a signal having a pulse width of 1H × (N / 256). The drive pulse has already been subjected to pulse width modulation by the clock shown in FIG. 11D. T in FIG. 11C corresponds to a pulse width of 1 LSB.

  In the second embodiment of the present invention, the distortion in the drive waveform can be corrected by changing the level in units of 1 LSB to obtain the waveform shown in FIG. 11C. Furthermore, for example, by setting the processing clock to a clock having a frequency four times that of the pulse width modulation clock (FIG. 11F), it is possible to apply amplitude modulation in steps obtained by further dividing the 1LSB into four (FIG. 11E). ). As described above, according to the second embodiment, it is possible to correct the load distortion of the driving signal not only for the amplitude modulation but also for the pulse width modulation.

  Next explained is the third embodiment of the invention. When driving a matrix type display device, the data of the current line may affect the data of the next line depending on the time constant of the panel, and the vertical contrast may deteriorate. The third embodiment solves this problem.

  As shown in FIG. 12, an image in which the mth pixel in the horizontal direction is white in the nth line of the display panel, and the mth pixel in the horizontal direction is black in the (n + 1) th line. Think of a pattern.

  FIG. 13 is a timing chart for explaining processing when correction is not performed, and FIG. 13A shows a drive clock CLK3 in the column direction. In the case of a display panel including, for example, an FED type display element as shown in FIG. 1, 1H data is latched once in the column direction column driver 6 and output at the same timing for the column selected in the row direction. As a result, a signal of a desired level can be lit on the selected line. Therefore, the period of the clock CLK3 is normally 1H.

  However, 600 lines for SVGA and 1080 lines for HD are connected to the driver in the column direction, and the output waveform of the driver is distorted by the presence or absence of a load due to their load capacitance and wiring resistance. FIG. 13B shows an output waveform from the column direction drive circuit (column driver 6) when there is no load, and FIG. 13C shows an output waveform when a load is connected. Due to the load, the distortion of the signal of the nth line (portion B in FIG. 13C) extends to the area of the (n + 1) th line.

  FIG. 13E shows a row selection signal for selecting the n-th line, and the n-th line emits light at a portion A where this timing coincides with the timing of the drive waveform in FIG. 13C. In addition, the (n + 1) th line emits light at a portion B where the timing of the row selection signal for selecting the (n + 1) th line shown in FIG. 13F coincides with the timing of the drive waveform in FIG. 13C. FIG. 13D shows the average light emission luminance of the pixels of each line. As a result of the above-described distortion, the n-th line has a signal as indicated by MA in FIG. 13D, and the n + 1-th line has A signal exists as shown by MB in FIG. 13D. Therefore, as shown in FIG. 14, the line that should be displayed as black originally has a certain luminance, and the vertical contrast is deteriorated.

  In the third embodiment of the present invention, as shown in FIG. 15A, the drive waveform shown in FIG. 15B is corrected by a clock CLK4 having a frequency four times the horizontal frequency, for example, and as shown in FIG. 15C, In the (n + 1) th line, column direction data having a level lower than the normal level is generated. As a result of this correction, the actual drive waveform has a steep fall as shown in FIG. 15D, and the drive signal is prevented from extending to the next line. As a result, the waveform distortion due to the time constant affects the next line, and the problem that the vertical contrast is lowered is prevented and reduced.

  When the display panel is driven with the corrected driving waveform, the average light emission luminance in the nth line and the (n + 1) th line is as shown in FIG. 15E, and the light emission in the (n + 1) th line can be suppressed. In this way, deterioration in vertical contrast can be suppressed.

  In the above description, it is assumed that the column direction driving circuit causes waveform distortion due to the column direction load and the row direction driving circuit has no waveform distortion. However, in the opposite case, that is, the row direction driving circuit has a time constant. Even if the waveform distortion is caused by this and the column direction drive circuit is not distorted, the vertical contrast may be deteriorated in the same manner. Therefore, when there are waveform distortions due to time constants in the drive circuits in the row direction and the column direction, and each of them affects the vertical direction contrast degradation, the correction device according to the third embodiment is applied to each of the column and row direction drive units. It is necessary to provide in.

  Further, when the distortion of the drive waveform varies from place to place, the distortion amount varies depending on the place by storing the correction amount in the memory of the system in the same manner as the method in the first embodiment described above. Can be dealt with.

  The present invention is not limited to the above-described first embodiment and the like, and various modifications and applications can be made without departing from the gist of the present invention. For example, in the above description, the correction value is generated for each pixel of the display panel, but the correction value may be generated for each area or line composed of a plurality of pixels. Further, when a plurality of clock steps are formed, it is not always necessary to have an integer multiple frequency relationship. Furthermore, the present invention may be applied to other matrix type display devices such as LCDs and PDPs as well as FEDs.

1 is a block diagram showing an overall configuration of an image display apparatus to which the present invention can be applied. It is each part waveform diagram for demonstrating the row direction drive when not correct | amending. It is each part waveform diagram for demonstrating the row direction drive in the case of performing correction | amendment by 1st Embodiment of this invention. It is each part waveform diagram for demonstrating the column direction drive when not correct | amending. It is each part waveform diagram for demonstrating the column direction drive in the case of correct | amending by 1st Embodiment of this invention. It is a block diagram which shows the structure of an example of a low correction | amendment part. It is a timing chart used for operation | movement description of an example of a low correction | amendment part. It is a flowchart which shows the flow of a process in case the automatic calculation of a correction signal is not performed in 1st Embodiment of this invention. It is a flowchart which shows the flow of a process in the case of performing the automatic calculation of the correction signal in 1st Embodiment of this invention. It is a timing chart used for description of an example of the correction process of 2nd Embodiment which applied this invention to the drive system by pulse width modulation. It is a timing chart used for explanation of other examples of amendment processing of a 2nd embodiment of this invention. It is a basic diagram used for description of 3rd Embodiment which applied this invention for prevention of the deterioration of the contrast of a perpendicular direction. It is a timing chart used for description of deterioration of contrast in a vertical direction that occurs when correction is not performed. It is a basic diagram which shows deterioration of the contrast of the perpendicular direction which arises when not correct | amending. It is a timing chart used for description of 3rd Embodiment of this invention.

Explanation of symbols

3 ... Image format conversion unit, 4 ... Time series signal / H unit signal conversion (serial / parallel conversion) unit for column drive circuit, 5 ... Timing generation unit for drive circuit, 6 ... Column ( Column driver for column) direction drive, 7... Row driver for row (row) direction drive, 9... Display panel, 10... Luminance meter, 12. ... Initialization unit, 20, 21 ... Delay element, 24, 28 ... Gain control unit

Claims (10)

In a drive circuit for driving a matrix display device in which a plurality of pixels are formed in a matrix,
A drive circuit capable of processing output data of at least one of a column and a row in a plurality of clock steps. In a drive circuit for driving a matrix display device in which a plurality of pixels are formed in a matrix,
A drive circuit for processing output data processing of at least one of a column and a row at a frequency that is an integral multiple of a minimum unit clock for driving a pixel. In a drive circuit for driving a matrix display device in which a plurality of pixels are formed in a matrix,
A drive circuit capable of adding a DC component and an AC component correction signal to output data of at least one of a column and a row. In a matrix display device in which a plurality of pixels are formed in a matrix,
A display device in which a drive circuit is configured to process output data of at least one of a column and a row in a plurality of clock steps. In a matrix display device in which a plurality of pixels are formed in a matrix,
A display device in which a drive circuit is configured to process output data processing of at least one of a column and a row at a frequency that is an integral multiple of a minimum unit clock for driving a pixel. In a matrix display device in which a plurality of pixels are formed in a matrix,
A display device in which a driving circuit can add a correction signal for a DC component and an AC component to output data of at least one of a column and a row. In a drive circuit for driving a matrix display device in which a plurality of pixels are formed in a matrix,
A distortion correction circuit for correcting distortion of at least one of the driving waveform of the column and row;
The distortion correction circuit is a drive circuit configured to add correction values at a plurality of clock steps to data of one pixel from which the drive waveform is output or data of a minimum unit constituting the one pixel. In claim 7,
The distortion correction circuit includes a storage unit that stores correction data, and is a drive circuit capable of controlling a correction amount for each pixel, each line, or each area. In claim 7,
The distortion correction circuit has a function of automatically calculating a correction amount from the value of the drive signal. In a matrix display device in which a plurality of pixels are formed in a matrix,
The drive circuit includes a distortion correction circuit that corrects distortion of at least one of the drive waveforms in the columns and rows,
The display device in which the distortion correction circuit is configured to add correction values to a plurality of clock steps of data of one pixel from which the drive waveform is output or data of a minimum unit constituting the one pixel.

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