JPH11194322A - Driving device for plasma address liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set the writing efficiency of liquid crystal driving voltage of a non-inversion side and an inversion side to be maximum and symmetrical by generating a plasma discharge pulse which can independently adjust/set the phase in accordance with the polarity of video signal voltage driving a first scanning electrode group and driving a second scanning electrode group with the plasma discharge pulse. SOLUTION: An LCD controller 29 generates a count clock for driving a lamp waveform generation part 30, pulse for driving an anode inversion driving circuit 31 and a pulse for driving the plasma driver 32 and discharging a plasma at every scanning groove based on an operation clock generated based on a synchronizing signal from an NTSC demodulation part 21. The count clock from the LCD controller 29 is supplied to the lamp waveform generation part 30, a lamp waveform obtained here is supplied to a liquid crystal column driver 27 and it drives the transparent column electrode of a plasma address liquid crystal display device (PALC) 37.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a plasma addressed liquid crystal display device using a plasma addressed liquid crystal display element for forming an image by an active matrix system.

[0002]

2. Description of the Related Art In recent years, in order to obtain more powerful images in consideration of, for example, an installation space that can be secured in a home, a large and thin television receiver, a rear projection type Projector devices have become widespread.

[0003] These television receivers and rear projection type projector devices have been realized to be considerably thinner as compared with those of the past in accordance with technological progress. In the case of television receivers, for example, CRT (Cathode Ray) Due to the depth of the tube, and in the case of a projector device, there is a natural limit to the reduction in thickness due to structural conditions such as the angle at which the projection lens is installed.

Further, a TFT (Thin Film Transistor)
A display device using a liquid crystal panel can be configured to be thinner than the above-described television receiver and projector device. However, in order to obtain a large-sized display device, an increase in the number of TFTs formed by IC technology requires higher precision. Along with the demand for manufacturing technology, the production yield is very low and the cost is very high.

[0005] Therefore, a plasma-addressed liquid crystal element (hereinafter, referred to as a "plasma-addressed liquid crystal"), which forms a large screen equivalent to that of a television receiver or a projector, and has a thickness comparable to that of a TFT liquid crystal panel.
A display device using the acronym PALC) for a display unit has been proposed.

This plasma-addressed liquid crystal element has a TF
High brightness and high contrast comparable to a T liquid crystal panel can be realized, and a large screen can be realized by a PDP (Plasma Display Panel) manufacturing technique.

Next, the structure of a PALC used in an embodiment of the present invention described later will be described with reference to FIGS. FIG. 2 is an exploded perspective view of a liquid crystal display device using PALC. FIG. 3 is a perspective view showing a part of the structure of the PALC, and a part is shown in a sectional view. As shown in FIG. 2, the PALC 1 has a structure as a transmissive display element for forming an image by selectively transmitting a light beam radiated from a backlight 2 disposed on the back thereof by an active matrix method. .

As shown in FIG. 3, a plasma substrate (back glass) 5 is provided with partition walls (ribs) 6, 6, 6,.
For example, scanning grooves (scanning grooves formed by cutting are also possible) at regular intervals, which are horizontally partitioned into hollows.
.. Are formed. In these scanning grooves 7, the anode electrodes 8,
, And the cathode electrodes 9, 9, 9,... Are formed at regular intervals so as to form a pair. That is, this scanning groove 7 constitutes a horizontal scanning line corresponding to the effective screen of PALC1, and the number of scanning lines (for example, about 480)
Book) is formed.

By arranging the thin glass substrate 10 on which an insulating layer is formed in front of the partition walls 6, 6, 6, the scanning grooves 7, 7, 7,... Can be sealed, and the inside of the scanning grooves 7, 7, 7,. For example, a rare gas such as helium gas or a mixed gas of rare gases is filled.

The cathode electrode 9 is supplied, for example, with a voltage of about -300 V from a driver circuit for plasma discharge (not shown).
Is applied at a predetermined timing (however, a ground potential is applied to the anode electrode 8), and a plasma discharge is generated between the anode electrode 8 and the cathode electrode 9 as described later in detail. I'm trying to wake them up.

By the plasma discharge, the plasma gas is ionized in the scanning groove 7 and an electric conductor (plasma channel) is formed until the plasma particles are completely extinguished. (Strobe).

In front of the thin glass (insulating layer) 10, a liquid crystal layer (liquid crystal display element) for forming pixels in a matrix is provided.
11, a color filter (layer) 12 composed of red, green, and blue filter portions 12 </ b> R, 12 </ b> G, and 12 </ b> B corresponding to each color of red, green, and blue, and red and green stripes for driving pixels of the liquid layer 11. , Blue drive electrodes 13R, 13G, 1
3B transparent electrode (transparent drive electrode) (layer) (for example, ITO (Indium TinOxide: indium tin oxide))
Are arranged at regular intervals so as to be orthogonal to the scanning grooves 7, 7, 7,..., And each orthogonal portion thereof is configured to be each pixel.

That is, the transparent drive electrode 13 of the PALC 1
By supplying video signals (data) for one horizontal line to R, 13G, and 13B, and sequentially selecting (strobe) and discharging the plasma gas in the scanning groove 7 in the vertical direction, the transparent driving electrodes 13R, 13G, and 13B are discharged. A video signal is applied to the liquid crystal of the pixel where 13G, 13B and the scanning groove 7 intersect,
Since the transmittance of the light emitted from the backlight 2 differs for each pixel, a color image can be displayed.

That is, as shown in FIG.
By arranging the polarizing filters 3 and 4 on the entrance side and the exit side of the ALC 1, respectively, the transmission amount of the light polarized by the PALC 1 can be controlled, and a color image can be formed by the same principle as a normal TFT liquid crystal display element. Will be able to gain.

Next, a switching operation for forming an image for one field will be described in more detail with reference to FIGS. FIG. 4 is a diagram schematically showing a part of the PALC 1 shown in FIG. 3 from a side. In order to explain the switching operation by the plasma channel, FIG.
2 shows a switch SW for convenience.

As described above, when a plasma generation pulse of, for example, -300 V is applied to the cathode electrode 9 (a ground potential is applied to the anode electrode 8) to cause a plasma discharge, a plasma channel is formed in the scanning groove 7. But
This plasma channel becomes a virtual electrode and the transparent electrode layer 1
3 (red, green and blue drive electrodes 13R, 13G, 13B) and the anode electrode 8 apply a video signal voltage. That is, the illustrated switch SW is turned ON.

FIG. 4 shows that when a voltage of -300 V is applied to the plasma channel by the switch SW, plasma gas is generated in the scanning groove 7 of the first line, and the strobe is generated.
(1) shows a state where is turned on. This shows a state in which no plasma gas has yet been generated in the scanning groove 7 of the second line, and the strobe (2) remains off. As shown in FIG. 4, when a plasma channel is formed by the plasma discharge, the inside of the scanning groove 7 becomes conductive, which is equivalently equivalent to F, as shown in FIG. 5B.
It can be described as an operation of an ET (Field-effect Transistor) switching element.

By the switching operation by the plasma channel, a virtual electrode is generated on the inner surface of the thin glass (substrate) 10 shown in FIG.
By applying a video signal voltage for driving pixels to G and 13B, the scanning groove 7 and the driving electrodes 13R,
A drive voltage is applied to each pixel (for one line) of the liquid crystal layer 11 at the intersection of 13G and 13B.

Therefore, the plasma discharge is sequentially applied to the scanning grooves 7.
By scanning so as to occur within (for example, the first line to the 480th line) and forming an image of one field, for example, an image of one field can be displayed.

That is, after selecting which line of an image is to be formed by the plasma channel, a driving voltage for forming an image of the line is applied to the red, green and blue driving electrodes 13R, 13G, 13B. 1 realizes selective scanning of lines constituting one field.
At this time, the light transmitted through the liquid crystal layer 11 is
By transmitting the red, green, and blue filter portions R, 12G, and 12B, a color image can be displayed. As a result, one line is synchronized with the driving of the pixels for one line.
By sequentially applying a drive voltage to the cathode electrodes from the line to the 480th line, an image for one field can be formed.

By forming a display device using a PALC capable of forming an image with such a structure and operation principle as a display element, a thin, lightweight and large-screen display device can be formed.

[0022]

The above-mentioned P
When displaying an image on the ALC, a driving circuit (column driver IC) for supplying a video signal to the transparent driving electrode 13
Since a withstand voltage of only about +60 V can be realized at present, a column driver using only a positive-direction power supply is used.
The negative inversion voltage for the C drive is a common anode in which all anode electrodes are used as a common (common) terminal, and the polarity is further inverted by a rectangular wave having substantially the same voltage for driving. An inversion driving method is employed.

At this time, P based on the anode voltage is considered.
Since the drive voltage for the ALC has an asymmetrical waveform on the positive side and the negative side, if the phase of the plasma discharge pulse with respect to the positive side and the negative side drive voltage is the same, the drive voltage waveforms on the positive side and the negative side are different. Optimal and efficient driving corresponding to the difference cannot be performed. Depending on the type of the plasma discharge gas, the duration of the ionized gas in the conductive state after the plasma discharge, the so-called decay time, may be affected by the polarity of the driving voltage of the liquid crystal. No driving is performed.

Further, as a measure for preventing the burn-in of the liquid crystal when the power is turned off, the drive voltage is reduced to 0V as soon as possible (for example, a white level voltage in the case of a normally white liquid crystal panel). It is necessary to write the voltage to PALC for one field, but since the power supply for driving the liquid crystal has a capacitive element for smoothing, it is necessary to discharge this power supply voltage instantly and write the driving voltage of 0 V to PALC. It is difficult to use the power supply voltage for driving the liquid crystal, including the discharge time of the power supply voltage for driving the liquid crystal. Was required.

In view of the above, the present invention provides a first transparent scanning electrode group disposed on a first surface of a liquid crystal display element,
The liquid crystal display device is disposed so as to face the second surface,
In a plasma addressed liquid crystal display device including a second scan electrode group forming a plurality of plasma discharge channels formed in a direction orthogonal to the scan electrode group, the phase of the plasma discharge drive pulse is shifted to the positive side and the negative side. An object of the present invention is to propose a device which can be independently adjusted and set for each drive voltage, and which can make the writing efficiency of the liquid crystal drive voltage on the non-inversion side and the inversion side maximum and symmetric, respectively.

[0026]

According to the present invention, a transparent first scanning electrode group arranged on a first surface side of a plasma addressed liquid crystal display element and a second scanning electrode group arranged on the first face side of the plasma addressed liquid crystal display element are provided. A second scan electrode group comprising a pair of an anode electrode and a cathode electrode forming a plurality of plasma discharge channels arranged on the surface side and arranged so as to be orthogonally opposed to the first scan electrode group. Driving means for driving a first scan electrode group by a video signal voltage which is alternately inverted and non-inverted every horizontal cycle, and which drives the first scan electrode group. Generates a plasma discharge pulse whose phase can be independently adjusted and set according to the polarity of the video signal voltage so that the asymmetric component according to the polarity does not occur in the writing efficiency of the video signal voltage And plasma discharge pulse generating means that,
And second driving means for driving the second scanning electrode group by the plasma discharge pulse from the plasma discharge pulse generating means.

According to the present invention, the first driving means drives the first scanning electrode group by the video signal voltage which is alternately inverted and non-inverted every one horizontal cycle, and is driven by the plasma discharge pulse generating means. A plasma whose phase can be independently adjusted and set according to the polarity of the video signal voltage so that an asymmetric component corresponding to the polarity does not occur in the writing efficiency of the video signal voltage for driving the first scan electrode group. A discharge pulse is generated, and the second drive unit drives the second scan electrode group by the plasma discharge pulse from the plasma discharge pulse generation unit.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first aspect of the present invention is a transparent first scanning electrode group disposed on the first surface side of a plasma addressed liquid crystal display element, and a second scanning electrode group disposed on the first face side of the plasma addressed liquid crystal display element. And a second scan electrode group consisting of a pair of an anode electrode and a cathode electrode forming a plurality of plasma discharge channels arranged so as to be orthogonally opposed to the first scan electrode group. A first driving unit for driving a first scanning electrode group by a video signal voltage alternately inverted and non-inverted every horizontal cycle; and a first scanning electrode group. Generates a plasma discharge pulse whose phase can be independently adjusted and set according to the polarity of the video signal voltage so that an asymmetric component corresponding to the polarity is not generated in the writing efficiency of the video signal voltage to be driven. A plasma discharge pulse generating means, and has a second drive means for driving the second scan electrode group by the plasma discharge pulses than the plasma discharge pulse generating means.

According to a second aspect of the present invention, in the driving apparatus for a plasma addressed liquid crystal display device according to the first aspect of the present invention, the plasma discharge pulse generating means instantaneously delays the phase of the plasma discharge pulse when the power is turned off. In one driving means, the writing section of the video signal voltage is set to be a section in which the polarity of the video signal voltage changes, and a driving voltage of 0 V as an average value of the writing voltage of the video signal voltage is set to a plasma address type liquid crystal display element. To prevent a DC component from remaining in the plasma-addressed liquid crystal display element when the power is turned off.

[Specific Examples of Embodiments of the Invention] Specific examples of the embodiments of the present invention will be described below in detail with reference to the drawings. First, a specific circuit of a liquid crystal display device including a plasma addressed liquid crystal display element according to a specific example of the embodiment will be described in detail with reference to FIG. FIG. 1 is a circuit block diagram showing a part of an image system of a liquid crystal display device using a plasma addressed liquid crystal display element of this embodiment, in particular. The specific description of the plasma-addressed liquid crystal display element 37 of FIG. 1 and the liquid crystal display device using the same uses the description given in FIGS. 2 to 5 in the related art.

In FIG. 1, NTSC (National Telev.
ision System Committee) In the preceding stage of the demodulation unit 21, for example, U / V tuner of NTSC system, B
A broadcast receiving unit such as an S tuner and one or more input terminals for inputting a standard video signal reproduced by an external device such as a VTR are provided.

Then, the standard video signal selected by the broadcast receiving means and the external standard video signal input from one or a plurality of input means are selected in the display device, and the NTS
It is supplied to the C demodulation unit 21.

The NTSC demodulation unit 21 demodulates the standard video signal into a luminance signal and a color difference signal, and supplies the luminance signal and the color difference signal to the double speed conversion unit 22. The demodulation unit 2
1 extracts a synchronization signal from a luminance signal obtained by demodulation, supplies the synchronization signal to an LCD (Liquid Crystal Display) controller 29 described later, and generates an operation clock of each functional circuit described below in the LCD controller 29. Thus, various signal processings are synchronized.

A frame memory capable of storing one frame of video signal (luminance signal and color difference signal) is provided in the double speed conversion section 22, and motion components are detected using this frame memory. Then, in the still image area of the video signal written in this frame, the video signal of the field at that time and the one horizontal period before one field are continuously read twice at twice the speed of writing.

Further, in the moving image area of the video signal written in this frame, the video signal of one horizontal period of the field information at that time and the interpolation generated by the interpolation process of the video signal of one horizontal period above and below it. The video signal is read at double speed and converted to a 525H / 60 Hz non-interlaced signal.

The video signal that has been subjected to the double-speed processing is subjected to color adjustment, hue adjustment, and the like in the video signal processing unit 23, and then red, green, and blue primary color signals are generated by inverse matrix processing. Each primary color signal generated by the video signal processing unit 23 is converted into digital red, green and blue video data V8b by an A / D converter 24 having 8-bit quantization accuracy. Each of the primary color video data V8b is further converted by the error diffusion processing unit 25 into 7-bit red, green and blue video data V7b having equivalent precision equivalent to 8 bits.

The red, green and blue video data V7b from the error diffusion processing section 25 are supplied to the liquid crystal column driver 27 after being subjected to white balance processing by the white balance adjustment section 26.

The liquid crystal column driver 27 latches video data for one horizontal period (for example, 854 pixels), that is, video data V7b of 854 pixels × 3 channels (red, green, blue), that is, 2562 pixels, and outputs video data for each pixel. V7b is held for one horizontal period. When a plasma discharge is generated in a predetermined scanning groove 7 (FIG. 3) by a plasma driver 32, which will be described later, the plasma discharge is read out for each horizontal line, and further converted to an analog signal by a D / A converter 28, and each signal is converted to a PALC ( The transparent drive electrode (ITO) 13 (red, plasma-type liquid crystal display element) 37 (1)
Green, blue drive electrodes 13R, 13G, 13B) (FIG. 3).

The LCD controller 29 is configured to operate with a power supply of, for example, 5 V, and counts a clock for driving the ramp waveform generator 30 based on an operation clock generated based on a synchronization signal from the NTSC demodulator 21. , An anode inversion pulse for driving the anode inversion drive circuit 31 and the plasma driver 32 for driving the scanning groove 7.
A plasma pulse for plasma discharge is generated for each (horizontal line).

The count clock from the LCD controller 29 is supplied to a ramp waveform generator 30. The ramp waveform obtained here is sent to a liquid crystal column driver 27 using a charge / hold type D / A conversion method described later. It is supplied to drive the transparent column electrode 13 of the PALC 37 (1).

In this embodiment, the plasma driver 32 shown in FIG. 1 has a horizontal scanning line corresponding to about 480 lines constituting an NTSC screen, that is, a PAL as shown in FIG.
The scanning grooves 7 formed in C37 (1) are sequentially selected, a plasma pulse is supplied, and a plasma discharge is generated by a power supply voltage of about -300 V applied to the cathode electrode 9.

That is, in synchronization with the double-speed video data V7b input to the liquid crystal column driver 27, the scanning grooves 7,
.. Are sequentially discharged from the top to the bottom, for example, and the discharge state is repeated for each field, so that the PALC 37 (1) can be driven according to the above-described video data. As a result, the input video signal can be displayed as a video.

The backlight 36 (2) is arranged as a light source for illuminating the PALC 37 (1) from the back side as shown in FIG. 2, and the emitted light beam passes through predetermined pixels of the PALC 37 (1). Thus, a display image is formed.
Further, picture adjustment can be performed by adjusting the brightness of the backlight 36 (2).

The microcomputer control unit 34 allows the user to operate the operation unit 33.
In accordance with a command input from, various controls such as the above-described tuning of each tuner, image adjustment, and power ON / OFF are performed.
In FIG. 1, the object to be controlled by the microcomputer control unit 34 and the microcomputer control unit 34 are connected by a broken line.

Next, the plasma (discharge) driver 32 will be described in detail with reference to FIG. In FIG. 6, PAL
An anode electrode 8 and a cathode electrode 9 of C37 (1) are also shown. For the plasma driver 32, a voltage of, for example, about -300 V from the plasma power supply Ep is used, and this voltage is applied to each line (for example, the first line L1 to L4).
(80th line L480: number of effective scanning lines) is applied to the cathode electrodes 9 (1), 9 (2),..., 9 (480) through the switching means and the current source. The cathode electrodes 9 (1) to 9 (480) are arranged as switching elements for plasma discharge, for example, NMOS.
(N channel MOS) Transistor Tr (1), Tr
(2),..., Connected to the drain of Tr (480).

NMOS transistors Tr (1) to Tr
The source electrodes of (480) are commonly connected, and are further connected to a plasma power supply Ep through a current source Si of, for example, about 100 mA.
And is controlled so that the current at the time of plasma discharge becomes constant, so that stable plasma discharge is performed. Cathode electrode 9 (1), 9
, 8 (480) corresponding to the anode electrodes 8 (1), 8 (2),.
Are commonly connected to the positive electrode of the plasma power supply Ep.
The NMOS transistors Tr (1) to Tr (48)
A positive pulse (plasma discharge pulse) of, for example, about 10 μsec supplied from the LCD controller 29 is sequentially applied to the gate electrode of (0) line by line.

NMOS transistors Tr (1) to Tr
When the plasma pulse from the LCD controller 29 is sequentially applied to the gate electrode of (480), first, for example, the anode electrode 8 (1) and the cathode electrode 9 ( A plasma discharge occurs between 1) and thereafter, a plasma pulse is sequentially applied to the cathode electrodes 9 (1) to 9 (480) from the first line L1 to the 480th line L480 in synchronization with the pixel signals for one line. This makes it possible to form an image for one field.

Next, the phase relationship between the video drive signal (write video data) supplied to the PALC 1 and the plasma discharge pulse will be described with reference to FIG. If the scanning period for one line is, for example, 32 μsec, for example, the NMOS corresponding to the first line L1 at the timing shown in FIG. 7B.
When a positive plasma pulse voltage of 10 μsec width is applied to the gate electrode of the transistor Tr (1), the cathode electrode 9 corresponding to the first line L1 as shown in FIG. 7C.
In (1), a negative pulse voltage having a voltage of −300 V and a width of 10 μsec is applied, and a plasma discharge occurs in the first scanning groove 7. In a state where the scanning groove 7 is plasma-discharged, a maximum of 60 V video signal sampled and held for each pixel shown in FIG. 7A is continuously applied to the drive electrode (ITO) 13 for, for example, about 20 μsec. By doing so, the video signal for one line can be written to the PALC 37 (1) (FIG. 1).

Then, in the subsequent second line L2, as shown in FIG. 7D, when a positive plasma pulse voltage of 10 μsec width is applied to the gate electrode of the NMOS transistor Tr (2), as shown in FIG. A negative pulse voltage having a voltage of -300 V and a width of 10 [mu] sec is applied to the cathode electrode 9 (2) corresponding to the line L2, and a plasma discharge occurs in the next scanning groove 7. In the state where the scanning groove 7 is in plasma discharge, as shown in FIG. 7A, the sample and hold is performed for each pixel, and the inverted data of the video signal of the second line up to 60 V is maintained for about 20 μsec, for example. Then, it is applied to the drive electrode (ITO) 13. Thus, in the first field, the inversion drive is performed alternately for each of the odd-numbered lines and the even-numbered lines, and in the next field, the data is alternately and reversely driven in the opposite phase.
The AC drive of (1) is realized to prevent the deterioration of the liquid crystal molecules due to the continuous application of the DC voltage.

By writing the video signals for 480 lines sequentially into the PALC 37 (1) at such timing, an image for one field can be formed and displayed.

Next, a plasma discharge pulse generation circuit will be described with reference to FIG. FIG. 8A shows a plasma discharge pulse generation circuit, and FIGS. 8B to 8J show operation waveforms. Reference numeral 71 denotes a cascade-connected, for example, 480-stage latch circuit. The discharge start pulse (FIG. 8B) is supplied to the D input terminal of the first-stage latch circuit 71, and each clock input terminal C of the 480-stage latch circuit 71 is supplied.
By supplying a common horizontal clock (H clock) (FIG. 8C) having a period equal to one horizontal period to K, 48
The zero-stage latch circuit 71 functions as a shift register. Each output of the 480-stage latch circuit 71 is represented by a1 (FIG. 8).
D), a2 (FIG. 8E), a3 (FIG. 8F), ‥‥‥‥‥,
a479 and a480. These outputs a1 to a48
0 is a single-shot pulse that is sequentially generated with a phase shift of one horizontal cycle. The discharge start pulse (FIG. 8B) is supplied to the D input terminal of the first-stage latch circuit 71, and its output a1
Is supplied to the D input terminal of the second-stage latch circuit 71,
The output a2 is supplied to the third-stage latch circuit 71.
出力 output a479 of the 479th stage latch circuit 71
Is supplied to the D input terminal of the latch circuit 71 of the 480th stage.

Each output a of the 480-stage latch circuit 71
1 to a480 are supplied to the 480 AND gates 72, and the enable pulse (FIG. 8G) having a time width of, for example, 10 μsec is supplied to the 480 AND gates 7.
2 are commonly supplied. Then, each output of the 480 AND gates 72 is used as the output a of the 480 latch circuits 71.
1, a2, a3,..., A479, a480, respectively, b1 (FIG. 8H), b2 (FIG. 8I),
b3 (FIG. 8J), Δ, b479, and b480. These outputs b1 to b480 are single-shot pulses sequentially generated each time the enable pulse arrives, and are 480 plasma discharge NMOS transistors Tr (1) to T (T) in FIG.
r (480) is supplied to each gate.

FIGS. 9 and 10 show a circuit configuration of a charge / hold type D / A converter 28 attached to the liquid crystal column driver 27 and an operation waveform thereof for holding video data. I do. A shift register (not shown) for sequentially storing one line of video signal for each pixel in the liquid crystal column driver 27 includes:
At the same time as capturing the last video data, the video data is transferred to the video data latch circuit 41 prepared by the number of pixels of one line of the D / A converter. Next, the data A of the up / down count circuit 42 for 128 clocks
And the video data B of the video data latch circuit 41 are compared in the comparator circuit 43, and the NMOS transistor (Q1) 45 is turned on until the data match.
In this state, the charge capacitor (CH) 44 is charged with the ramp waveform voltage VR. Note that this transistor (Q
1) A diode (D1) between the drain and source of 45
46 are connected. As shown in FIG. 10, for example, when the video data is 125, the ramp waveform voltage (VR) is charged to the charge capacitor (CH) 44 until the 126th count clock, and the comparator output of FIG. The voltage of the charge capacitor (CH) 44 at the moment of the change is held.

The D / A converted voltage is applied to the NMOS transistors (Q5) 50, (Q
6) The output impedance is reduced by 51 and supplied to each column drive electrode (ITO) 13. VDD is a drain power supply. Thus, the operation of the charge and hold type D / A conversion is performed.

When the drive electrode 13 is directly driven by a video signal of ± 60 V, a drive waveform of about 120 Vpp is required, which increases the cost of the semiconductor process of the D / A converter and the power consumption. The problem arises that is greatly increased. For this reason, a common anode inversion driving method is generally used. 11 and 12 show waveforms of the operation principle, and the common anode inversion driving method will be described with reference to these drawings.

In the common anode inversion driving method, for example, when writing a black signal of ± 60 V with a luminance of 0 IRE, as shown in FIG. 11A, a 60 V video signal (ITO driving voltage) on the positive side as shown in FIG. 11A. ) Is directly applied to the drive electrode (ITO) 13 and, at the same time, a voltage of 0 V is applied to the common electrode (corresponding to the common anode electrode in the case of PALC) as shown in FIG. 11B. In the next line, it is necessary to write a black signal of −60 V which is inverted for the inversion drive. First, as shown in FIG.
And then applied to the drive electrode (ITO) 13. At the same time, when this inversion signal is applied, as shown in FIG.
A voltage of V is applied. That is, when the electrode potential of the common anode is considered as a reference, the driving waveform becomes relatively ± 60 V as shown in FIG.
This is equivalent to performing direct drive of Vpp.

Here, the drive voltage on the inverted data side is substantially the inverted drive voltage waveform of the anode electrode.
Compared to the non-inverted side data hold section 20μsec,
The data inversion side is as long as about 32 μsec. This is because when the decay time until the impedance of the ionized plasma gas becomes completely infinite after the end of the plasma discharge requires, for example, more than 20 μsec, the black signal level on the inverted signal side is set to a maximum of 32 μsec. It means that you can write up to.

Therefore, in this specific example, the phase of the plasma discharge pulse (discharge enable pulse) is changed, as shown in FIG.
By moving the conventional plasma discharge pulse (discharge enable pulse) shown in FIG. 3B to the front side by 3 μsec, the write section of the negative drive voltage of −60 V is set to 26 μse.
It is set to c to improve the contrast ratio of the video signal. In practice, the adjustment is performed by changing the discharge phase so that the black level on the screen becomes the darkest.
FIG. 13A shows a drive voltage waveform of the liquid crystal described with reference to FIG.

Next, with reference to FIG. 14, a description will be given of a plasma discharge phase adjustment circuit in a plasma discharge pulse generation circuit of a specific example. FIG. 15 shows the operation waveform. In FIG. 14, reference numeral 81 denotes an inverting-side phase adjustment circuit, and 81D denotes a delay circuit. Reference numeral 82 denotes a non-inverting side phase adjustment circuit, and reference numeral 82D denotes its delay circuit. Each of the delay circuits 81D and 82D is composed of a cascade-connected four-stage latch circuit 83.
First-stage latch circuit 8 of each of delay circuits 81D and 82D
3 is supplied with an enable pulse (FIG. 15A), and each latch circuit 83 is supplied with, for example, 1 MHz.
(FIG. 15B) is supplied to each of the clocks (the cycle is 1 μsec) so that each of the clocks functions as a shift register.

The discharge enable pulse (FIG. 15A) is supplied to the first-stage latch circuit 83 of each of the delay circuits 81D and 82D, and the output of the first-stage latch circuit 83 is 2
The output of the second-stage latch 83 is supplied to the D-input terminal of the third-stage latch, and the output of the third-stage latch circuit 83 is supplied to the D-input terminal of the third-stage latch. It is configured to be supplied to the D input terminal of the circuit. Then, each output of the first to fourth latch circuits 83 of the delay circuits 81D and 82D (the enable pulse in FIG.
sec and 3 μsec delayed) select circuits 84 and 8
5 are selected and supplied to the inversion-side phase adjustment circuit 81 and the non-inversion-side phase adjustment circuit 82, respectively.

The outputs S1 and S1 of the selection circuits 84 and 85 of the inverting-side phase adjusting circuit 81 and the non-inverting-side phase adjusting circuit 82, respectively.
S2 is switched by a changeover switch 86 which is switched by an H / 2 clock having a half of the horizontal frequency, whereby a discharge enable pulse having a different delay time is output for each horizontal cycle, and this discharge enable pulse is output. 4 of the plasma discharge pulse generation circuit of FIG.
It is supplied commonly to the 80 AND gates 72.

In the example shown in FIG. 14, the selection circuit 84 of the inversion-side phase adjustment circuit 81 selects the first-stage latch circuit 8.
Since the output of the latch circuit 83 of the fourth stage (FIG. 15D) is selected by the selection circuit 85 of the non-inverting side phase adjustment circuit 82 while the output of FIG.
The time difference is 3 μse, which is three times the period of the 1 MHz clock.
becomes c. Then, the enable pulse S1 (FIG. 15)
C) and S2 (FIG. 15D) are set to 48 in FIG.
When supplied to the 0 AND gates, the discharge pulse of the inversion side data is 3 μsec as shown by the solid line waveform in FIG. 13C.
The phase is advanced.

When the power supply is turned off, conventionally, as shown in FIG. 16, the drive power supply voltage of the liquid crystal column driver 27 (FIG. 16A) and the power supply voltage of the anode inversion drive circuit 31 (FIG. 16A) are required for 20 msec. 16A) is simultaneously lowered to 0 V, and after the driving voltage (FIG. 16B) of the liquid crystal becomes 0 V (for example, a white level voltage in the case of a normally white liquid crystal panel), the discharge power supply is turned off. The voltage is maintained for one field period by a capacitor having a large charging capacity (for example, about 100 μF), and the drive voltage of 0 V is written to the liquid crystal so that the writing operation is not stopped while the DC voltage is applied to the liquid crystal. Therefore, measures were taken to prevent burning of the liquid crystal when the power was turned off. For example, N
Considering the TSC television signal, a total time constant of 37 msec was required for this discharge time constant of 20 msec and one field period (480 lines) of 17 msec. FIGS. 16C to 16I show enable pulses, and FIGS. 16F to 16I show enable pulses of the first to 480th lines for writing a drive voltage of 0V. FIG. 16J shows the stop of discharge.

Therefore, in a specific example, as shown in FIG. 17C, the phases of the enable pulses on the non-inverting side and the inverting side are instantaneously changed, for example, to 14 μsec and 20 μm, respectively, when the power is turned off.
With a further delay of μsec, the writing voltage (FIG. 17A) for about 20 μsec to the liquid crystal is set so that it goes from positive to negative for the non-inverted data and from negative to positive for the inverted data. Is designed to write an average voltage of 0 V (the sum of the areas of the hatched portions on the positive side and the negative side), thereby making it possible to reduce the capacity of a large-capacity capacitive element used for measures against burn-in when the power is turned off. Since a time constant of 17 msec for one field is sufficient, the capacity of a large-capacitance element used for the countermeasure for burn-in at the time of power-off can be reduced to about 容量 of the conventional capacity (for example, about 50 μF). . FIG. 17B shows an enable pulse during normal operation.

Next, referring to FIG. 18, a description will be given of a plasma discharge phase adjusting circuit when the power is turned off in the plasma discharge pulse generating circuit of the specific example. FIG. 19 shows the operation waveform. In FIG. 18, reference numeral 91 denotes an inverting-side phase delay circuit, and reference numeral 91D denotes its delay circuit. The delay circuit 91D includes a 20-stage cascade-connected latch circuit 93, and the D circuit of the first-stage latch circuit 93 is provided.
While the enable pulse S1 is supplied to the input terminal,
By supplying a clock of 1 MHz (the cycle is 1 μsec) (FIG. 19B) to each of the latch circuits 93,
The delay circuit has a delay time of 20 μsec. Also, 92
Denotes a non-inverting side phase delay circuit, and 92D denotes the delay circuit. The delay circuit 92D includes a cascade-connected 14-stage latch circuit 93. The enable pulse S2 is input to the D input terminal of the first-stage latch circuit 93.
And 1 MHz is supplied to each of the latch circuits 93.
Is supplied (FIG. 19B), a delay circuit having a delay time of 14 .mu.sec is obtained.

In the inverting-side phase delay circuit 91, the output enable pulse S1 (FIG. 15C) and the output enable pulse S1 are supplied to the delay circuit 91D for 20 μsec.
The delayed enable pulse and the changeover switch 94
And is switched by a switching signal at power-off (for example, obtained from a control port of a microcomputer). In the non-inverting phase delay circuit 92, the output enable pulse S2 (FIG. 15D) (FIG. 19A) and the output enable pulse S2 are supplied to the delay circuit 92D and delayed by 14 μsec (FIG. 19).
C) is supplied to the changeover switch 95, and is switched by a switching signal at power-off (for example, obtained from a control port of a microcomputer).

The outputs S4 and S5 of the changeover switches 94 and 95 of the inverting-side phase delay circuit 91 and the non-inverting-side phase delay circuit 92 are switched by an H / 2 clock having half the horizontal frequency. By switching by the changeover switch 96, a discharge enable pulse S3 having a delay time different from 20 μsec and 14 μsec is output every horizontal cycle, and this discharge enable pulse is connected to the 480 ANs of the plasma discharge pulse generation circuit of FIG.
DLC 72 supplies PALC1 in common.
Is written with an average voltage of 0V.

According to the above specific example, the transparent driving electrode 13
Even if a driving circuit (column driver IC) for supplying a video signal having an asymmetric driving waveform is used, a low cost and high performance driving apparatus for a plasma addressed liquid crystal display device having an excellent contrast ratio can be obtained. it can.

[0069]

According to the first aspect of the present invention, a transparent first scanning electrode group arranged on the first surface side of the plasma addressed liquid crystal display element and the second scanning electrode group arranged on the first face side of the plasma addressed liquid crystal display element. And a second scan electrode group consisting of a pair of an anode electrode and a cathode electrode forming a plurality of plasma discharge channels arranged so as to be orthogonally opposed to the first scan electrode group. A first driving unit for driving a first scanning electrode group by a video signal voltage alternately inverted and non-inverted every horizontal cycle; and a first scanning electrode group. Generates a plasma discharge pulse whose phase can be independently adjusted and set according to the polarity of the video signal voltage so that an asymmetric component corresponding to the polarity is not generated in the writing efficiency of the video signal voltage to be driven. Since the plasma discharge pulse generating means and the second driving means for driving the second scan electrode group by the plasma discharge pulse from the plasma discharge pulse generating means are provided, the phases of the plasma discharge driving pulse are set to the positive side and the negative side. It is possible to obtain a driving device for a plasma-addressed liquid crystal display device which can be adjusted and set independently for each driving voltage on the side, and which can maximize and symmetrically write the liquid crystal driving voltage on the non-inverting side and the inverting side.

According to the first aspect of the present invention, depending on the type of the plasma discharge gas, the time until the conductive gas state disappears after the plasma discharge discharge, that is, the decay time, is affected by the polarity of the driving voltage. In some cases, the write efficiency of the liquid crystal drive voltage can be set to an optimum value according to the polarity of each drive voltage.

According to a second aspect of the present invention, in the driving apparatus for a plasma addressed liquid crystal display device according to the first aspect of the present invention, the plasma discharge pulse generating means instantaneously delays the phase of the plasma discharge pulse when the power is turned off. In one driving means, the writing section of the video signal voltage is set to be a section in which the polarity of the video signal voltage changes, and a driving voltage of 0 V as an average value of the writing voltage of the video signal voltage is set to a plasma address type liquid crystal display element. To prevent the DC component from remaining in the plasma addressed liquid crystal display element when the power is turned off. Therefore, in addition to the effect of the first aspect of the present invention, burn-in of the plasma addressed liquid crystal display element when the power is turned off is performed. Can be prevented.

According to the second aspect of the present invention, it is possible to reduce the capacity of a large-capacity capacitor for charging a power supply voltage for plasma discharge required to stably maintain plasma discharge when the power is off.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a driving circuit of a plasma addressed liquid crystal display device according to a specific example of an embodiment of the present invention.

FIG. 2 is an exploded perspective view showing a plasma addressed liquid crystal display device used in a specific example.

FIG. 3 is a partially cutaway perspective view showing a plasma addressed liquid crystal display element used in a specific example.

FIG. 4 is a partially cutaway perspective view showing a plasma-addressed liquid crystal display device for explaining generation of a plasma channel by plasma discharge.

FIG. 5 is a circuit diagram showing an A plasma channel.
B is a circuit diagram showing an equivalent circuit of the plasma channel.

FIG. 6 is a circuit diagram showing a circuit of a plasma discharge driver used in a specific example.

FIG. 7 is a timing chart showing a phase relationship between video data written to a liquid crystal display element and a plasma discharge pulse. FIG. 5 is a waveform diagram showing AD / A converted video output data. FIG. 6 is a waveform diagram showing a gate voltage of an NMOS transistor on a B1 line. It is a waveform diagram which shows the cathode waveform of C1 line. FIG. 9 is a waveform chart showing the gate voltage of the NMOS transistor on the D2 line. FIG. 9 is a waveform chart showing a cathode voltage of the NMOS transistor on the E2 line.

FIG. 8 is a circuit diagram showing a charge-and-hold type D / A converter used in a specific example A; It is an operation waveform diagram of the circuit of B-JA. B is a waveform diagram showing a start pulse. FIG. 4 is a waveform diagram showing a CH clock. It is a waveform diagram which shows D output a1. FIG. 9 is a waveform chart showing an E output a2. It is a waveform diagram which shows F output a3. It is a waveform diagram which shows G enable. FIG. 9 is a waveform chart showing an H output b1. It is a waveform diagram which shows I output b2. FIG. 9 is a waveform chart showing a J output b3.

FIG. 9 shows a charge-and-hold type D /
It is a circuit diagram which shows an A converter.

FIG. 10 is a timing chart at the time of operation of the D / A converter when the video data is 125; FIG. 6 is a waveform diagram showing an A count clock. It is a waveform diagram which shows BD / A conversion output. It is a waveform diagram which shows C comparator output.

FIG. 11 is a timing chart showing the operation principle of the common anode inversion driving method, and is a diagram showing an actual driving waveform when the luminance is 0IRE. A is a waveform of an ITO drive voltage. B is a waveform of an anode inversion drive voltage.

FIG. 12 is a timing chart illustrating the operation principle of the common anode inversion driving method, and is a diagram illustrating a liquid crystal driving voltage waveform based on an anode potential.

FIG. 13 is a timing chart for explaining an optimum plasma discharge phase on the inverted data side. 3A is a waveform diagram showing a driving voltage of the liquid crystal. FIG. B is a waveform diagram showing a conventional enable pulse. C is a waveform diagram showing an enable in a specific example.

FIG. 14 is a block diagram showing a specific example of a plasma phase adjustment circuit.

FIG. 15 is a timing chart for explaining the operation of the plasma phase adjustment circuit of FIG. 14; FIG. 4 is a waveform diagram showing an A enable pulse. B is a waveform diagram showing a 1 MHz clock. FIG. 6C is a waveform chart showing a plasma inversion-side pulse. D is a waveform diagram showing a non-inversion side plasma enable pulse. FIG.

FIG. 16 is a timing chart showing a conventional write sequence of a drive voltage of 0 V when the power is turned off. FIG. 3A is a waveform diagram showing a liquid crystal drive power supply voltage. FIG. 6B is a waveform chart showing a driving voltage of the liquid crystal. It is a waveform diagram which shows CI enable pulse. It is a figure which shows J discharge stop.

FIG. 17 is a diagram illustrating a plasma discharge phase delay when power is turned off.
6 is a timing chart showing writing of V. A is a driving voltage waveform of the liquid crystal. B is a waveform diagram showing an enable pulse during a normal operation. C is a waveform diagram showing an enable pulse when the power is off.

FIG. 18 is a block diagram showing a plasma phase delay circuit when a power supply is turned off in a specific example.

FIG. 19 is a timing chart for explaining the operation of the plasma phase delay circuit when the power is turned off in FIG. 18; FIG. 4A is a waveform diagram showing an enable pulse on the non-inverting side. B is a waveform diagram showing a 1 MHz clock. FIG. 9C is a waveform diagram showing an inversion-side plasma enable pulse when the power is off.

[Explanation of symbols]

1 PALC liquid crystal display device, 2 backlight, 3, 4
Polarizing filter, 5 plasma substrate (back glass), 6
Partition walls (ribs), 7 scanning grooves (plasma channels), 8
Anode electrode, 9 Cathode electrode, 10 Insulating layer (thin glass), 11 Liquid crystal layer, 12 Color filter, 1
3 Transparent electrode (ITO thin film), 14 front glass, 21
NTSC demodulator, 22 frame double speed conversion circuit, 23
Video signal processing circuit, 24 A / D converter, 25 error diffusion processing unit, 26 white balance adjustment circuit, 27 liquid crystal column driver, 28 D / A converter, 29 LCD
Controller, 30 ramp waveform generation circuit, 31 anode inversion drive circuit, 32 plasma driver, 33 operation section, 34 microcomputer control section, 35 power supply circuit, 36
Backlight picture adjustment circuit, 37 Plasma address type liquid crystal display element (PALC).

Claims (2)

[Claims] 2. A plasma addressed liquid crystal display device comprising:
A first transparent electrode group disposed on the second surface side of the plasma addressed liquid crystal display element, and a transparent first scanning electrode group disposed on the second surface side of the plasma addressed liquid crystal display element. In a plasma addressed liquid crystal display device having a second scanning electrode group consisting of a pair of an anode electrode and a cathode electrode forming a plurality of arranged plasma discharge channels, the liquid crystal display device is alternately inverted and non-inverted every horizontal cycle. A first driving unit that drives the first scanning electrode group by the obtained video signal voltage; and an asymmetric component corresponding to the polarity does not occur in the writing efficiency of the video signal voltage that drives the first scanning electrode group. A plasma discharge pulse generating means for generating a plasma discharge pulse whose phase can be independently adjusted and set according to the polarity of the video signal voltage; And a second driving means for driving the second scanning electrode group by a plasma discharge pulse from the driving means. 2. The driving apparatus for a plasma addressed liquid crystal display device according to claim 1, wherein said plasma discharge pulse generating means instantaneously delays the phase of said plasma discharge pulse when power is turned off,
In the first driving means, the writing section of the video signal voltage is set to be a section in which the polarity of the video signal voltage changes, and the driving voltage of 0 V as an average value of the writing voltage of the video signal voltage is set to the plasma address. A driving device for driving a plasma addressed liquid crystal display device, wherein data is written to the liquid crystal display device to prevent a DC component from remaining in the plasma addressed liquid crystal display device when the power is turned off.