JPH11261930A - Driving circuit for liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a driving circuit for the liquid crystal display device used for a camcorder or the like to drive simultaneously two liquid crystal display devices with different frequencies of horizontal scanning pulses. SOLUTION: This drive circuit is provide with a 1st horizontal drive pulse generating circuit 24 that drives a 1st liquid crystal display device and with a 2nd horizontal drive pulse generating circuit 34 that drives a 2nd liquid crystal display device separately so as to configure the driving circuit in a way that the 1st liquid crystal display device and the 2nd liquid crystal display device use in common an RGB image signal output circuit and a vertical drive pulse generating circuit 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a camera-integrated VT.
The present invention relates to a driving circuit of a liquid crystal display device used for R or the like.

[0002]

2. Description of the Related Art In recent years, an increase in the number of camera-integrated VTRs equipped with a liquid crystal display device for monitor display has been increasing in addition to a liquid crystal display device for a viewfinder which has been conventionally used. A liquid crystal display device for a viewfinder is suitable for outdoor use under strong sunlight, while a liquid crystal display device for a monitor display is used for photographing a rapidly moving subject or taking a camera-integrated VTR away from the eyes. However, in a camera-integrated VTR equipped with such two liquid crystal display devices, it is possible to use only one of the liquid crystal display devices according to the shooting conditions, or to use the two liquid crystal display devices. Are configured to be used at the same time.

As a liquid crystal display device used in a camera-integrated VTR, an active matrix type liquid crystal display device is generally used. Among them, a TFT type liquid crystal display device capable of obtaining a high contrast and a half tone is used. There are many. As the TFT type liquid crystal display device, an amorphous silicon TFT and a polysilicon TFT are known depending on a difference in a semiconductor material.

An amorphous silicon TFT is a configuration in which a TFT formed on a glass substrate as an active element is driven by an IC chip made of single crystal silicon added on a separate substrate, and is about 2.5 inches to more than 10 inches. Suitable for relatively large liquid crystal display devices up to.

[0005] On the other hand, the polysilicon TFT has a high process temperature, so that the substrate material and the film forming apparatus are restricted.
Although it is difficult to increase the size, it is possible to drive the TFT by a MOS transistor formed on a glass substrate without adding an IC chip, and it is suitable for a relatively small liquid crystal display device up to about 2 inches. I have.

Therefore, in a camera-integrated VTR, a large liquid crystal display device using amorphous silicon TFTs is used for monitor display, while a small liquid crystal display device using polysilicon TFTs is used for viewfinder. .

[0007]

In a camera-integrated VTR equipped with two liquid crystal display devices as described above, each of the liquid crystal display devices is separately provided due to a difference in the frequency of the horizontal scanning pulse of each liquid crystal display device. And a separate drive circuit was mounted. This leads to an increase in circuit volume and circuit weight, and a camera-integrated VTR.
Hindered the miniaturization and weight reduction of

When both liquid crystal display devices are driven at the same time, it is necessary to operate two driving circuits, and the power consumption is greatly increased. I was holding it.

Further, when separate driving circuits are mounted on the liquid crystal display device for the monitor display and the liquid crystal display device for the viewfinder, it is necessary to develop each driving circuit separately, which increases the number of design steps. In addition to this, two adjustments were required on the production line.

[0010]

In order to solve the above problems, a driving circuit for a liquid crystal display device according to the present invention comprises: a first liquid crystal display device driven at a predetermined horizontal scanning frequency; A second liquid crystal display device driven by a horizontal scanning frequency different from the horizontal scanning frequency is connected;
The same video information can be simultaneously displayed on the first liquid crystal display device and the second liquid crystal display device based on an input video signal, and the drive circuit of the liquid crystal display device includes at least: A first drive signal output unit that outputs a first drive signal for displaying the video information on the first liquid crystal display device based on a synchronization signal included in the input video signal; A second drive signal output unit for outputting a second drive signal for displaying the video information on the second liquid crystal display device based on the included synchronization signal; Is comprised of a first horizontal drive signal and a first vertical drive signal, the second drive signal is comprised of a second horizontal drive signal, and the first liquid crystal display device is First horizontal drive signal And the first liquid crystal display device is driven based on the first vertical drive signal, and the second liquid crystal display device is driven based on the second horizontal drive signal and the signal related to the first vertical drive signal. It is.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The driving circuit of a liquid crystal display device according to the present invention is characterized in that one driving circuit can simultaneously drive two liquid crystal display devices having different horizontal scanning pulse frequencies. The details will be described.

FIG. 1 is a block diagram for explaining a basic configuration of a driving circuit of a liquid crystal display device according to the present invention. FIG.
, 1 is a camera-integrated VTR for outputting a video signal from a camera or a VTR, and 2 is a camera-integrated VT.
A drive circuit for simultaneously driving the monitor liquid crystal display device 3 (monitor LCD panel) and the viewfinder liquid crystal display device 4 (viewfinder LCD panel) in accordance with the video signal output from the R unit 1. Here, a liquid crystal display device using an amorphous silicon TFT with a large number of pixels is used for the monitor liquid crystal display device 3, and a liquid crystal display device using a polysilicon TFT with a small number of pixels is used for the viewfinder liquid crystal display device 4. I have. The drive circuit 2 includes a decoder section 2a, a timing generator section 2b (TG section), and a viewfinder driving additional circuit 2c.

Here, a decoder section 2a, a timing generator section 2b, and a viewfinder driving additional circuit 2c
The respective configurations will be described with reference to FIG. First, the decoder section 2a will be described. Reference numeral 10 denotes an input of a video signal from the camera-integrated VTR section 1 and a luminance signal (Y).
/ Y / C separation circuit for separating and outputting a color signal (C)
11 is a color signal (C) output from the Y / C separation circuit 10
Demodulation circuit that outputs color difference signals (I, Q) based on
A matrix circuit 2 combines the luminance signal (Y) from the Y / C separation circuit 10 and the color difference signals (RY, BY) from the demodulation circuit 11 to output image signals (R, G, B). It is.

Reference numeral 13 denotes an amplitude adjustment circuit for shaping an image signal (R, G, B) output from the matrix circuit 12 into an appropriate waveform and adjusting the amplitude level, and reference numeral 14 denotes an image signal from the amplitude adjustment circuit 13. Is input, and the polarity of the input image signal (R, G, B) is inverted every horizontal scanning line and every video field based on an inverted signal (FRP) from an inverted signal generating circuit 28 in the timing generator section 2b described later. Image signals (VR, VG, V
B) for outputting the image signal (V).
R, VG, VB) are output to the monitor liquid crystal display device 3.

Reference numeral 15 denotes a camera-integrated VTR 1
The horizontal and vertical synchronizing signals only are extracted from the video signal from the phase comparator 20, a phase synchronizing circuit 20, a vertical synchronizing separating circuit 25 in the timing generator 2b, and a phase comparing circuit 30 in the viewfinder driving additional circuit 2c.
Is output to the sync separation circuit.

With the above configuration, the decoder 2a
Outputs an image signal (VR, VG, VB) to the monitor liquid crystal display device 3 based on an input video signal and an inverted signal (FRP) from the timing generator 2b, and drives the timing generator 2b and the viewfinder. And outputs a synchronization signal to the additional circuit 2c.

Next, a description will be given of the timing generator section 2b. Reference numeral 20 denotes a vertical and horizontal synchronizing signal from the synchronizing / separating circuit 15 in the decoder section 2a, which is output from a horizontal frequency dividing circuit 23 to be described later. A phase comparison circuit that performs phase comparison with a signal and outputs a signal corresponding to the phase difference; 21 is an integration circuit that outputs a DC component of a signal output from the phase comparison circuit 20; 22 is output from the integration circuit 21 A voltage controlled oscillator (VCO) 23 oscillating a high frequency signal according to the voltage level of the signal, separates the high frequency signal output from the voltage controlled oscillator 22 according to the frequency of the horizontal scanning pulse of the monitor liquid crystal display device 3. This is a horizontal frequency dividing circuit that outputs a signal having a period corresponding to one horizontal scanning line period of a video signal.

The output signal of the horizontal frequency dividing circuit 23 is fed back to the phase comparing circuit 20,
0, a loop formed by the integrating circuit 21, the voltage controlled oscillation circuit 22, and the horizontal frequency dividing circuit 23, so that the timing of the video signal input to the decoder 2a and the timing of the signal output by the horizontal frequency dividing circuit 23 coincide. Phase lock is applied.

Reference numeral 24 denotes a horizontal pulse generating circuit for outputting an HSTART signal and an HCLOCK signal necessary for driving the monitor liquid crystal display device 3 in the horizontal direction based on the output signal of the horizontal frequency dividing circuit 23; The vertical and horizontal synchronizing signals from the synchronizing and separating circuit 15 in 2a are inputted, and the vertical synchronizing signal separating circuit 26 separates and outputs only the vertical synchronizing signal, and 26 further divides the signal output from the horizontal frequency dividing circuit 23. This is a vertical frequency dividing circuit that outputs a signal having a period coincident with one vertical scanning period of a video signal. The vertical frequency dividing circuit 26 is mainly composed of a counter.
By using the vertical synchronization signal output from the vertical synchronization separation circuit 25 as a reset signal of the counter, the timing of the video signal input to the decoder unit 2a and the timing of the signal output by the vertical frequency division circuit 26 are matched.

Reference numeral 27 denotes a vertical pulse generating circuit for outputting a VSTART signal and a VCLOCK signal necessary for driving the monitor liquid crystal display device 3 in the vertical direction based on the output signal of the vertical frequency dividing circuit 26; An inverted signal generating circuit for outputting an inverted signal (FRP) for inverting a pulse for each horizontal scanning line and for each video field based on the output signal of the circuit 23. The output signal of the inverted signal generating circuit 28 is a decoder. After being output to the polarity inversion circuit 14 in the unit 2a and pulled up to a predetermined potential, the counter voltage signal (VCO
M).

In the above-described configuration, the timing generator section 2b sends a counter voltage signal (VCOM) and a horizontal drive pulse to the monitor liquid crystal display device 3 based on the synchronization signal input from the decoder section 2a. HSTAR
A T signal and an HCLOCK signal, and a VSTART signal and a VCLOCK signal, which are vertical drive pulses, are output.

Lastly, the viewfinder driving additional circuit 2c will be described. The vertical and horizontal synchronizing signals from the synchronizing / separating circuit 15 in the decoder section 2a are input to the input section 30. A phase comparison circuit that performs a phase comparison with the output signal and outputs a signal corresponding to the phase difference, 31 is an integration circuit that outputs a DC component of the signal output from the phase comparison circuit 30, and 32 is an integration circuit that outputs A voltage controlled oscillator (VCO) for oscillating a high-frequency signal according to the voltage level of the output signal;
Reference numeral 3 denotes a frequency-divided high-frequency signal output from the voltage-controlled oscillation circuit 32 in accordance with the frequency of the horizontal scanning pulse of the viewfinder liquid crystal display device 4, and outputs a signal having a period matching one horizontal scanning line period of the video signal. This is a horizontal frequency dividing circuit.

The output signal of the horizontal frequency dividing circuit 33 is fed back to the phase comparing circuit 30, and the phase comparing circuit 3
0, a loop formed by the integrating circuit 31, the voltage controlled oscillation circuit 32, and the horizontal frequency dividing circuit 33 so that the timing of the video signal input to the decoder unit 2a coincides with the timing of the signal output by the horizontal frequency dividing circuit 33. Phase lock is applied.

Reference numeral 34 denotes a horizontal pulse generating circuit for outputting an Hstart signal and an Hclock signal necessary for driving the viewfinder liquid crystal display device 4 in the horizontal direction based on the output signal of the horizontal frequency dividing circuit 33; This is a gain amplifier that adjusts the level of the image signal (VR, VG, VB) output from the polarity inversion circuit 14 in the section 2a to the input level of the liquid crystal display device 4 for a viewfinder, and 35a for the R system and 35b for the G system. , B system, and 35c for each output signal (Vr,
Vg, Vb) are output to the viewfinder liquid crystal display device 4.

An integration circuit 36 outputs the DC component (having the potential of Ecom) of the signal output from the gain amplifier 35b. The output of the integration circuit 36 is output from the liquid crystal display device 4 for the viewfinder to the counter electrode voltage signal (Vcom). ). Here, the counter voltage signal (Vcom) is based on the signal (Vg) output from the gain amplifier 35b.
Has been shown, but the counter voltage signal (Vcom) may be generated based on the signal (Vr) output from the gain amplifier 35a or the signal (Vb) output from the gain amplifier 35c, or The counter voltage signal (Vcom) may be generated based on the combination.

With the above-described configuration, the decoder 2c sends the image signals (Vr, Vr, Vr) to the viewfinder liquid crystal display device 4 based on the synchronization signal and the image signals (VR, VG, Vb) input from the decoder 2a. Vg, Vb), a counter voltage signal (Vcom), and a horizontal drive pulse Hs
A start signal and an Hclock signal, and a Vstart signal and a Vclock signal, which are drive pulses in the vertical direction, are output.

The drive circuit 2 has the decoder 2
a, a timing generator section 2b and an additional circuit for driving a viewfinder 2c, so that both the liquid crystal display devices for the monitor 3 and the viewfinder 4 can be driven simultaneously.

Here, the horizontal drive pulse output to the monitor liquid crystal display device 3 and the horizontal drive pulse output to the viewfinder liquid crystal display device 4 are separately generated. This is because the frequency of the horizontal scanning pulse required for each liquid crystal display device is different.

On the other hand, in the monitor liquid crystal display device 3 and the viewfinder liquid crystal display device 4, the number of lines in the vertical direction is substantially reduced in order to display the same video signal composed of a predetermined number of horizontal scanning line signals. Since they are provided to the same degree, the liquid crystal display device for monitor 3 and the liquid crystal display device for viewfinder 4 can be driven based on the drive pulse output from the vertical pulse generation circuit 27 in the timing generator section 2b.

In this case, the monitor liquid crystal display device 3
A liquid crystal display device using an amorphous silicon TFT is used as an example, and a liquid crystal display device using a polysilicon TFT is used as a liquid crystal display device 4 for a viewfinder. However, a liquid crystal display device 3 for a monitor and a liquid crystal display device for a viewfinder are shown. In the case where a liquid crystal display device using polysilicon TFTs is used for both of them, the gain amplifier 35 in the viewfinder driving additional circuit 2c does not need to be provided, and the amplitude adjustment circuit 13 in the decoder unit 2a is not necessary.
The gain may be adjusted to an appropriate level with.

With respect to the counter voltage signal (VCOM) output to the monitor liquid crystal display 3, the counter voltage signal (Vc) output to the viewfinder liquid crystal display 4 is used.
om).

FIG. 3 is an explanatory diagram showing an example of an image signal and a driving pulse generated by the driving circuit 2. Here, the video signal input to the drive circuit 2 is (a), the red image signal (VR) output from the drive circuit 2 to the monitor liquid crystal display 3 is (b), and the counter electrode voltage signal (VCOM) is (D), the HSTART signal, which is a horizontal drive pulse, is shown as (f), the HCLOCK signal is shown as (g), and the red image signal (Vr) output to the viewfinder liquid crystal display device 4 is shown as (c). , Its counter voltage signal (Vco
m) to (e), Hstar which is a horizontal drive pulse.
The t signal is shown as (h) and the Hclock signal is shown as (i).

The red image signal (R) included in the video signal input to the drive circuit 2 is supplied to the polarity inversion circuit 14 as described above.
, The polarity is inverted for each horizontal scanning line and for each video field, and as shown in FIG.
R) is output to the monitor liquid crystal display device 3, and
After being amplified to an appropriate level by the gain amplifier 35a, it is output to the viewfinder liquid crystal display device 4 as a red image signal (Vr) shown in FIG.

Then, the horizontal driving pulse HS
TART signal, HCLOCK signal, Hstart signal,
The generation timing of the Hclock signal is set according to the difference in the system of the liquid crystal display devices connected to each other and the difference in the number of pixels. In the case of this embodiment, as described above, a liquid crystal display device using an amorphous silicon TFT is used as the monitor liquid crystal display device 3, and a liquid crystal display device using a polysilicon TFT is used as the viewfinder liquid crystal display device 4. Therefore, each driving pulse is greatly different, and the counter voltage signals (VCOM, Vc
om) is also different.

That is, the red image signal (V) shown in FIG.
R) has a small amplitude level, so that the counter voltage signal (VCOM) is a signal whose polarity is inverted every horizontal scanning line and every video field as shown in FIG. Since the red image signal (Vr) shown in FIG. 3C has a large amplitude level, the counter electrode voltage signal (Vcom) is a constant potential signal as shown in FIG. 3E.

Next, the monitor liquid crystal display device 3 and the viewfinder liquid crystal display device 4 driven by the drive circuit 2 will be described with reference to FIG. In the monitor liquid crystal display device 3 using an amorphous silicon TFT shown in FIG. 4A, reference numeral 40 denotes a horizontal drive pulse HST.
A horizontal scanning shift register to which the ART signal and the HCLOCK signal are input. Reference numeral 41 denotes a vertical driving pulse V.
A vertical scan shift register 42 to which the START signal and the VCLOCK signal are input is a pixel cell alloy 42 in which TFT liquid crystal elements are arranged in a matrix in the number of pixels.

Reference numeral 43 denotes an input image signal (VR,
VG, VB) based on signals from the horizontal scanning shift register 40.
Reference numeral 4 denotes an image signal (VR, VG, VB) taken in through a plurality of sample and hold switches 43 in the horizontal direction.
A plurality of hold capacitors 45 for storing lines correspond to image signals (V
R, VG, and VB) to the pixel cell alloy 42.
0, a plurality of sample / hold switches 43, a plurality of hold capacitors 44, and a plurality of operational amplifiers 45 are configured as a source driver IC.

The operation of the monitor liquid crystal display device 3 is as follows.
First, the HSTART signal output from the drive circuit 2 is H
When the clock of the HCLOCK signal is input during the period of the pulse, the H pulse is input to the first block in the horizontal scan shift register 40. Since the first block is connected to the gate side of the sample and hold switch 43a, the sample and hold switch 43a
is connected, and the input image signal (VB) is stored in the hold capacitor 44a.

When the clock of the HCLOCK signal is input again to the horizontal scan shift register 40, the horizontal scan shift register 40 shifts the H pulse to the next block every clock. At the timing when the H pulse is shifted to the next block, the HSTART signal is an L pulse, and the L pulse is input to the first block, so that the sample and hold switch 43a is opened. Therefore, the hold capacitor 44a holds the current image signal (VB) until the next H pulse is input to the first block.

On the other hand, since the H pulse is input to the next block, the sample / hold switch 43b is connected, and the input image signal (VR) is stored in the hold capacitor 44b. Then, each time the clock of the HCLOCK signal is input to the horizontal scan shift register 40, the H pulse is shifted, and is repeated until the H pulse reaches the last block of the horizontal scan shift register 40.

The image signals (VR, V
G, VB) are stored in each hold capacitor 44, and during the H pulse period of the VSTART signal input from the drive circuit 2 to the vertical scan shift register 41, the VCLO
The clock of the CK signal is input, and an H pulse is input to the first block of the vertical scan shift register 41.

The first block includes a pixel cell alloy 42.
Are connected in parallel to the TFT liquid crystal elements on the first line (not shown), the image signals stored in the respective hold capacitors 44 at the timing when the H pulse is input to the first block of the vertical scanning shift register 41. V
R, VG, and VB) are input to the pixel cell alloy 42 via the operational amplifiers 45, and simultaneously operate the TFT liquid crystal elements on the first line.

With the above operation, the image signal of the first line is displayed on the pixel cell alloy 42. The vertical scan shift register 41 outputs the VCLOCK output from the drive circuit 2.
The H pulse is shifted to the next block for each signal clock, and the new image signals (VR, VG, VB) stored in each hold capacitor 44 are shifted to the next block when the H pulse is input to the next block. The image signal is output to the cell alloy 42 and the image signal of the second line is displayed. This operation is repeated until the H pulse reaches the last block of the vertical scanning shift register 41, whereby 1
Image signals for the screen can be displayed.

Next, the polysilicon TF shown in FIG.
The viewfinder liquid crystal display device 4 using T will be described. In the liquid crystal display device 4 for a viewfinder using a polysilicon TFT, 50 is a horizontal scanning shift register to which an Hstart signal and a Hclock signal as horizontal driving pulses are inputted, and 51 is a Vstart signal and a Vclock signal as vertical driving pulses. Are input to the vertical scanning shift register, and 52 is a pixel cell alloy in which TFT liquid crystal elements are arranged in a matrix in the number of pixels.

Reference numeral 53 denotes a horizontal scanning shift register 50.
A plurality of buffer amplifiers that amplify and output pulses at
Reference numeral 54 denotes a plurality of source switches which output the input image signals (Vr, Vg, Vb) to the pixel cell alloy 52 based on the signals output from the plurality of buffer amplifiers.

The operation of the viewfinder liquid crystal display device 4 is as follows.
When the clock of the Vclock signal is input during a period in which the t signal is an H pulse, the clock signal is input to the first block of the vertical scanning shift register 51 connected in parallel to the TFT liquid crystal element on the first line (not shown) in the pixel cell alloy 52. An H pulse is input.

Then, Hst output from the drive circuit 2 is output.
When the clock of the Hclock signal is input during the period in which the art signal is the H pulse, the H pulse is input to the first block in the horizontal scan shift register 50. Since the first block is connected to the gates of the source switches 54a, 54b, 54c via the buffer amplifier 53, the H block in the Hstart signal is input to the first block of the horizontal scanning shift register 50 at the timing. , Image signals (Vr, Vg, Vb) are output to the pixel cell alloy 52 via the source switches 54a, 54b, 54c, and the head block of the vertical scan shift register 51 and the source switches 54a, 54b, 54c
, The TFT liquid crystal elements for three pixels operated simultaneously.

When the clock of the Hclock signal is input to the horizontal scan shift register 50 again, the horizontal scan shift register 50 shifts the H pulse to the next block every clock. At the timing when the H pulse is shifted to the next block, since the Hstart signal is still an H pulse as shown in FIG. 3H, the H pulse is input to both the first block and the next block. become.

As described above, in the liquid crystal display device using the polysilicon TFT, the image signals (Vr, Vg, Vb) are output for each of the three TFT liquid crystal elements in the pixel cell alloy 52, and the H pulse is input over a plurality of blocks. By doing so, an image signal is displayed on the pixel cell alloy 52.

In this embodiment, as shown in FIGS. 3H and 3I, four clocks of the Hclock signal are present during the H pulse period of the Hstart signal. An H pulse is input over a continuous block.

Then, the horizontal scanning shift register 50 stores H
Each time the clock of the clock signal is input, the H pulse is shifted. The H pulse reaches the last block of the horizontal scan shift register 50 and is repeated until the H pulse returns to the L pulse.
All are displayed above.

On the other hand, the vertical scanning shift register 51 shifts the H pulse input to the first block for each clock of the Vclock signal output from the drive circuit 2, and when the H pulse is input to the next block. This time, the image signal of the second line is displayed on the pixel cell alloy 52 in the same manner as the image signal of the first line. In this way,
By repeating until the H pulse reaches the last block of the vertical scanning shift register 51, an image signal for one screen can be displayed.

Thus, the monitor liquid crystal display device 3
And the viewfinder liquid crystal display device 4 includes a drive circuit 2
The image signal can be displayed simultaneously based on the image signal, the counter electrode voltage signal, and the driving pulse output from.

As described above, in this embodiment, the amorphous silicon T is used as the monitor liquid crystal display device 3.
An example in which a liquid crystal display device using an FT is used and a liquid crystal display device using a polysilicon TFT is used as the liquid crystal display device 4 for the viewfinder, but the liquid crystal display device using the polysilicon TFT is replaced with the monitor liquid crystal display device 3 and the viewfinder It can also be used with the liquid crystal display device 4 for use, and in that case, the drive circuit 2 can be configured more simply.

[0055]

According to the driving circuit for a liquid crystal display device according to the present invention, the same image information can be simultaneously displayed on the first liquid crystal display device and the second liquid crystal display device. When the driving circuit is mounted on a camera-integrated VTR, the photographer and the subject can simultaneously check the image being photographed, and the power consumption can be reduced because only one driving circuit is used. . Further, since it is only necessary to add a circuit for outputting a horizontal drive signal to the conventional drive circuit of the liquid crystal display device, an increase in circuit scale can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a basic configuration of a driving circuit of a liquid crystal display device according to the present invention.

FIG. 2 is a block diagram for explaining a configuration of a driving circuit of the liquid crystal display device according to the present invention.

FIG. 3 is an explanatory diagram illustrating an example of an image signal and a driving pulse generated by a driving circuit.

FIG. 4 is an explanatory diagram for describing a configuration of a liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Camera-integrated VTR part 2 ... Drive circuit 2a ... Decoder part 2b ... Timing generator part (TG part) 2c ... Viewfinder drive additional circuit 3 ... Monitor liquid crystal display (monitor LCD panel) 4 .... Viewfinder Liquid crystal display device (LCD panel for viewfinder) 10 Y / C separation circuit 11 Demodulation circuit 12 Matrix circuit 13 Amplitude adjustment circuit 14 Polarity inversion circuit 20, 30 Phase comparison circuit 21, 31, 36 Integration circuit 22, 32: voltage controlled oscillator (VCO) 23, 33: horizontal frequency divider 24, 34: horizontal pulse generator 25: vertical synchronization separator 26: vertical frequency divider 27: vertical pulse generator 28: inverted signal generation Circuits 35, 35a, 35b, 35c Gain amplifiers 40, 50 Horizontal scan shift registers 41, 51 Vertical scan shift registers 42, 52: Pixel cell alloy 43, 43a, 43b, 43c: Sample / hold switches 44, 44a, 44b, 44c: Hold capacitors 45, 45a, 45b, 45c: Operational amplifier 53: Buffer amplifiers 54, 54a, 54b; 54c ... Source switch

Claims (3)

[Claims] 1. A first liquid crystal display device driven at a predetermined horizontal scanning frequency and a second liquid crystal display device driven at a horizontal scanning frequency different from the predetermined horizontal scanning frequency are connected. A driving circuit for a liquid crystal display device capable of simultaneously displaying the same video information on the first liquid crystal display device and the second liquid crystal display device based on a video signal. 2. The liquid crystal display device according to claim 1, further comprising: a driving circuit for displaying the video information on the first liquid crystal display device based on at least a synchronization signal included in the input video signal.
First drive signal output means for outputting a drive signal of the second type, and a second drive signal output means for displaying the video information on the second liquid crystal display device based on a synchronization signal included in the input video signal.
2. A driving circuit for a liquid crystal display device according to claim 1, further comprising second driving signal output means for outputting said driving signal. 3. The first drive signal is composed of a first horizontal drive signal and a first vertical drive signal, the second drive signal is composed of a second horizontal drive signal, The first liquid crystal display device is driven based on the first horizontal drive signal and the first vertical drive signal, and
The liquid crystal display device of
3. The driving circuit for a liquid crystal display device according to claim 2, wherein the driving circuit is driven based on a signal related to the vertical driving signal.