JP2005222025A - Display panel control circuit and display panel control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel control circuit which can simultaneously display two or more display panels and suppress an increase of a circuit area. <P>SOLUTION: The display panel control circuit includes a voltage controlled oscillator (VCO) 100 for outputting a clock signal; a first-panel horizontal system pulse generation section 200; a second-panel horizontal system pulse generation section 500; a vertical system pulse generation section 600 which is commonly used among the first and second panels; a phase comparator 300; and a smoothing element 400. The first-panel horizontal system pulse generation section 200 and the second-panel horizontal system pulse generation section 500 respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLK 1 output with the VCO 100. It is thus possible to simultaneously drive two different panels. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display panel control circuit that controls display on a display panel such as a liquid crystal panel, and more particularly to a display panel control circuit that drives two display panels of different driving methods simultaneously.

  Liquid crystal display devices that display images using so-called liquid crystals are widely used. In a liquid crystal display device, a liquid crystal panel control circuit is mounted on a digital video camera (DVC), a digital camera (DSC), or other AV equipment having a liquid crystal panel display function.

  A conventional liquid crystal panel display control circuit will be described with reference to FIGS. 4, 5 and 6 to 10. FIG. 4 is a block circuit diagram showing a configuration of a control circuit for a liquid crystal panel display according to a conventional example. FIG. 5 is a block circuit diagram showing a specific configuration of a liquid crystal panel display control circuit according to a conventional example. This control circuit is a circuit used for a digital video camera or the like provided with two liquid crystal panels.

  A conventional display panel control circuit is input to a voltage controlled oscillator (hereinafter referred to as VCO) 1100, a horizontal drive pulse generator 1700 for the first panel and the second panel, and a horizontal synchronization signal input terminal 1010. The phase comparator 1300 that outputs a phase error between the horizontal synchronization signal HD and the phase comparison signal that is the output signal of the horizontal drive pulse generator 1700, and the phase error output of the phase comparator 1300 is smoothed and fed back to the VCO 1100. A smoother (hereinafter referred to as LPF) 1400, a first panel to which VCLK, which is an output signal of the horizontal drive pulse generator 1700, and a vertical synchronization signal VD input to the vertical synchronization signal input terminal 1020 are input; And a vertical drive pulse generator 1600 for the second panel. In the conventional display panel control circuit, the operations of the VCO 1100, the horizontal drive pulse generator 1700, and the vertical drive pulse generator 1600 are switched by the panel selection signal SEL. That is, the signal output from the panel selection signal input terminal 1070 is switched between the first panel signal and the second panel signal in accordance with “Hi” and “Lo” of the panel selection signal SEL. Specifically, the VCO 1100 outputs the first panel clock signal VCOCLK1 or the second panel clock signal VCOCLK2 in response to the panel selection signal SEL. Also, the horizontal drive pulse generator 1700 outputs the first panel horizontal output group to the first panel horizontal output group output terminal 1030 or the second panel horizontal output group in response to the panel selection signal SEL. Are output to the second panel horizontal output group output terminal 1050. The vertical drive pulse generation unit 1600 outputs the first panel vertical output group to the first panel vertical output group output terminal 1040 or the second panel vertical output group in response to the panel selection signal SEL. Whether to output to the second panel vertical output group output terminal 1060 is switched.

  By the way, the driving method of the liquid crystal panel is a one-pixel sequential transfer method in which three pixels corresponding to R (red), G (green), and B (blue) are sequentially driven, and three pixels of R, G, and B are simultaneously driven. There is a three-pixel simultaneous transfer method to display. In many cases, the horizontal shift clock in the one-pixel sequential transfer method is mainly made up of three-phase pulse signals, and the horizontal shift clock in the three-pixel simultaneous transfer method is made up of two-phase pulse signals.

  Further, the horizontal shift clock in the liquid crystal panel display in which the pixels are arranged in a delta arrangement needs to be phase-controlled in the odd rows (ODD lines) and even rows (EVEN lines) to match the pixel arrangement.

  FIG. 5 shows an example of a display panel control circuit that controls a one-pixel sequential transfer type panel as the first panel and a three-pixel simultaneous transfer type panel as the second panel.

  In the display panel control circuit shown in the figure, the horizontal drive pulse generator 1700 generates a signal HCLK1 obtained by dividing the output signal VCOCLK1 or VCOCLK2 of the VCO 1100 by 1/6 with a 1/6 divider 1210 by an H counter ( 1) 1220 clock signal. The signal HCLK1 is input to the first panel horizontal shift clock generator 1230 and the second panel horizontal shift clock generator 1530.

  One of the plurality of output signals of the H counter (1) 1220 is supplied to the phase comparator 1300, the output signal VCLK is supplied to the vertical drive pulse generating unit 1600, and the other output of the H counter (1) 1220 is output. The signal group is sent to the first panel horizontal output group terminal 1030 or the second panel horizontal output group terminal 1050.

  The first panel horizontal shift clock generator 1230 includes a 1/2 frequency divider 1231 that receives HCLK1 as a clock input, a shift register 1232 that receives VCOCLK1 or VCOCLK2 that is an output signal of VC01100, and a shift register 1232. Is output from a switch unit 1233 that switches the phase of the output signal between the ODD line and the EVEN line of the liquid crystal panel in which the pixels are arranged in a delta arrangement. From the first panel horizontal shift clock generating unit 1230, the first panel three-phase horizontal shift clocks CPH1, CPH2, and CPH3, which are output signals of the switch unit 1233, are used as the first panel horizontal shift clock output terminal 1035. Is output.

  The second panel horizontal shift clock generator 1530 receives a D-type flip-flop (hereinafter referred to as “D-FF”) in which HCLK1 is input as a clock via an inverter 1534 and the output of the 1/2 frequency divider 1231 is the D input. 1532), and a switch unit 1533 for switching the output of the 1/2 frequency divider 1231 and the output of the D-FF 1532 between the ODD line and the EVEN line of the liquid crystal panel arranged in a delta arrangement. From the switch unit 1533, the two-phase horizontal shift clocks CKH1 and CKH2 for the second panel are output to the second panel horizontal shift clock output terminal 1055.

  The vertical drive pulse generation unit 1600 includes a V counter (1) 1610 that receives VCLK as a clock input and an inversion processing unit 1640 that inverts the logic of each output of the V counter (1) 1610. The output signal group from the unit 1640 is output to the first panel vertical output group terminal 1040 or the second panel vertical output group terminal 1060.

  In the conventional display panel control circuit shown here, the VCO 1100, the horizontal drive pulse generating unit 1700, and the vertical drive pulse generating unit 1600 have the first level depending on the level of the panel selection signal SEL input to the panel selection signal input terminal 1070. The operation for the first panel and the operation for the second panel are switched.

  FIG. 6 is a circuit diagram showing a partial configuration of a conventional display panel control circuit. In the figure, a 1/2 frequency divider 1231 that is a component of the first panel horizontal shift clock generator 1230, a D-FF 1532 that is a component of the second panel horizontal shift clock generator 1530, and an inverter 1534 is shown. The output signal of the 1/2 frequency divider 1231 is CKHO, the output signal of the D-FF 1532 is CKHE, and the waveform diagram of these signals is shown in FIG.

  FIG. 8 is a waveform diagram showing changes in horizontal shift clocks for the first panel and the second panel output from the conventional display panel control circuit. Here, the output signal CKHO of the 1/2 divider 1231 is a horizontal shift clock for the ODD line of the second panel, and the output signal CKHE of the D-FF 1532 is a horizontal shift clock for the EVEN line of the second panel. It is. Also, ODD and EVEN may be reversed. As shown in FIG. 8, HCLK1 is a signal obtained by dividing VCOCLK1 or VCOCLK2 by a factor of 6, CKHO is a signal obtained by dividing HCLK1 by a factor of 2, and CKHE is a signal that is 90 degrees different from CKHO. Yes.

  FIG. 7 is a circuit diagram showing a specific configuration example of the shift register 1232 which is a component of the first panel horizontal shift clock generating unit 1230. The shift register 1232 delays the output signal CKHO of the 1/2 frequency divider 1231 by two clocks by VCOCLK1 or VCOCLK2 which is the output signal of the VCO 1100, and inputs the signal to the EX-OR and EX-NOR gates. , Three-phase output signals CPH1, CPH2, and CPH3 are obtained in which a period of two clock cycles of VCOCLK1 or VCOCLK2 is a Hi period. CPH1, CPH2, and CPH3 shown in FIG. 8 are horizontal shift clocks for the ODD line of the first panel, and CPH1, CPH2, and CPH3 that are delayed by one clock period of VCOCLK1 or VCOCLK2 are horizontal shift clocks for the EVEN line. And Although the circuit for obtaining CPH1, CPH2, and CPH3 for the EVEN line is not shown in FIG. 7, only the operation waveforms are shown in FIG. ODD and EVEN may be reversed.

  FIG. 9 is a waveform diagram showing horizontal shift clocks for the ODD line and the EVEN line of the first panel. As shown in the figure, since the first panel is a one-pixel sequential transfer type delta arrangement panel using a three-phase shift clock, the phase difference between the rising edges of CPH1, CPH2, and CPH3 is one pixel (also referred to as 1 dot). This is equivalent to minutes. In addition, since it is a one-pixel sequential transfer method, it is necessary to perform a shift correction for 0.5 pixels on the ODD line and the EVEN line, and the CPH1, CPH2, and CPH3 of EVEN are respectively delayed by delaying CPH1, CPH2, and CPH3 by one period of VCOCLK1. CPH2 and CPH3 are created.

On the other hand, the second panel is a three-pixel simultaneous transfer type delta arrangement panel using a two-phase shift clock, and therefore, as shown in FIG. Is equivalent to a time of 3 pixels (also referred to as 3 dots). Here, FIG. 10 is a waveform diagram showing horizontal shift clocks for the ODD line and the EVEN line of the second panel. As shown in the figure, CKHE = CKH1 is set for the EVEN line, and a shift correction of 1.5 pixels is performed from the shift clock for the ODD line.
JP-A-2-137586

  However, in the conventional display panel control circuit described above, when the first panel is displayed, the output signal VCOCLK1 of the VCO 1100 is set to the first frequency determined from the period of one pixel of the first panel. In the case of setting and displaying the second panel, it is necessary to set VCOCLK2, which is an output signal of the VCO 1100, to the second frequency determined from the period of one pixel of the second panel. Therefore, in the conventional display panel control circuit, the first panel and the second panel can be displayed alternately, but the first panel and the second panel cannot be displayed simultaneously. .

  If two VCOs are prepared and two PLL loops are provided, two panels can be displayed at the same time. However, when the display panel control circuit is integrated and used, the circuit size increases and the area of the entire LSI is reduced. There was a problem that it could not be reduced.

  Furthermore, in the past, in order to drive and display two different types of liquid crystal panels at the same time, two LSIs each having a separate display panel control circuit were used, so the area of the entire set on which the LSIs were mounted increased. was there.

  Note that the control circuit of the liquid crystal display device disclosed in Japanese Patent Laid-Open No. 2-137586 is a circuit for driving one display panel, although it solves the problem of still image reproduction in the VTR. Other prior art documents do not disclose a control device or control circuit related to liquid crystal display for simultaneously displaying a plurality of liquid crystal panels.

  The present invention solves the above-described conventional problems, and provides a display panel control circuit capable of simultaneously displaying two or more display panels with one VCO and suppressing an increase in circuit area. Objective.

  In order to solve the above problems, a display panel control circuit according to the present invention is a display panel control circuit that controls display on a first panel and a second panel, and includes a voltage-controlled oscillator that outputs a clock signal, A first panel horizontal pulse generation unit that has a first counter that counts a clock signal and is reset at a first frequency division ratio, and outputs a horizontal output pulse group for the first panel; A second counter that counts the clock signal and is reset at the same timing as the first counter is reset, and outputs a horizontal output pulse group for the second panel. 2 panel horizontal pulse generators.

  With this configuration, the clock of the first counter and the clock of the second counter can be generated without switching the output signal of the voltage controlled oscillator. Therefore, the horizontal output pulse group for the first panel and the horizontal output pulse group for the second panel can be output at the same time, so that two display panels having different driving methods are driven simultaneously. It becomes possible. Thus, for example, if the display panel control circuit of the present invention is installed in a digital video camera, the monitor and the liquid crystal panel of the viewfinder can be displayed at the same time. Note that three or more display panels can be simultaneously driven by using the display panel control circuit of the present invention.

  In addition, the first panel and the second panel have a third counter that counts an output signal of the horizontal panel pulse generation unit as a clock and is reset by a vertical synchronization signal. It is preferable to further include a vertical pulse generation unit that outputs a vertical output pulse group.

  A phase comparator that compares the phase of the output signal of the first horizontal panel pulse generator and the phase of the horizontal synchronizing signal, and the phase error voltage as a PLL loop in response to the comparison result by the phase comparator. And a smoother for feeding back to the type oscillator. As a result, the PLL operates so that the reset timing of the first counter coincides with the timing of the externally input horizontal synchronization signal HD. Therefore, the reset timing of the counter of the second panel horizontal pulse generator is also set to the horizontal synchronization signal. The display timing can be matched and display disturbance can be suppressed.

  The first panel horizontal pulse generating unit further includes a first frequency divider that generates a clock of the first counter by dividing the clock signal by 1 / N (N is a positive integer). And the second panel horizontal pulse generating unit divides the clock signal by 1 / M (M is a positive integer different from N) to generate a clock for the second counter. By further including the frequency divider, it is possible to generate a reference signal of a horizontal output pulse group that is different for each panel.

  The PLL reset signal output from the first counter is input to the second frequency divider and the second counter, so that the horizontal shift clock and the horizontal output pulse for the second panel are horizontally synchronized. Since it is possible to synchronize with a signal, display disturbance can be suppressed.

  The display panel control method of the present invention also includes a voltage-controlled oscillator, a first panel horizontal pulse generator having a first counter, and a second panel horizontal pulse generator having a second counter. A display panel control circuit using a display panel control circuit comprising: a display panel control circuit for simultaneously controlling display of a first panel and a second panel, wherein the first clock signal output from the voltage controlled oscillator is used. A step (a) for generating a second clock signal, and the first panel horizontal pulse generation unit outputs a horizontal output pulse group for the first panel using the second clock signal as a clock. A step (b), a step (c) for generating a third clock signal from the first clock signal, and a horizontal pulse generation for the second panel using the third clock signal as a clock. Parts is a step (d) for outputting a horizontal system output pulse group for the second panel.

  According to this method, upon receipt of the same clock signal, the first panel horizontal pulse generation unit and the second panel horizontal pulse generation unit can simultaneously output the horizontal output pulse groups for the respective panels. Therefore, even a panel with a different driving method or a panel with a different number of pixels can be driven simultaneously.

  The display panel control circuit receives a comparison result by the phase comparator for comparing the phase of the output signal of the horizontal pulse generating unit for the first panel and the horizontal synchronizing signal, and a PLL loop as a result of the comparison by the phase comparator. A smoother that feeds back a phase error voltage to a voltage controlled oscillator in the previous period. The step of resetting the first counter at a predetermined timing is the same as the timing of resetting the first counter. A step of resetting the second counter at the timing, so that the PLL operates so that the reset timing of the first counter coincides with the timing of the externally input horizontal synchronization signal HD. The reset timing of the counter of the horizontal pulse generator for panel 2 also matches the timing of the horizontal sync signal. Rukoto can, it is possible to suppress the disturbance of the display.

  According to the present invention, at different VCO output frequencies, for example, a first panel having a one-pixel sequential transfer method and a second panel having a three-pixel simultaneous transfer method are alternately used. However, the display panel control circuit that drives both of them simultaneously can be realized.

  Further, according to the present invention, a plurality of display panels can be displayed at the same time, and an increase in circuit area is small, so that a display panel control circuit that is advantageous when there is a size limitation can be realized.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments that specifically show the best mode for carrying out the present invention will be described below with reference to the drawings.

(Embodiment)
A liquid crystal display control circuit (display panel control circuit) according to an embodiment of the present invention will be described with reference to FIGS. The liquid crystal display control circuit of this embodiment is used for AV equipment such as a digital video camera and a digital camera provided with two liquid crystal panels.

  FIG. 1 is a block circuit diagram showing a configuration of a liquid crystal display control circuit according to an embodiment of the present invention.

  As shown in the figure, the liquid crystal display control circuit of this embodiment changes the oscillation frequency according to the control voltage, and outputs a clock signal VCOCLK having an oscillation frequency n times the frequency of the reference input signal in the phase locked state. A voltage controlled oscillator (hereinafter referred to as VCO) 100, a first horizontal pulse generating unit 200 for a panel having a counter that counts a clock signal VCOCLK and is reset at a predetermined frequency division ratio, and a frequency divider, A second panel horizontal pulse generating section 500 having a counter that is reset at the same timing as the clock signal VCOCLK is counted and the counter of the first panel horizontal pulse generating section 200 is reset; The output signal of the panel horizontal pulse generator 200 is counted as the clock signal VCLK and input to the terminal 20. The first panel and the second panel share vertical pulse generator 600 having a counter that is reset in synchronization with the vertical synchronization signal VD, and the output signal PLL of the first panel horizontal pulse generator 200. A phase comparator 300 that compares the phases of RESET and the horizontal synchronization signal HD input to the terminal 10, and a smoother (hereinafter referred to as LPF) that receives the output of the phase comparator 300 and feeds back a phase error voltage to the VCO 100 as a PLL loop. 400). Note that the clock signal VCLK and the PLL RESET, which are output signals of the first panel horizontal pulse generating unit 200, may be different signals or the same signal.

  The first panel horizontal pulse generator 200 sends the first panel horizontal output pulse group to the output terminal 25, and the second panel horizontal pulse generator 500 generates the second panel horizontal pulse. The system output pulse group is sent to the output terminal 45. The vertical pulse generating unit 600 shared by the first panel and the second panel sends the first panel vertical output pulse group to the first panel vertical output group terminal 40 to be used for the second panel. The vertical output pulse group is sent to the second panel vertical output group terminal 60, respectively. Here, the horizontal output pulse group for the first panel includes various output pulses and a horizontal shift clock necessary for driving the first panel. The second panel horizontal output pulse group includes various output pulses and a horizontal shift clock necessary for driving the second panel.

  In the liquid crystal display control circuit of the present embodiment, the signal to be compared in the phase comparator in the PLL loop and the signal for resetting the counter of the second panel horizontal pulse generator 500 are set as the same signal PLL RESET. However, it may be an individual signal. The counter in the first panel horizontal pulse generating unit 200 needs to operate at least for a period of 64 μsec in one horizontal period in order to generate a phase-compared signal PLL RESET for phase comparison with the horizontal synchronizing signal HD. The counter in the second panel horizontal pulse generating unit 500 only needs to be able to count the time until horizontal blanking at most, so the scale may be smaller than the counter in the first panel horizontal pulse generating unit 200. .

  The vertical pulse generator 600 outputs both the output pulse group for the first panel and the output pulse group for the second panel. This is because even if the panel has a different number of pixels and different driving methods, the pulse group in the vertical direction becomes a timing output pulse group with a period of one horizontal period, so a common signal is branched and output to both panels. This is because it can be done.

  Next, each component will be described with specific examples of the liquid crystal display control circuit. FIG. 2 is a block circuit diagram showing a specific configuration example of the liquid crystal display control circuit of the present embodiment. In the drawing, a one-pixel sequential transfer type panel is shown as an example of the first panel, and a three-pixel simultaneous transfer type panel is shown as an example of the second panel. In the case of a digital video camera, one of the first panel and the second panel is used for a viewfinder, and the other is used as a liquid crystal monitor for image confirmation.

  As shown in FIG. 2, the horizontal panel pulse generator 200 for the first panel includes a 1/6 divider (1 / N divider) 210, an H counter (1) 220, and a first panel use. A horizontal shift clock generator 230.

  In the first panel horizontal pulse generator 200, the signal HCLK1 obtained by dividing the VCOCLK1 output signal of the VCO 100 by 1/6 by the 1/6 divider 210 is used as the clock signal of the H counter (1) 220. Yes. The signal HCLK1 is input to the first panel horizontal shift clock generator 230. Among the plurality of outputs of the H counter (1) 220, the signal PLL RESET is supplied to the phase comparator 300 and the second panel horizontal pulse generation unit 500, and the first panel horizontal output group among the plurality of outputs. Is sent to the horizontal output group terminal 30 for the first panel, and the output signal VCLK of the plurality of outputs is supplied to the vertical pulse generating unit 600.

  The first panel horizontal shift clock generator 230 receives a 1/2 frequency divider 231 using HCLK1 as a clock input and a VCOCLK1 output signal of the VCO 100 as a clock input, and outputs the 1/2 frequency divider 231 output. It has a shift register 232 for receiving, and a switch unit 233 for switching the output of the shift register 232 between the ODD line and the EVEN line of the liquid crystal panel in which pixels are delta arranged. From the first panel horizontal shift clock output terminal 35, the first panel three-phase horizontal shift clocks CPH1, CPH2, and CPH3, which are output signals of the switch section 233, are output to the outside of the circuit. The first panel horizontal shift clock generator 230 is the same as the first panel horizontal shift clock generator 230 of the conventional example. The first panel horizontal output group terminal 30 and the first panel horizontal shift clock output terminal 35 shown in FIG. 2 correspond to the output terminal 25 shown in FIG.

  The second panel horizontal pulse generator 500 includes a 1/5 frequency divider (1 / M frequency divider) 510, an H counter (2) 520, and a second panel horizontal shift clock generator 530. have.

  The second panel horizontal shift clock generating unit 530 includes a 1/2 frequency divider 531, an inverter 534, a D-FF 532, and a switch unit 533.

  In second panel horizontal pulse generating section 500, 1/5 frequency divider 510 divides VCOCLK1, which is an output signal of VCO 100, by one fifth, and outputs signal HCLK2. PLL reset, which is the output of H counter (1) 220, is also input to 1/5 frequency divider 510. Further, the signal HCLK2 becomes a clock signal of the H counter (2) and also becomes a clock signal of the ½ frequency divider 531 in the second panel horizontal shift clock generating unit 530. This HCLK2 is input via an inverter 534 to a clock input terminal of a D-FF 532 having an output of the 1/2 frequency divider 531 as a D input. Both outputs of the 1/2 frequency divider 531 and the D-FF 532 are input to the switch unit 533 that switches between the ODD line and the EVEN line of the delta-arranged liquid crystal panel, and the switch unit 533 is for the second panel. The horizontal shift clocks CKH1 and CKH2 of the phase are output to the second panel horizontal shift clock output terminal 55. The horizontal shift clocks CKH1 and CKH2 are synchronized with the horizontal synchronization signal HD. Further, the H counter (2) 520 receives the PLL RESET in addition to the above-described HCLK2, and outputs the second panel horizontal output synchronized with the horizontal synchronization signal HD to the second panel horizontal output group terminal 50. Output. The second panel horizontal output group terminal 50 and the second panel horizontal shift clock output terminal 55 shown in FIG. 2 correspond to the output terminal 45 shown in FIG.

  Here, the liquid crystal display control circuit of the present embodiment is different from the conventional liquid crystal display control circuit in that the clocks output from the 1/2 divider 231 and the 1/2 divider 531, that is, for the first panel. Two reference signals (HCLK1 and HCLK2) for generating the horizontal shift clock and the horizontal shift clock for the second panel are simultaneously output. On the other hand, in the conventional example, HCLK1 is input to the 1/2 frequency divider 1231 (see FIG. 5) in common for the first panel and the second panel. Since the output of the VCO 1100 is switched between the VCOCLK1 and the VCOCLK2 by the selection signal SEL in the case of the first panel display and the case of the second panel display, the HCLK1 has the first panel display and the second panel display. The frequency was different. For this reason, in the conventional example, even though the first panel and the second panel can be displayed alternately, they cannot be displayed simultaneously.

  In the embodiment of the present invention, the reference of HCLK1 which is the reference signal of the first panel horizontal shift clock and the reference of the second panel horizontal shift clock from the single signal VCOCLK1 without switching the system clock which is the output of the VCO. A signal HCLK2 is generated. Therefore, it is possible to output simultaneously with the second panel horizontal shift clocks CKH1 and CKH2 and the first panel horizontal shift clocks CPH1, CPH2 and CPH3. Panels can be displayed simultaneously.

  The reference signal HCLK1 of the first panel horizontal shift clock in the conventional example and the reference signal HCLK1 of the first panel horizontal shift clock in the present embodiment are the same, but the second signal in the conventional example is the second. The panel horizontal shift clock reference signal HCLK1 and the second panel horizontal shift clock reference signal HCLK2 in this embodiment have substantially the same frequency but are not the same signal.

  The circuit configuration of the shift register 232 included in the first panel horizontal shift clock generator 230 is the same as that of the conventional shift register 1232 shown in FIG. A circuit for generating CKHO and CKHE included in the second panel horizontal shift clock generating unit 530 is the same as the conventional circuit shown in FIG. The inverter 5534 is replaced with an inverter 534, and the D-FF 1532 is replaced with a D-FF 532.

  FIG. 3 is a diagram illustrating operation waveforms of the second panel horizontal shift clock and the like in the liquid crystal display control circuit of the present embodiment. As shown in the figure, a signal obtained by dividing HCLK2 obtained by dividing VCOCLK1 by 1/5 is CKHO, and a signal having a 90-degree phase delay of CKHO is CKHE. The Hi period of CKHO or CKHE corresponds to 3 pixels in the second panel. In the example of this embodiment, the value of M of the 1 / M frequency divider is 5 in order to obtain the signal HCLK2 for the second panel from VCOCLK1 determined by the pixel period of the first panel. As an example of a specific panel, when the first panel is a one-pixel sequential transfer method of 480 pixels and the second panel is a three-pixel simultaneous transfer method of 521 pixels, both panels are set with N = 6 and M = 5. In both cases, it is possible to set the roundness to approximately 1.

  Also, as shown in FIG. 2, the vertical pulse generator 600 has a V counter (1) 610 to which VCLK is inputted as a clock input and a vertical synchronizing signal VD inputted to the terminal 20 is inputted, and a V counter (1). Inversion processing units 620 and 630 for inverting each output of 610 with respect to a signal that needs to be inverted. An output signal group from the inversion processing unit 620 is output to the first panel vertical output group terminal 40, and an output signal group from the inversion processing unit 630 is output to the second panel vertical output group terminal 60. Yes. The configuration of the vertical pulse generator 600 is the same as that of a conventional liquid crystal display control circuit.

  As described above, according to the liquid crystal display control circuit of the present embodiment, it is possible to simultaneously drive a plurality of panels having different numbers of pixels or driving methods without providing individual control circuits. That is, since two or more panels can be driven by one VCO, a control circuit can be configured by one LSI, and an increase in circuit area can be suppressed. Therefore, if the liquid crystal display control circuit of this embodiment is used for a digital video camera or a digital camera, it is possible to perform face-to-face shooting in which a subject is shot while checking its own video.

  In the description of the present embodiment, an example in which a one-pixel sequential transfer-type panel and a three-pixel simultaneous transfer-type panel are simultaneously driven has been shown. However, the liquid crystal display control circuit of the present embodiment has other drive schemes. Even if it is a panel, a several panel can be driven simultaneously. Further, even when the first panel and the second panel have the same transfer method and only the number of pixels is different, both panels can be driven simultaneously. Therefore, the range of selection of the panel provided in the AV device is widened, and for example, it is possible to reduce the manufacturing cost by using a low-cost panel. Further, the liquid crystal display control circuit of the present embodiment can drive a stripe panel that does not employ a delta arrangement. In that case, the switch unit 233 and the switch unit 533 are not necessary. Similarly, the liquid crystal display control circuit of this embodiment can drive a panel driven by a method other than line inversion driving. In this case, the inversion processing units 620 and 630 are not necessary.

  In the above description, an example in which N of the 1 / N frequency divider 210 is 6 and M of the 1 / M frequency divider is 5 has been described, but N and M may be appropriately changed according to the panel. However, when the first panel and the second panel are panels having different numbers of pixels or panels having different driving methods, N and M are different from each other in order to set the clock cycle of the reference signal of the horizontal system output different from each other. Must be set to a value. In addition to this, if the user can change the frequency dividing ratio of these frequency dividers, the degree of freedom for selecting a panel is further increased when the user manufactures AV equipment.

  Further, if the liquid crystal display control circuit of the present invention is used, three or more display panels can be driven simultaneously. In this case, horizontal output pulse generating units are provided as many as the number of display panels, and reference signals for the respective panels are generated in the horizontal output pulse generating units from the VCO output VCOCLK1, and an H counter is used as a clock. What is necessary is just to provide.

  The liquid crystal display control circuit of the present invention can be used for AV equipment such as a digital video camera equipped with a liquid crystal panel for monitor (first panel) and a liquid crystal panel for EVF (electric view finder) (second panel). it can.

It is a block circuit diagram which shows the structure of the liquid crystal display control circuit which concerns on embodiment of this invention. It is a block circuit diagram which shows the specific structural example of the liquid crystal display control circuit which concerns on embodiment of this invention. It is a figure which shows operation waveforms, such as a 2nd panel horizontal shift clock, in the liquid crystal display control circuit which concerns on embodiment of this invention. It is a block circuit diagram which shows the structure of the control circuit of the liquid crystal panel display which concerns on a prior art example. It is a block circuit diagram which shows the specific structure of the control circuit of the liquid crystal panel display which concerns on a prior art example. It is a circuit diagram which shows a part of structure of the conventional display panel control circuit. In the conventional display panel control circuit, it is a circuit diagram which shows the specific structural example of the shift register which is a component of the 1st panel horizontal shift clock preparation part. It is a wave form diagram which shows the change of the horizontal shift clock for 1st panels and 2nd panels output from the conventional display panel control circuit. In the conventional display panel control circuit, it is a wave form diagram which shows the horizontal shift clock for ODD lines and EVEN lines of the 1st panel. In the conventional display panel control circuit, it is a wave form diagram which shows the horizontal shift clock for the ODD line and EVEN line of a 2nd panel.

Explanation of symbols

10, 20 Terminals 25, 45 Output terminal 30 First panel horizontal output group terminal 35 First panel horizontal shift clock output terminal 40 First panel vertical output group terminal 50 Second panel horizontal system Output group terminal 55 Second panel horizontal shift clock output terminal 60 Second panel vertical output group terminal 100 Voltage controlled oscillator (VCO)
200 First panel horizontal pulse generator 210 1 / N frequency divider 220 H counter (1)
230 First panel horizontal shift clock generator 231, 531 ½ frequency divider 232 Shift register 233, 533 Switch unit 300 Phase comparator 400 Smoother (LPF)
500 Second panel horizontal pulse generator 510 1 / M frequency divider 520 H counter (2)
530 Second panel horizontal shift clock generator 532 D-FF
534 Inverter 600 Vertical system pulse generator 610 V counter (1)
620, 630 Inversion processing units CKH1, CKH2 Second panel horizontal shift clocks CPH1, CPH2, CPH3 First panel horizontal shift clocks

Claims (7)

A display panel control circuit for controlling display of the first panel and the second panel,
A voltage controlled oscillator that outputs a clock signal;
A first panel horizontal pulse generation unit that has a first counter that counts the clock signal and is reset at a first frequency division ratio, and outputs a horizontal output pulse group for the first panel. When,
A second counter that counts the clock signal and has a second counter that is reset at the same timing as the first counter is reset, and outputs a horizontal output pulse group for the second panel; A display panel control circuit comprising: a horizontal pulse generator for a panel.   A vertical counter for the first panel and the second panel has a third counter that counts the output signal of the horizontal pulse generator for the first panel as a clock and is reset by a vertical synchronization signal. The display panel control circuit according to claim 1, further comprising a vertical pulse generation unit that outputs an output pulse group. A phase comparator that compares the phase of the output signal of the horizontal pulse generator for the first panel and the phase of the horizontal synchronization signal;
The display panel control circuit according to claim 1, further comprising: a smoother that receives a result of the comparison by the phase comparator and feeds back a phase error voltage to a voltage controlled oscillator as a PLL loop. The first panel horizontal pulse generating unit further includes a first frequency divider that generates a clock of the first counter by dividing the clock signal by 1 / N (N is a positive integer). Have
The second panel horizontal pulse generating unit divides the clock signal by 1 / M (M is a positive integer different from N) to generate a second counter clock for generating the second counter clock. The display panel control circuit according to claim 1, further comprising a display.   The display panel control circuit according to claim 4, wherein a PLL reset signal output from the first counter is input to the second frequency divider and the second counter. A display panel control circuit including a voltage-controlled oscillator, a first panel horizontal pulse generator having a first counter, and a second panel horizontal pulse generator having a second counter is used. A display panel control method for simultaneously controlling display of the first panel and the second panel,
Generating a second clock signal from the first clock signal output from the voltage controlled oscillator;
A step (b) in which the first panel horizontal pulse generating section outputs the first panel horizontal output pulse group using the second clock signal as a clock;
Generating a third clock signal from the first clock signal (c);
The second panel horizontal pulse generating unit outputs the second panel horizontal output pulse group using the third clock signal as a clock (d). Display panel control method. The display panel control circuit receives a comparison result by the phase comparator for comparing the phase of the output signal of the horizontal pulse generating unit for the first panel and the horizontal synchronizing signal, and a PLL loop as a result of the comparison by the phase comparator And a smoother that feeds back the phase error voltage to the previous voltage controlled oscillator.
Resetting the first counter at a predetermined timing;
The display panel control method according to claim 6, further comprising a step of resetting the second counter at the same timing as the timing at which the first counter is reset.

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