JPS62150970A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To decrease a quantization-error of phase as for as possible and thereby to make the titled circuit similar to an analog synchronizing circuit by generating plural clocks whose phases are delayed in order from an original clock within the period of one clocking, and stopping and restarting the supplying of clock to a counter by means of an internal signal and an external signal. CONSTITUTION:When one cycle of a horizontal synchronization ends and an internal horizontal synchronizing signal HS is generated, a signal F falls, and later, when a clock C rises, a flip-flop 54b fetches it and a Q-output turns to L and H respectively, and further an AND gate 56b is closed to stop the transmission of the clock C and to release the cleaning of other flip-flops. The restarting of the said transmission of the clock C is executed when the signal F turns to H and an input clock rises continually. At this time, a clock which is selected at this time is such one that rises the earliest after the rising of the signal F. Thereafter, the above mentioned process is repeated, and the external synchronization and the internal synchronization are made aligned in phase maximally possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital phase synchronization circuit, and is intended to reduce phase shift as much as possible.

[Conventional technology]

Displaying the internal screen (computer screen) and the on-air or VTR TV screen overlappingly on the CRT display (CRT display) on a computer (PC)
superimposing) is being performed. In this case, it is necessary to synchronize both screens, but since the TV screen cannot be adjusted, this can be done by synchronizing the computer screen with the TV screen.

To explain this with reference to FIG. 4, 10 is a video signal output terminal of a television receiver or video tape recorder, and the video (TV) signal from this terminal is sent to the sync separation circuit 1 on the computer screen side.
2 and the selection gate 14. Horizontal synchronization signal EH and vertical synchronization signal EV are separated in circuit 12 and input to phase comparison circuits 16 and 18. 20 is a clock oscillator, and the clock CLK output by this oscillator becomes the dot clock of the CRT display screen, and is counted to have the same period (or shorter) as the horizontal synchronization signal H3 and vertical synchronization signal EV of the television signal. A horizontal synchronizing signal H3 and a vertical synchronizing signal VS are generated. 22 receives the clock CLK via the gate 24, and receives the horizontal and vertical synchronizing signals H3, V
This counter outputs S and also generates an address for accessing the screen memory (VRAM, video ram) 30. The memory 30 stores the computer screen to be displayed on the monitor (CRT display), and the counter 22
When the data is read out at the address where the dot occurs, data for multiple dots is output simultaneously, which is stored in the shift register 28, and is sequentially output (parallel/serial converted) with the clock CLK to become an image signal (for details, H3 and VS are added to this). The clock CLK is also the central processing unit CP.
The image data is also supplied to the CPU U, etc., and the CPU writes image data into the memory 30.

The gate 14 selects and outputs either the video signal from the terminal 10 or the video signal from the shift register 28 in response to a control signal (not shown). For example, to superimpose the computer screen 34 on the television screen 32 as shown in FIG. , the signal from point P2 to the end fiE may be a television signal, but the gate 14 performs this switching.

Synchronization between the TV screen and the computer screen is performed as follows. That is, the internal horizontal synchronizing signal H3 generated on the personal computer side is the external horizontal synchronizing signal EH separated from the TV signal.
If this occurs earlier, the phase comparison circuit 16 produces an output which enters the clock stop gate 24 through the OR gate 26 and inhibits the input of the clock CLK to the counter 22.The phase comparison circuit is, for example, a flip-flop; H3 is reset with cents, F, and V, and its Q output enters the clock stop gate 24, which is an AND gate.
The above operations are performed. When the external horizontal synchronization signal EH is input, the phase comparator circuit 16 releases the clock stop, and the counter 22 starts counting the clock CLK.

Since the period of internal horizontal synchronization signal H3 generated on the personal computer side is slightly shorter than the period of external horizontal synchronization signal EH,
3 arrives slightly earlier than EH, so a clock stop is effected and the clock stop is released when signal EH arrives. The same applies below, and thus the internal horizontal synchronization signal H3
is synchronized to external horizontal synchronization signal EH. Internal vertical synchronization signal VS is similarly synchronized with external vertical synchronization signal EV.

[Problem that the invention seeks to solve]

Synchronization of the horizontal/vertical synchronizing signals in the circuit of FIG. 4 is performed digitally, and therefore there is a quantization error.

That is, at the i-th clock CLK, the counter 22 generates the horizontal synchronization pulse H3, which causes the clock stop gate 2
4 is turned off and the clock supply is stopped, the external horizontal synchronizing signal EH is then turned off within one period of the clock CLK.
When the clock CL is input, the gate 24 is turned on and the clock CL is input.
Since K is supplied to the counter 22, it is the same as if there was no clock interruption (there are cases where a part of the clock pulse is missing and the counter malfunctions, but this will be ignored here), and within the above period. Although there is no EH input, if EH is input within the next cycle, only one clock will be missing, and this will apply hereafter, so synchronization of EH and H3 is only possible at an integral multiple of the clock cycle.

This results in a superimposed screen on a CRT display having each scanning line on the computer screen fluctuating from side to side with the width of one clock cycle (causing jitter), degrading the image quality. The present invention aims to improve these points and provide a synchronization circuit which is digital phase synchronization but has as little phase error as possible.

[Means for solving problems]

The present invention generates an internal signal when a counter counts a clock and reaches a constant value, stops clock supply to the counter with the internal signal, restarts clock supply with an external signal,
In this way, in a phase-locked circuit in a device that generates an internal signal synchronized with an external signal, an n-wave generation circuit that generates multiple clocks whose phases are sequentially delayed within the range of the clock cycle, and an internal signal generation circuit are used. A control signal that takes one of high and low levels and the other by external signal generation and the plurality of clocks are input, and when the control signal switches to the other level, the clock that appears earliest is output. The present invention is characterized in that it includes a selection circuit for one wave out of n waves that continues the state until the control signal changes to one level, and the output clock of the selection circuit is supplied to the counter.

[Effect]

By creating multiple clocks whose phases are sequentially delayed within the clock period from the original clock, and not only stopping and restarting the clock supply to the counter using internal and external signals, but also switching the clocks, This enables phase synchronization that allows the phases to match fairly well.

〔Example〕

An outline of the circuit of the present invention is shown in FIG. In the present invention, this first
As shown in the figure (al), the output clock CLK of the oscillator 20
(indicated by A here) is received by the n-wave generation circuit 42, and a clock B whose phase is slightly delayed from the output clock CLK is received by the n-wave generation circuit 42.
, C, D, old..., and selects the clock closest to the external horizontal synchronizing signal EH (the clock that appeared earliest after generation of EH) in the one-wave selection circuit 44 out of n waves, and outputs it. In this way, the larger n is, the more an internal synchronization signal that is in phase with the external synchronization signal can be obtained.

Specifically, the n-wave generation circuit 42 may be a tapped delay circuit 52 as shown in FIG. 1(b), and clocks B, C, and D whose phases are sequentially delayed from the tap.

You can get... These clocks B
.

C, D, ...... have the same period, waveform, etc. as the original clock A, and in this example, each delay time is also the same (B
is delayed by φ with respect to A, C is delayed by φ with respect to B, etc.

However, φ is selected as τ/n) where τ is the clock period. An example of this is shown in FIG. Of course, each delay time may be different, but the delay is made to be within the clock cycle, that is, even the most delayed clock occurs before the next clock of the original clock A occurs. Such n clocks B
The selection circuit 44 selects and outputs one of the output clocks (C, D, .
The counter 22, C is used as the output clock of the oscillation 820 in the figure.
It is supplied to the PU1 shift register 28, etc.

The constituent elements of the selection circuit 44 are shown in FIG. 1(C). As shown in the figure, this consists of a flip-flop 54 and an AND gate 56, which receives the signal F at its data input terminal, receives one of the output clocks of the n-wave generating circuit 42, B in this example, at its clock terminal, and has a clear terminal CLR. The output J from another flip-flop is input to , the Q output is input to the AND gate 56 together with the input clock B, and the output (2) becomes the set signal R of the other flip-flop. FIG. 3 shows details of the circuit shown in FIG. 1 fa) constructed using these components.

In FIG. 3, the n-wave generation circuit 42 generates four clocks B-D with the same delay time, and a flip-flop 54 and an AND gate 56 (a, b,
... is a subscript that distinguishes each other and may be omitted as appropriate)
will be established. Clock BD is input to the clock terminal of each flip-flop 54a to 54d, and the output R is collected by OR gates 58a to 58d and input to the clear terminal of other flip-flops. Also, and gates 56a to 56
The outputs of d are collected by an OR gate 60, and the output G of the gate 6o is used as the output clock of this circuit.

To explain the operation with reference to FIG. 2, when the signal F rises due to the arrival of the external horizontal synchronizing signal EH, the D
The terminal becomes H (high) level, and after that, when the input clock of the clock terminal rises to H, the H level of the data terminal is taken in, and the Q output becomes H1ζ output becomes L. Since the b output clears other flip-flops, the only flip-flop that can make such an output change is the flip-flop whose clock rises first after the rise of the signal F, and in the example of FIG. This is only the flip-flop 54b that receives clock C. Therefore, in this cycle, the clock C is the AND gate 56b.

The output clock G passes through the OR gate 60, and the other clocks B, D, and E pass through the AND gates 56a,
It is blocked by 56c and 56d and does not output.

The flip-flop 54b takes in data every clock cycle, and since the signal F remains rising until one horizontal synchronization period ends, the Q output continues to be H and the Q output to L, and other Keep flip-flops clear,
The output clock G is assumed to be the clock C.

When one cycle of horizontal synchronization ends and the internal horizontal synchronization signal H8 is generated, the signal F falls, and then when the clock C rises, the flip-flop 54b takes it in and outputs the Q output, making the Q output H. The AND gate 56b is closed to stop sending out the clock C and release the clearing of the other flip-flops.

Therefore, this circuit also serves as the clock stop gate 24 in FIG. Clock transmission is restarted when the signal F rises to H level and then the input clock rises, and the clock selected at this time is the clock that rose earlier than the rise of the signal F. Thereafter, this is repeated to achieve as much phase alignment as possible between external synchronization and internal synchronization.

When n = 4 as in this example, there is jitter within the range of 1/4 of one clock period, but in a display system where one horizontal scanning line is represented by 512 or 1024 dots, the fluctuation of 1/4 dot width is It becomes almost unnoticeable.

Of course, n may be set to 8, but the circuit will be more complex and faster. In addition, this circuit is not limited to synchronizing external/internal synchronization signals of the superimpose device, but also synchronizes internal signals (corresponding to internal horizontal synchronizing signal H3) in other devices with external signals (corresponding to external horizontal synchronizing signal EH). to synchronize. It can also be used in digital synchronization circuits.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the phase quantization error in a digital synchronization circuit as much as possible and make it similar to an analog synchronization circuit. It has the advantage that there is no inconvenience in adjustment, and it can be easily manufactured using logic gate ICs such as gate arrays.

[Brief explanation of drawings]

Fig. 1 is a schematic explanatory diagram of the present invention, Fig. 2 is a waveform diagram for explaining operation, Fig. 3 is a diagram showing details of Fig. 1, Fig. 4 is a circuit diagram of the main part of superimposition, and Fig. 5 is a diagram showing the details of Fig. 1. The figure is an explanatory diagram of the superimpose screen. In the drawing, 22 is a counter, H3 is an internal signal, EH is an external signal, B, C, . . . are multiple clocks whose phase is delayed, F is a control signal, 42 is an n-wave generation circuit, 44 is n
This is a one-wave selection circuit.

Claims (1)

[Claims] When a counter counts a clock and reaches a constant value, an internal signal is generated, and the internal signal stops the clock supply to the counter, and the external signal restarts the clock supply. In a phase synchronized circuit in a device that generates synchronized internal signals, a plurality of clocks whose phases are sequentially delayed within one clock period from the clock are generated.
A wave generation circuit, a control signal that takes one of high and low levels by internal signal generation and the other by external signal generation, and a control signal that receives the plurality of clocks and switches to the other level when the control signal switches to the other level. It is characterized by comprising a one wave selection circuit out of n waves which outputs a clock that appears earlier and continues this state until the control signal changes to one level, and supplies the output clock of the selection circuit to the counter. phase-locked circuit.