JP2571924B2 - Interface circuit for display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit of a flat display device using a liquid crystal, an EL, a plasma, an LED, etc., and particularly to a CRT display device frequently used in personal computers and the like. Using only separate video signals, it generates display data and timing signals necessary to operate a flat display device, and can supply a light, thin and short display terminal by replacing a CRT display device with a flat display device. Related to the interface circuit.

[Summary of the Invention]

The present invention uses a display data synchronizing signal of a CRT display device, and stores real-time processing of input display data without storing the display data in a frame buffer memory (RAM). It has an interface function that converts color data into parallel 4-bit display data and parallel 8-bit display data, and enables color display with the same drive circuit configuration as before. The present invention relates to an interface circuit of a versatile flat display device in which the parallel method is selected and obtained.

[Conventional technology]

Since flat display devices such as liquid crystals have characteristics of thinness, low voltage, and low power consumption, they have recently been put to practical use as display terminals for personal computers, word processors, and the like due to large dot matrix pulses. Today, liquid crystal interface circuits that can be directly connected to CRT control circuits have been developed for use as display terminals of portable personal computers instead of CRTs. However, the interface circuit of the conventional liquid crystal display device is designed with the idea of driving the liquid crystal panel even during the blinking period of the CRT display. Therefore, the display data is prepared by preparing a frame buffer memory, writing the display data into the frame buffer memory once, and then reading out the display data sequentially to display the display data. Further, since the conventional interface circuit is dedicated to monochrome display, the amount of display information is insufficient when displaying graphics.

That is, red, red,
Since one or two of the green and blue color display data is used to simply display ON / OFF, the attractiveness of the display device is insufficient compared to the CRT display device. However, in recent years, a color filter technology for coloring the surface of a transparent electrode of a display panel with a color has been established, and a non-linear filter such as a TFT (thin film transistor) and a MIM, MSI (see Japanese Patent Application Laid-Open No. 61-90192). Despite the development of the active element built-in type panel or the new type of liquid crystal panel having a storage function such as a smectic liquid crystal, the interface of the color liquid crystal display device has not been developed yet. for that reason,
The interface circuit of the monochrome flat display device requiring the frame buffer memory needs to be provided for red, green, and blue.

[Problems to be solved by the invention]

As described above, the interface circuit of the conventional flat display device needs to prepare a frame buffer memory (RAM) as an external circuit and write and read data under the management of the interface circuit. Therefore, the cost of the circuit configuration is high, the configuration is complicated, and it has been difficult to integrate the display terminals into a small and inexpensive display terminal. Since the interface circuit is dedicated to monochrome display, in order to configure the interface circuit of the color flat display device, it is necessary to prepare the three interface circuits for monochrome display as one set. There were high prices and complexity of construction.

Furthermore, since the current monochrome 640 × 400 dot flat display drive circuit is input using 4-bit parallel data, the transfer speed for color display of 640 × 400 dots is three times that of monochrome display. Therefore, there is a problem that the flat display driving circuit cannot be used unless the transfer speed is improved.

[Means for solving the problem]

The present invention has been made in order to solve the above-described problems, and has a function of directly interfacing display data and timig signals to a flat display device by real-time processing of a video signal for a CRT display, and has a function of parallel display data. Has a parallel bit selection function of switching the data to 4 bits or 8 bits. When a performance higher than the maximum transfer speed of the drive circuit is required, 8-bit parallel data is selected to reduce the transfer speed. With such a configuration, a versatile interface circuit is provided.

〔Example〕

 Next, an embodiment of the present invention will be described.

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a timing chart for supplementing the description of the operation of FIG.

In FIG. 1, Hsyc is a horizontal synchronization signal, Vsyc is a vertical synchronization signal, CK is a dot clock signal, RD, GD, and BD are red,
These are green and blue display data. These Hsyc, Vsyc, CK, R
D, GD, and BD are equivalent to interface signals to the CRT display device. 1 is an X-axis display position adjustment circuit that counts the dot clock CK and adjusts the display position in the X-axis direction. 4 is a Y-axis display position adjustment circuit that counts the horizontal synchronization signal Hsyc and adjusts the display position in the Y-axis direction. , 3 aND circuit which receives the output dot clock CK of the X-axis and Y-axis display position adjusting circuit 1, 4, 6 to the frequency of the clock signal P ₁ 1/8 minute, which is the output of the aND circuit 3 1/8 frequency dividing circuit for further dividing the output P ₂ of the 1/8 frequency dividing circuit 6
Frequency dividing circuit for generating a reset signal P ₃ for resetting the X-axis display position adjusting circuit 1, 10, 11, 12 red, green, the shift register and the shift register for shifting the blue display data output Are each a S / P conversion circuit including a latch circuit for temporarily latching the S / P.

21 wherein, by the first pulse signal P _2, a set-reset flip-flop circuit for setting. 16 and 17 when the output T ₂ of the Y-axis display position adjusting circuit 4 rises to "H", the a D-type flip-flop circuits and NOR circuit for generating a set pulse signal P _9. 18
The flip-flop circuit for generating a set output by the set pulse signal P _9, 47, 48 is a D-type flip-flop circuit for delaying the output of the flip-flop circuit 18. The D-type flip-flop circuit 48
Output FRM is a frame signal. Reference numeral 20 denotes a flip-flop circuit for dividing the signal of the frame signal FRM by 1/2. The output of the flip-flop circuit 20 is a liquid crystal AC drive signal M. LK is a latch signal of a latch circuit built in the X-axis drive circuit for the display data transferred to the X-axis drive circuit. 27 is a flip-flop circuit for 1/2 dividing the clock pulse signal P ₁₀ of the AND circuit 22.
Reference numeral 28 denotes a quaternary ring counter using the output of the flip-flop circuit 27 as a clock signal. 54, 55, 56 color display data of red, green, the data of the blue, an exclusive OR circuit for inverting by turning ON the switch SW _1.
Reference numerals 57 and 58 denote a display data switching circuit of the upper drive circuit and a display data switching circuit of the lower drive circuit for outputting display data in a time-division manner in 4-bit parallel. Reference numerals 60 and 59 denote a display data switching circuit of the upper drive circuit and a display data switching circuit of the lower drive circuit for outputting display data in 8-bit parallel in a time-division manner. SW ₂ is the 4-bit or a selection switch for selecting whether to output to the drive circuit by 8-bit parallel output.

Next, the operation of the embodiment shown in FIG. 1 of the present invention will be described.

The X-axis display position adjustment circuit 1 starts counting the dot clock CK when the horizontal synchronizing signal Hsyc is input. The count value is to match the set value of the blanking period of the display data, the output T ₁ of the said X-axis display position adjusting circuit 1 rises to "H". The setting of the blanking period can be adjusted in units of one dot by an external setting means such as a digital switch.

When the vertical synchronization signal Vsyc is input, the Y-axis display position adjustment circuit 4 starts counting the horizontal synchronization signal Hsyc. The count value is to match the set value of the blanking period in the Y-axis direction of the display data, the output T ₂ of the said Y-axis display position adjusting circuit 4 rises to "H". The setting of the blanking period can be adjusted in units of one dot by an external setting means such as a digital switch as described above. When the outputs T ₁ and T _{2 of the} X-axis and Y-axis position adjustment circuits both rise to “H”, the display starts (home position),
From the AND circuit 3, the clock signal P ₁ is output. The clock signal P ₁ is inputted as a shift clock for the shift register built in the 1/8 frequency divider 6 and the S / P conversion circuit 10, 11, 12. The display data RD, GD, and BD are exclusive OR circuits 54, 5
It is inverted by 5,56 and shifted every shift clock.

1/8 output P ₂ of the first aspect of the division circuit 6 sets the flip-flop circuit 21. Therefore, the AND circuit 22 starts outputting the clock signal P _10.

When SW ₂ is OFF, the gate is O from the switching circuit 51, so that the frequency is divided by the flip-flop circuit 27 of the 分 frequency dividing circuit and input as a clock of the quaternary ring counter 28. The quaternary ring counter 28 uses the output of the NOR circuit 29 as data. Quaternary ring counter 28
The switching control signal P _5, P _6, generates P ₇ time division manner, the display by switching ON time division switching circuit 57, 58, 59, 60 data UD ₁ ~UD _4, LD ₁ ~LD _{4, UD 5 ~UD 8, LD} 5
~ LD ₈ is output in parallel. Further, the clock signal P
₁₀ is frequency-divided by 1/2 by the flip-flop circuit 23,
The shift clock signal SK of the parallel data is output. Flip-flop circuit 23, since the data of the quaternary ring counter 28 is reset by the signal inverted by the inverter 30, at 8 clock input of the clock signal P _10,
The shift clock signal SK of the parallel data is output for three clocks. The output P ₂ of the 1/8 frequency divider 6 is connected to the switching circuit 5
3, the gate is turned on, so the S / P conversion circuits 10, 11,
The latch signal becomes a latch signal of a latch circuit built in 12, and the shifted data is latched _every eight clock signals P1.

The outputs of the S / P conversion circuits 10, 11, 12 are R, G, B (red,
(Green, blue) are input alternately to the switching circuits 57 and 58 in 1-bit units. The switching circuit 57, the upper display data UD ₁ ~UD _4, the switching circuit 58 is output after being grouped under the display data LD ₁ ~LD _4.

The color display data RD, GD, BD are input to the switching circuits 57, 58 alternately from the first bit. Therefore, the display data is output in a time-division manner by the outputs P ₅ , P ₆ , and P _{7 of the} quaternary ring counter circuit 28, so that the switching circuit 57 outputs (R ₁ , B ₁ , G ₂ , R ₃ ) (B ₃ , G ₄ …)… output. The switching circuit 58, the 57 the same Tainmingu, the display data _{LD 1 ~LD 4, (G 1} , R 2,
B ₂ , G ₃ ) (R ₄ , B ₄ …). (☆ Note, the number indicates the bit number of the data.) The above is the method of transferring display data to the upper drive circuit and the lower drive circuit in 4-bit parallel.

Next, the case where the ON switch SW _2.
At this time, the mode becomes the 8-bit parallel output mode, the switching circuits 59 and 60 are selected, and becomes the active state.
And it outputs the upper display data UD ₁ ~UD ₈ and lower display data LD ₁ to Ld ₈ time division manner. The output P of the 1/8 frequency divider 6
₂ is frequency-divided by に よ っ て by the flip-flop circuit 52, and is input to the S / P conversion circuits 10, 11, and 12 as a latch signal via the switching circuit 53. Therefore, the S / P conversion circuits 10, 11, 1
2 latches 16-bit display data. On the other hand, the output P ₁₀ of the AND circuit 22, the flip-flop circuit 50 1/2
The frequency is divided, passed through the switching circuit 51, is divided by the flip-flop circuit 27 in the same manner as described above, the quaternary ring counter circuit 28 is operated, and the flip-flop circuit 23 outputs the shift clock SK of the display data. The switching circuits 59 and 60 alternately input the 16-bit display data of the S / P conversion circuits 10, 11, and 12 for each bit. The switching circuit 60 includes upper display data UD _{1 to} UD ₈ and a switching circuit 59.
Is output is grouped under the display data LD ₁ ~LD _8. Color display data RD, GD, B of S / P conversion circuits 10, 11, 12
D is input to the switching circuits 60 and 59 alternately from the first bit as described above. Therefore, the display data is output in a time-sharing manner by the outputs P ₅ , P ₆ , and P _{7 of the} quaternary ring counter circuit 28, so that the switching circuit 60
Is (R ₁ , B ₁ , G ₂ , R ₃ , B ₃ , G ₄ , R ₅ , B ₅ ), (G ₆ , R ₇ , B ₇ , G ₈ …)…
Produces the output of Further, the switching circuit 59 adds (G ₁ , R ₂ , B ₂ , B ₃ ,
R ₄ , B ₄ , G ₅ , R ₆ ), (B ₆ , G ₇ , R ₈ …).
(☆ Note, the number indicates the bit number of the data.) Next, the timing signal to the liquid crystal display device will be described.

When the output T _{2 of the} Y-axis display position adjustment circuit 4 rises to “H”, the output T ₂ is inverted by the inverter 5, and the set pulse P ₉ is generated by the D-type flip-flop circuit 16 and the NOR circuit 17.
The flip-flop circuit 18 is set.

The clock signal P ₂ of the 1/8 frequency dividing circuit 6 is counted by the frequency divider 7, after counting (for example, 700 counts) to display data of the X-axis direction is input, D-type flip-flop circuit 9 and the NOR circuit 8,
Generates reset signal P ₃ and adjusts X-axis display position adjustment circuit 1, 1/8
The frequency divider 6, the frequency divider 7, and the flip-flop circuit 18 are reset. The reset signal P _3, the X electrode driving circuit latch signal of the latch circuit built in the (X driver) LK and the shift clock YSCL in the shift register built in the Y electrode drive circuit (Y driver). The output of the flip-flop circuit 18 is delayed by D-type flip-flop circuits 47 and 48 to output a frame signal FRM,
It becomes the scanning start data of the Y electrode drive circuit (Y driver).

The frame signal FRM is frequency-divided by the 1/2 frequency divider circuit 20, generates an AC drive signal M so that the polarity of the drive voltage is inverted for each frame, and outputs the AC drive signal M to the X electrode and Y electrode drive circuits. Output.

Thus, as noted, by turning ON the switch SW _2, is 8-bit parallel mode, it is possible to select the 4-bit parallel mode by turned OFF. By turning ON the switch SW _1, the display data is inverted, N
The display becomes EGA, and when it is turned off, Posi display becomes possible.

In the timing chart of FIG. 2, (A) shows the X axis and Y
Shows the timing of the output T ₁ and T ₂ of the axis display position adjusting circuit. (B) the timing of the clock signal P ₁ and P _3,
(C) shows switching control signals P ₅ , P ₆ , P ₇ and display data
UD _{1 to} UD ₄ , LD _{1 to} LD ₄ timing, (D) shift clock which is a timing signal to the drive circuit of the liquid crystal display device
The timings of the CP, the clutch clock LK frame signal FRM, and the AC drive signal M are shown.

FIG. 3 shows an embodiment of an electrode configuration of a color liquid crystal panel when a color display is performed in the present invention.

In Figure 3, Y-axis electrode drive circuit 61 generates a scan drive signal, Y-axis electrodes Y _1, Y ₂ ... driving circuit for sequentially driving the Y _N, X electrode driving circuit 62 and 64, respectively This is a circuit in which X electrodes are separated into odd and even numbers by upper and lower connection terminals and driven. The X electrodes of the flat panel 63 are R, G, B (red, green, blue) from the left end by colored color filters.
Is colored. UD ₁ ~UD ₄ and LD ₁ to Ld ₄ is a 4-bit parallel data signals of two systems to the X electrode drive circuit 62, 64. As described above, UD ₁ ~UD ₄ and LD ₁ to Ld _4, from the left end _{(R 1, B 1, G} 2, R 3) inputs a signal _{(B 3, G 4 ...)} , LD 1 ~ L
D ₄ is the left end _{(G 1, G 2, B} 2, G 3) for inputting a signal _{(R 4, B 4 ...)} .

The coloring arrangement of the electrodes is not limited to this embodiment. FIG. 4 shows an example of a system configuration in the case of the 4-bit parallel mode.

In FIG. 4, a separate video signal from a personal computer 80 is input to an interface circuit 81. The interface circuit 81 includes the X electrode drive circuit 8
2, 84 and Y electrode drive circuit 85, timing signals, SK, LK, M, F
RM and display data UD ₁ ~UD _4, and outputs the LD ₁ ~LD _4, to drive the color panel 83. This allows a deeper understanding of the present invention.

〔The invention's effect〕

As described above, according to the present invention, a video signal of a CRT display device is used to perform real-time processing to convert display data and timing signals of a flat display such as a liquid crystal display device into a frame buffer. Does not require memory. Therefore, it has become possible to manufacture a small, low-cost display / display terminal by using a gate array IC. An interface circuit for color display, which did not exist conventionally, can be supplied, and can be directly substituted for a CRT display device, thereby increasing the appeal of the display device.
Since the parallel display data bits can be easily selected to be 4 bits or 8 bits, it is possible to select either a 4-bit or 8-bit parallel drive circuit within the allowable range of the transfer speed of the drive circuit. Versatility has been greatly increased.

For this reason, a 4-bit drive circuit could not be used conventionally, but an 8-bit configuration using two parallel circuits has become available. Since a drive circuit having the same configuration as that of the related art can be used as it is, there is no need to develop a drive circuit dedicated to color. And so on. The present invention relates to an active matrix having a built-in non-linear resistance element such as MSI and MIM, and an active matrix having a built-in switching transistor like a TFT panel.
A ferroelectric liquid crystal panel having a memory property such as a matrix or a smectic liquid crystal panel is particularly effective for these new liquid crystal panels having a memory property in pixels even during a blanking period. Although the present invention has been described only for switching between 4 bits and 8 bits, the present invention is also applied to other bits, for example, switching from 8 bits to 16 bits, and is not limited to this.

Of course, the present invention can be applied to elements other than the liquid crystal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIGS. 1 to 3 are diagrams showing the timing of FIG. 1, FIG. 3 is an electrode configuration diagram of one embodiment of a color liquid crystal panel, and FIG. 4 is a block diagram showing a system configuration. 1 X-axis display position adjustment circuit 2 Y-axis display position adjustment circuit 3 AND circuit 6 1/8 frequency divider 7 frequency divider 9,16,47,48 D-type flip-flop Flip-flop circuits 10, 11, 12, S / P conversion circuits 18, 21, 23, 27, 50, 52 Flip-flop circuits 28 Quaternary ring counters 51, 52, 57, 58, 59, 60 Switching circuit SW ₁ , SW ₂ … Switch

Claims (1)

(57) [Claims] An interface circuit of a display device for receiving a video signal and generating a display data signal and a timing signal for operating a display signal, for converting color display data of R, G, and B into a parallel signal. And S / P conversion circuits (10, 11, 12), and outputs of the S / P conversion circuits R, G, B
A first switching circuit group (57, 58) for performing time-series switching of the color-mixed data with a first parallel bit; A second switching circuit group (59, 60) for chronologically switching data with a second parallel bit; and a parallel switching circuit for selecting an operation of the first and second switch circuit groups. An interface circuit for a display device having a bit selection function (SW ₂ ) and outputting the first or second parallel bit selected by the parallel bit selection function.