JPH0551918B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] This invention relates to interface circuits for flat displays such as liquid crystal displays, plasma displays, and EL display devices, and in particular to interface circuits for flat displays such as liquid crystal display devices, plasma displays, and EL display devices, and in particular, for interface circuits for only separate video signals such as CRT display devices that are often used in personal computers. By using this technology to generate display data and timing signals necessary to operate liquid crystal display devices, and by replacing CRT display devices with flat display devices such as liquid crystal display devices, it has become possible to supply display terminals that are light, thin, short, and small. This relates to interface circuits. [Summary of the Invention] The present invention utilizes a display data periodic signal of a CRT display device or a separate video signal obtained by separating a composite signal to input display data without storing it in a frame buffer memory (RAM). The interface function converts display data into a mixture of red, green, and blue through real-time processing, allowing color display with the same drive circuit configuration as before, and the interface function allowing monochrome display. The present invention relates to an interface circuit for a display device having the present invention. [Prior Art] Flat displays, especially liquid crystal displays, have the characteristics of being thin, low voltage, and low power consumption. It was put into practical use as a terminal.
Nowadays, liquid crystal interface circuits that can be directly connected to CRT control circuits have been developed for use as display terminals in portable personal computers instead of CRTs. However, the interface circuit of the conventional liquid crystal display device is designed with the idea that the liquid crystal panel is driven even during the blanking period of the CRT display device. Therefore, a frame buffer memory was prepared for display data, and after the display data was written into the frame buffer memory, it was sequentially read out.
Further, since the conventional interface circuit is only for monochrome display, the amount of display information is insufficient when displaying graphically. That is, by using one or two of red, green, and blue color display data on a simple matrix liquid crystal panel, you can simply display
Because of the ON/OFF display, the display device was not as attractive as a CRT display device. However, on the other hand, the technology of color filters on the surface of transparent electrodes of liquid crystal panels has been established, and panels with built-in active elements such as TFT (thin film transistor) and non-linear elements such as MIM, MSI, or smectic liquid crystals with memory functions have been established. Despite the development of new liquid crystal panels, the interface circuit for color liquid crystal display devices has not yet been developed. For this reason, it was necessary to install interface circuits for red, green, and blue in the monochrome liquid crystal display device, which requires a frame buffer memory. In this case, since only stripes can be used for the color dot arrangement of the color panel, there is a problem that it cannot be used for a mosaic color dot arrangement panel. [Problems to be Solved by the Invention] As described above, the interface circuit of a conventional display device has a frame buffer memory prepared as an external circuit, and under the control of the interface circuit writes and writes data. I needed to read it. Therefore, the cost of the circuit structure became high, the circuit structure became complicated, and it was difficult to assemble it into a small display terminal. This is an interface circuit exclusively for monochrome display, and in order to configure the interface circuit for a color display device, it is necessary to prepare three of the interface circuits for monochrome display as one set, which is simply three times as many. The high cost and complexity of the configuration was a problem. The present invention has been made to solve the above problems, and has a function of directly interfacing display data and timing signals to a display device by processing the video signal of a CRT display in real time. It is an object of the present invention to provide an interface circuit that can be applied to color display devices as well. Furthermore, the arrangement of the various colored dots on the color panel (e.g.
The purpose of this is to be able to correspond to striped, mosaic, reverse mosaic, triangular layouts, etc.). [Means for Solving the Problems] In order to solve the above problems, the present invention provides an interface circuit for a display device that generates display data and timing signals for operating the display device. A color display is performed on the S/P conversion circuit through a color scheme selection circuit having an S/P conversion circuit that converts color display data in parallel, and a color display data switching means that periodically switches the color display data. It is designed to input data. [Example] Next, an example of the present invention will be described. . FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a timing diagram to supplement the explanation of the operation of the circuit shown in FIG. 1. In Figure 1, Hsyc is a horizontal synchronization signal, Vsyc is a vertical synchronization signal, CK is a dot clock signal, RD,
GD and BD are red, green, and blue display data, respectively. These Hsyc, Ysyc, CK, RD, GD, BD
is equivalent to an interface signal to a CRT display device. 1 is the dot clock
X-axis display position adjustment circuit that counts CK and adjusts the display position in the X-axis direction, 4 is a horizontal synchronization signal
A Y-axis display position adjustment circuit that counts Hsyc and adjusts the display position in the Y-axis direction, 3 is the X-axis and Y-axis
An AND circuit whose inputs are the outputs of the axis display position adjustment circuits 1 and 4 and the dot clock CK; 6 is a 1/8 frequency dividing circuit for dividing the frequency of the clock signal _P1 , which is the output of the AND circuit 3, into 1/8; 7 is the output of 1/8 frequency divider circuit 6
A frequency dividing circuit for further dividing _P2 to generate a reset signal _P3 for resetting the X-axis display position adjustment circuit; 10, 11, and 12 are for shifting red, green, and blue display data; shift register circuits, 13, 14, 15 are shift registers 10, 1
Latch circuits 41 to 46 are for temporarily latching the display data of 1 and 12, and 41 to 46 are the latch circuits 13.
28 is a switching circuit for time-divisionally switching the display data of ~15 and outputting the display data to the X electrode drive circuit (X driver) of the liquid crystal display device; 28 is a switching circuit for time-divisionally switching the switching circuits 41 to 46; This is a shift register for 24 and 25 are D-type flip-flop circuits (D-type F/F circuits) for receiving the clock signal _P2 and generating the latch signal _P4 . 21
is a set-reset flip-flop circuit for setting upon generation of the latch signal _P4 . 16 and 17 are the Y-axis display position adjustment circuit 4;
This is a D-type flip-flop circuit and a NOR circuit for generating a set pulse signal _P9 when the output _T2 of the circuit rises to "H". 18 is a flip-flop circuit for generating a set output by the set pulse circuit _P9 , and 47 and 48 are D-type flip-flop circuits for delaying the output of the flip-flop circuit 18. The output FRM of the D-type flip-flop circuit 48 is a frame signal. 20 is the frame signal
This is a flip-flop circuit that divides the FRM signal by 1/2. The output of the flip-flop circuit 20 is a liquid crystal AC drive signal M. Further, LK is a latch signal of a latch circuit built in the X-axis drive circuit, which latches display data transferred to the X-axis drive circuit. 31 is a 1/4 frequency dividing circuit for frequency dividing the clock signal _P10 by 1/4. 33 is a flip-flop circuit which divides the output _P13 of the frequency dividing circuit 31 into 1/2. 39,40
is a switching circuit for time-divisionally switching the display data of the latch circuit 15. 35, 36, and 37 are an AND circuit and a ROM circuit, which constitute a selection gate circuit for selecting the shift clock SK of a 4-bit parallel shift register built in the X electrode drive circuit for display data in the case of monochrome or color display. are doing. 50 is a color scheme selection circuit for adjusting the arrangement of red, green, and blue color dots to a stripe arrangement, or a mosaic arrangement, a reverse mosaic arrangement, or the like. Next, the operation of one embodiment of the present invention shown in FIG. 1 will be explained. The X-axis display position adjustment circuit 1 uses a horizontal synchronization signal
When Hsyc is input, the dot clock CK starts counting. When this count value matches the setting value of the blanking period of display data, the
The output T1 of the axis display position adjustment circuit ₁ rises to "H". The setting of this blanking period can be adjusted in dot units by external setting means such as a digital switch. Y-axis display position adjustment circuit 4
starts counting the horizontal synchronization signal Hsyc when the vertical synchronization signal Vsyc is input. When this count value matches the set value of the blanking period of the display data in the Y-axis direction, the output _T2 of the Y-axis display position adjustment circuit 4 rises to "H". The setting of this blanking period can be adjusted in dot units by an external setting means such as a digital switch, as described above. When the outputs _T1 and _T2 of the X-axis and Y-axis position adjustment circuits both rise to "H", it becomes the display starting point (home position),
A clock signal _P1 is output from the AND circuit 3.
The clock signal _P1 is input to the 1/8 frequency divider circuit 6 and shift registers 10, 11, and 12. Display data
RD, GD, and BD are shifted to shift registers 10, 11, and 12 every clock to use the clock signal _P1 as a shift clock. The output _P2 of the 1/8 frequency divider circuit 6 is a D-type flip-flop circuit 24.
and the NOR circuit 25 generates a latch signal _P4 every time eight clock signals _P1 are input,
The parallel display data in the shift registers 10, 11 and 12 are latched in latch circuits 13, 14 and 15 to perform S/P conversion. Since the latch signal _P4 is inverted by the inverter 26 and sets the flip-flop circuit 21, the AND circuit 22 is
Start outputting clock signal _P10 . The clock signal P ₁₀ is frequency-divided by a 1/2 frequency divider circuit 27 and inputted as a shift clock to a shift register 28 . Since the shift register 28 uses the output of the NOR circuit 29 as shift data, it operates as a quaternary ring counter and receives the switching control signal.
P ₅ , P ₆ , and P ₇ are generated, and switching circuits 41 and 42, 43 and 44, and 45 and 46 are time-divisionally switched ON to display display data (UD ₀ to _{UD 3} ) and (LD ₀ to _{LD 3 )} . ) in parallel. The clock signal _P10 is halved by the flip-flop circuit 23.
The clock signal _P8 is output. Furthermore,
Since the flip-flop circuit 23 is reset by a signal obtained by inverting the shift data of the shift register 28 by the inverter 30, the flip-flop circuit 23 outputs 3 clocks of the clock signal P8 by inputting ₈ clocks of the clock signal _P10 , and performs an AND operation. circuit 36,
A shift clock SK is generated through an OR circuit 37. The outputs of the latch circuits 15, 14, 13 are R,
In order to obtain mixed color display data of G and B (red, green, and blue), the data is input to the switching circuits 41 to 46 as follows. The switching circuits 41 to 46 are
It is composed of a 4-bit parallel transmission gate, and its input is connected to latch circuits 15 and 1.
From the 1st bit of 4, 13, R ₁ , G ₁ , B ₁ to _{R 8} ,
Assuming that G ₈ and B ₈ are 8 bits, the switching circuits 41 to 46 are connected as shown in the table below.

〔Effect of the invention〕

As described above, according to the present invention, interface signals from a CRT display device or the like are used to convert into display data and timing signals for a flat display device through real-time processing.
Since frame buffer memory is not required,
It has become possible to produce small, low-cost, flat-type display terminals by using gate array ICs. It has become possible to provide an interface circuit for color display, which did not previously exist, and this has further increased the appeal of flat type display devices. A single interface circuit allows selection of display mode, monochrome display or color display. Since the same conventional drive circuit can be used, there is no need to develop a color-specific drive circuit.For panels with various color dot arrangements such as stripe type, mosaic type, or reverse mosaic type of color display panels. Also, the optimum method can be selected at any time using the selection terminal, so it is extremely versatile. It has many effects such as: And, the present invention is an MSI (metal semiconductor-
blanking for active matrices with built-in non-linear resistance elements such as ive insulators and MIMs, active matrices with built-in switching transistors such as TFT panels, and ferroelectric liquid crystal panels with memory such as smectic liquid crystal panels. This is especially effective in the case of these new type liquid crystal panels that utilize the memory properties of the elements.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
Figures A to E are diagrams showing the timing of Figure 1, Figure 3 is a diagram showing an example of the electrode configuration of a color liquid crystal panel, Figure 4 is a diagram showing an example of color dot arrangement, and Figure 5. 6A and 6B are diagrams showing an embodiment of the color dot placement selection circuit, and FIGS. 6A and 6B are diagrams showing the system configuration. 1...X-axis display position adjustment circuit, 2...Y-axis display position adjustment circuit, 3...AND circuit, 6...1/8 frequency division circuit, 7
...Frequency divider circuit, 9,16,24,47,48...D flip-flop circuit, 10,11,12...Shift register, 13,14,15...Latch circuit, 1
8, 21, 23...flip-flop circuit, 20,
27, 33...1/2 frequency divider circuit, 31...1/4 frequency divider circuit,
39-46...Switching circuit, 64, 65, 6
6... Switching circuit, 51, 52... D-type flip-flop circuit, 55, 56, 57, 58... Transmission circuit.

Claims (1)

[Scope of Claims] 1. Color signal switching means that repeatedly outputs display color data consisting of R, G, and B in a predetermined order, and the order of color output is selectively controlled by a color scheme selection signal; a color scheme selection circuit comprising a color scheme selection means for generating the color scheme selection signal; a serial/parallel conversion circuit inputting the output of the color scheme selection circuit and outputting parallel color display data; and the parallel color display. a latch circuit that inputs and latches data; a plurality of switching circuits that time-sequentially switches the parallel color display data from the latch circuit in units of multiple bits and outputs the same to a drive circuit of a matrix type display device; An interface circuit for a matrix type display device including signal generating means for supplying the switching control signal to the switching circuit, wherein the color scheme selection means generates a display signal for a stripe mode and a display for a forward/reverse mosaic mode. At least a signal selection switching means and a horizontal synchronization signal input terminal are provided as an input section, and the signal selected by the selection switching means changes the first display color of each row of the screen to the selected one in synchronization with the horizontal synchronization signal. 1. An interface circuit for a matrix type display device, characterized in that the interface circuit selects a color scheme according to the type of signal and outputs a color scheme selection signal.