JPS592086A - Matrix display driving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] A: The present invention relates to a drive circuit for an IJ display device, and is particularly effective for driving a multi-split screen IJ display Kft, which is effective for expanding the display scale and improving display quality. Regarding circuits.

A so-called matrix display device that displays by arranging electrodes in a matrix performs display by applying line-sequential signals to the row electrodes, but as the display scale of such a display device increases and the number of scanning lines increases. However, the disadvantage is that the display contrast is low and sufficient display quality cannot be obtained. As a means to overcome this drawback, a method is often used that uses a display panel in which the display screen is divided into two from the center, as shown in FIG.

In FIG. 1, 4A and 4B image data signals are shown.
5 is a column electrode drive circuit for receiving the signal D, converting it into a display signal suitable for driving a display panel and applying it to the panel; and 5 a row electrode drive circuit for applying a line sequential scanning signal. 7 is a 2'+ split matrix display panel having pixels in rows and columns J. As can be seen from the figure, the column electrodes are divided at the center of the panel, and the output lines of the column electrode drive circuits 4A, 4B are are connected to each other, and the upper F screen forms one open plane. As shown in the figure, the row electrodes are electrically connected between the two divided screens in the upper F and are tangential to the common row electrode drive circuit 5 -C1. Note that the column-pole drive circuits 4A and 4
B is a serial-to-parallel conversion type line memo IJ41A, 41B that stores one row of data, and multiplexers 42A, 42B that change pk to create a drive suitable for driving the display panel.
Consists of.

On the other hand, in order to form an image on the display panel, the peripheral circuit 5
0, a refresh memory 3 (hereinafter simply referred to as memory) capable of storing image data for at least one screen, a readout circuit 2 for reading out the contents of this memory, and a refresh memory 3 (hereinafter simply referred to as memory) capable of storing image data for at least one screen; A υ period address setting circuit 1 is required to set the initial value of the read address.

By the way, when driving a two-split matrix display panel, the row electrode drive circuits are commonly used, so the column electrode drive circuits 4A and 4B are used to drive the images corresponding to the upper and upper surfaces of the display panel. The data signals IA, IA, and IA must be transferred almost simultaneously.For this reason, in the conventional chestnut, data is transferred almost simultaneously using the method shown in FIG. 42.3 In FIG. 1[1 is the initial °r dress fixture for the upper and lower screens, 2A, 2Br, address generation a for reading image data from the memory, 11 The half-dress switching circuit 3 is a memory.
The address switching circuit 1 alternately switches the address on the upper surface and the address on the upper surface, and the memory output data signals 1 and 2, which are switched accordingly, are changed to column '4.' with an appropriate lock signal. This is to be transferred to the pole drive drives 4A and 4B.

However, in such a method, two initial address setting circuits IA and IB must be prepared, so there is a drawback that the peripheral circuit cannot be miniaturized.

In addition, for displays, there is a method called page switching in which the data for two or more screens is stored in the frame memory and the screen is instantly switched by simply changing the initial value of the read address. There is a drawback that the setting values of the address setters IA and IB must be individually reset.

Furthermore, the same drawback exists in the scroll display method in which the display screen is shifted by one line in the -'F direction by incrementing the initial value of the read address by 1 (by one line of the screen).

This kind of problem occurs not only when driving a 2-split matrix display panel as shown in Figure @1, but also when driving a general kO-reduced matrix display panel (2≦≦■/2) such as a 3-split or 4-split matrix display panel. occurs in

An object of the present invention is to reduce the number of initial address setters during k-divided interest driving to 1 fl! in a matrix display device having a k-divided matrix display panel. It is an object of the present invention to provide a drive circuit for a display device, which allows the circuit to be miniaturized and to easily set an initial address value in a scroll display mode.

The feature of the present invention is that in the 2 address generation circuits of a k-split screen matrix display device, -C1 is set to (t+1) the final address of the address generation circuit of the 2nd (-1 for r≦t≦) address generation circuit. The purpose is to use this as the initial address of the second address generation circuit.

The present invention eliminates the above-mentioned drawbacks. From F
, FIG. 31, g4+4, and FIG.

FIG. 3 is a configuration diagram of the display device. In Figure 3,
8 is a control circuit with internal address settings ar1,
Two address generation circuits and 2B, a timing clock generator 10, and an address switching circuit 11 are attached. Further, 3 is a refresh memory, which is a memory capable of storing image data for one screen or more. 7 is a two-split display panel (k=2) having pixels in I row and J column;
Like the conventional example shown in the figure, it is composed of column electrode drive circuits 4A and 4B and a row electrode drive circuit 5. This peripheral circuit operates exactly the same as the conventional example.

The setting of the address value of the address setter is performed by a signal from a computer or the like. Further, the address generation circuits 2 and 2B are so-called presettable counters, which are preset at each refresh frame period.

As shown in FIG. 3, the initial address values of the two address generation circuits are set by the output of the address setter 1.

The output of the two address generation circuits is address switching port 1.
1 and is also connected to the preset input of the address generation circuit 2B. Furthermore, address generation circuit 2
The output of B is input to the switching circuit 11. The output (+) of the clock generator 10 is input to the two address generation circuits and 2B.
) and (el are applied, and address signals are output in synchronization with each other. Two types of address signals (C), (f
) is selectively switched by the address switching circuit 11, and this one word becomes the address signal 01) of the refresh memory 3. In response to this address signal 01), one copy of the image data in the refresh memory 3 is output, and the image data DI is sent to the upper and lower column electrode drive circuits 4A and 4B.

Transfer Dt.

Next, the operation of the display device having this configuration will be explained using the 41d time chart. Here, in order to avoid complication of explanation, the refresh memory will be explained using a memory in which one bit per address is output. Further, the refresh memory has addresses al + at + . . . corresponding to the display screen.

aR+ “nul+”・l Alm, image data A
,,A,.

...A, B, ...B are stored in the array shown in FIG.

FIG. 4(a) is a load pulse, and from this pulse 2, the initial value a of the two address generation circuits is determined by the initial address setting, (
Established from Ren 1). width) is the address generator? &
2 A clock applied to A. This clock causes the ``address generation source, I! The output of 82A is sequentially al + a! as shown in (c) of the same figure. +..., a is output.

-4, (d> is the load pulse signal of the address generator circuit 2B. With this pulse generated just before the frame period and the clock (e), the output of the address generator circuit 2B is (f).
Changes as shown in . As can be seen from the figure, the clock in (e) is a pulse added just before the frame period to the peak), and the output of the address generation circuit 2B is in the frame period, aR411a, 7. ...+32
Immediately before the frame period m and the previous stage address output signal a
, di output.

Now, the outputs of the two address generation circuits and 2B are input to the address switching circuit 11 and selectively switched by the clock (g). Then, since the address signal of the refresh memory 3 becomes K as 0)), a signal (i) in which the data on the lower surface and the data on the lower surface are alternately switched is obtained at the output of the memory. Furthermore, 1, this data signal (i
) are taken into the column electrode drive circuits above and below the clock (j) and (k) K, respectively, so the data in (2) is stored in the column electrode drive circuit 4A on the bottom surface, and Sixth data will be transferred to the drive circuit 4B. Hereinafter, since the operation of the drive circuit section is exactly the same as that of the conventional example, the explanation will be omitted here.

Address shield raw circuit 2A, 2B, address switching circuit 11
, column electrode drive circuits 4A, 4I3, etc. are all controlled by the clock from the clock generation circuit 10. Ill
However, even if the phase of the clock signal is modified, for example, as in (a') and (1N') of No. 6i91, the address output signal will be changed so that the lower side and the lower side are sequentially alternated. 4, and is not limited to the control signal shown in FIG. 4.

Furthermore, in this embodiment, a case has been described in which the load pulses and clocks applied to address iF=two raw circuits and 2B are modified, but as the address generation circuit 2B, for example, a counter with set/reset is used, A method using a control signal different from the control signal may also be used. That is, the output of the address generation circuit of Kgl per frame period is
There is a second address generation circuit which inputs an initial setting value; By switching the second address output,
Any device that can obtain a predetermined operation may be used.

In the embodiments of the present invention, the memory format is one in which one address and one bit are output.
For example, in the case of using 8-pit output per address, the parallel-to-serial converter 20 may be interposed between the refresh memory 3 and the column electrode drive circuits 4A and 4B. An example of the circuit configuration in this case is shown in FIG. 7, and an example of a control signal for driving this is shown in FIG. The image data output signal of the refresh memory 3 is as shown in (i) as in the above-mentioned implementation, where (i) is a parallel output signal of the negative number bits, and 9 (i) is a parallel output signal of serial bits. It becomes the input of the converter 30, and the data signal is serialized by the clock (n). (j') and (k') are clocks for transferring data signals, and thereby the column, 4-pole 1-driving circuit 4A
and transfer the image data to 4B.

As described above, a predetermined display can be obtained in the same manner as in the above-mentioned implementation row.

Furthermore, the same holds true when using a character generator. An example of the circuit configuration at this time is shown in FIG. In this case, the output signal (i) of the refresh memory 3 is code data, and if this data is converted into dot data by the character generator 30v and further inputted to the parallel-serial converter 20, good. Note that the character generator 3o includes
In addition to the code data (i), a part of the memory address signal is input as a row address signal (2), but this configuration is the same as the conventional one.

Next, operations during scroll display and page switching display will be explained using FIG. 3, FIG. 1o, and FIG. 11.

In Fig. 3, the image data stored in the refresh memory: ] differs from Fig. 5, and when switching pages,
At least two screens worth of image data are stored. In Figure 10, the artist data of the first screen is
..., All, B,,...+Bn, the image data of the second screen is C7,..., C1D1 +..., D9, and the final display data of the first line of the first picture direction is Am. It is said that

For operations before scrolling and page switching, the output (p) of the initial address setter 1 is address a8, and as mentioned above, the memory address is set to aI as the initial value.
The operation is repeated from a to a by switching from one to the other.

By the way, during scroll display, the value of the output (p) of the address setter 1 is switched from a to -1 at the timing shown in FIG. 11.

This switching is done from the first computer. Then, from the next cycle, the initial address value of the refresh memory 3 will be a,
,,becomes 4I. Hereinafter, as in the previous embodiment,
The address value 01) of refresh memory 3 is am+,
+ ae+m+I l 3m+21 ”' +32
Since the image is switched to 114111, image data (i) is output accordingly. As explained in the operation of the above embodiment, the final address value of the lower surface at this time is a
l, etc., and this address data becomes the preset address data for the upward surface. Therefore, the column electrode drive circuit 4A includes A, R, 1 v Away e..., B-
The display data of Bm+1 is also stored in the column electrode drive circuit 4B.
1 B +, +2. Since the image data of 10111 are transferred sequentially, a display shifted by one line is obtained on the display screen compared to the display before scrolling.

On the other hand, the page switching operation can also be realized in exactly the same way. That is, in the case of °4, by simply setting the initial address setting value to C7,1, the display screen changes from the previous A, , A, , ..., B, to C,, C,, .
..., 1).

Therefore, even when scrolling or switching pages, there is no need to be aware that the display panel is a two-part matrix display panel, and just the initial address setting of the display screen is just the same as with conventional CR, T displays, etc. , even though the prescribed display is obtained, as shown in Figure 11, image data of the F screen remains in one cycle immediately after scrolling and page switching, but this time is extremely short (normally (approximately 1/60 second) and is almost imperceptible to the human eye.

In this practical example, a two-part matrix display panel has been described as an example, but the present invention is not limited to this, and an inverted two-part matrix display panel 71 as shown in FIG.
, a four-part matrix display panel 72 shown in FIG.
It can also be applied to general divided matrix display panels such as.

According to the present invention, when driving a k-divided matrix display panel, it is possible to reduce the number of initial address value setting circuits to one, thereby reducing the size of the circuit, and at the same time, it is possible to reduce the size of the circuit. Easy to set up.

[Brief explanation of the drawing]

fg The figure is an explanatory diagram of the driving method of a two-part display panel, the second
The figure is a diagram of a conventional example, and Figure 3 is a diagram of a first drive circuit of the present invention.
Fig. 4 is a time chart thereof, Fig. 5 is a data array diagram of the memory, Fig. 6 is a diagram of a modification of the mowing signal of the implementation row, and Fig. 7 is a second actual winding example of the present invention. 8 is a diagram of an example of the control signal, FIG. 9 is a diagram of the third embodiment of the present invention, and FIGS. 10 and 11 are scroll displays and pages in the first embodiment of the present invention. Diagram explaining operation of section display, 12th
13 and 13 are diagrams showing other application examples of the present invention. IA...Address setter 2A, 2B...Address generation circuit, 3...Refresh memory, 4A, 4t3
. . . Column electrode drive circuit, 5 . . . Row electrode drive circuit, 7.
... Two-division matrix display panel, 10... Clock generation circuit, 11... Address switching circuit.腯I eye A 4δ 腯2 eyes 3 eyes 4(c) 薯にn 薯＄9 eyes

Claims (1)

[Claims] 1. A display body is provided between the row electrodes and the column electrodes, and pixels are formed at the intersections of the row electrodes and the column reeds, and the pixels form an IJ square shape with one row and five columns as a whole. In what drives the matrix display panel, k rows (2≦ and ≦I/2
), a row viewing pole drive circuit that applies a selection signal to the row electrodes to simultaneously select the row talk corresponding to the pixels of ) for a certain period of time; a refresh memory that stores image 1ψ data for at least one screen; 1 (face value (1≦t≦-1)
When the final address of (t4-1) becomes the initial address of the face, there is one address generation circuit, an address switching circuit that sequentially selects one of the address generation circuits, and a picture of the above-mentioned reflex memory. 1) A drive circuit for an IJ display device, characterized in that the column is equipped with a column pole drive circuit that applies a display signal to the poles based on data.