JP4454068B2 - Display device control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control circuit for a display device such as a liquid crystal display (LCD), which controls each pixel based on a digital video signal and performs display. The present invention relates to a control circuit of a display device that performs display by dividing into multiple phases in a direction.
[0002]
[Prior art]
Hereinafter, a control circuit of an active matrix LCD will be described as an example of a conventional display device. FIG. 12 is a block diagram of a conventional LCD and its driving circuit. A conventional drive circuit includes a driver 101 to which a video signal is input, a plurality of data lines 102 extending in the vertical direction, a plurality of gate lines 103 extending in the horizontal direction, and a data line selector for sequentially selecting one of the data lines 102. 104, one of the gate lines 103 is selected in sequence, a gate driver 105 for applying a gate voltage thereto, and a thin film transistor (TFT) 106 is formed at each grid point of the data line 102 and the gate line 103. The pixel electrode 107, the common line 108 connected to the driver 101, and the TFT 109 whose gate is connected to the data line selector 104 are included.
[0003]
A video signal, which is a digital signal, is input to the driver 101 from the outside, and is temporarily stored (buffer), and is subjected to digital / analog conversion (DA conversion), thereby applying a pixel voltage applied to the pixel electrode of each pixel. Are output sequentially. The gate driver 105 selects one gate line 103 for each horizontal scanning period and applies a gate voltage to turn on the TFT 106 in that row. The data line selector 104 selects one of the plurality of connected TFTs 109 and activates one of the data lines 102 to apply a pixel voltage to the data line 104. As a result, a pixel voltage is applied to the pixel electrode connected thereto via the TFT 106 at the intersection of the selected data line 102 and the gate line 103. When the shift clock becomes high, the data line selector 104 selects the next data line 102 and applies a pixel voltage thereto. Similarly, the data line selector 104 sequentially selects from the leftmost data line during one horizontal scanning period, and selects the next pixel each time the shift clock becomes high, and the driver 101 applies to each pixel. The pixel voltages to be output are sequentially output.
[0004]
With the recent increase in the number of display pixels of LCDs and higher definition, the number of pixels that must be written during one horizontal scanning period has increased. For example, although the number of pixels in the horizontal direction is 640 in VGA, it is doubled to 1280 in SXGA. At this time, if the number of vertical lines is the same, the length of one horizontal period does not change. Therefore, when the number of pixels increases, the frequency of the shift clock increases, and the time taken to apply a voltage per pixel decreases. To do. Further, when the number of vertical lines is increased, one horizontal period itself is shortened. However, the operation speed of the driver 101 has an upper limit, and the response speed of the liquid crystal also has an upper limit.
[0005]
On the other hand, there has been proposed a control method in which a video signal for one row is divided into a plurality and a voltage is applied in parallel to a plurality of pixel electrodes. Hereinafter, a control method for dividing the video signal into two phases will be described as an example.
[0006]
FIG. 13 is a block diagram of a control circuit for an LCD that is divided into two phases. This control circuit has a multiplexer 121 and a two-stage driver 122, and the data line selector 123 is different from the control circuit of FIG. 12 in that it is configured to select two data lines at a time.
[0007]
A video signal input from the outside is alternately divided into two phases for each pixel by the multiplexer 121 and input to the two-stage driver 122. The two-stage driver 122 simultaneously processes data for two pixels and outputs a pixel voltage for two pixels. The data line selector 123 simultaneously selects adjacent TFTs 109, simultaneously activates two adjacent data lines 102, and applies two pixel voltages simultaneously. For example, the data line selector 123 first selects the first and second data lines. The two-stage driver 122 outputs the pixel voltages of the first and second columns, and the pixel voltages are applied to the pixel electrodes. Next, after two cycles of the shift clock, the data line selector 123 simultaneously selects the third and fourth data lines, and the two-stage driver 122 outputs the third and fourth pixel voltages. Thereafter, the voltage is applied in units of two pixels in the same manner. In this way, by applying a voltage simultaneously to a plurality of pixel electrodes and controlling the pixel voltage, the pixel voltage can be continuously applied for a plurality of periods of the shift clock, and the pixel voltage application time is sufficiently secured even when the number of pixels increases. can do.
[0008]
In addition, a control method has been proposed in which a display area is divided into several parts in the horizontal direction and a voltage is applied in parallel to a plurality of pixels. Hereinafter, a control method for horizontally dividing the display area into two will be described as an example.
[0009]
FIG. 14 is a block diagram of an LCD control circuit divided into two horizontal regions. This control circuit is different from the control circuit of FIG. 12 in that it has a multiplexer 131, a memory unit 132, and a two-stage driver 133, and the data line selector 134 is configured to select two data lines at a time.
[0010]
The video signal for one row input from the outside is input to the multiplexer 131. The multiplexer 131 outputs the first half of the video signal, that is, the data on the left half of the screen to the memory unit 132, and the memory unit 132 temporarily stores the data. The memory unit 132 outputs the first half data to the two-stage driver 133 in synchronization with the second half data, that is, the right half data on the screen. The two-stage driver 133 outputs pixel voltages V1 and V2 based on the first half data and the second half data.
[0011]
The data line selector 134 simultaneously selects two of the data lines 135 and applies two pixel voltages simultaneously. For example, the data line selector 123 first selects the first data line in the first column and the right half, for example, the data line 134a in the 401st column in the case of a horizontal 800 pixel LCD. The two-stage driver 122 outputs the pixel voltages of the first and 401st columns, and the pixel voltages are applied to the pixel electrodes. Next, the data line selector 134 simultaneously selects the data lines of the second column and the 402th column, and the two-stage driver 133 outputs the pixel voltages of the second column and the 402th column. Thereafter, the voltage is applied in units of two pixels in the same manner. Also by this control method, by simultaneously applying a voltage to a plurality of pixel electrodes and controlling the pixel voltage, the pixel voltage can be continuously applied for a plurality of periods of the shift clock, and the pixel voltage application time can be increased even if the number of pixels increases. Can be secured sufficiently.
[0012]
In this manner, by dividing the video signal into multiple phases and simultaneously applying the pixel voltage to a plurality of pixels, it is possible to ensure the application time of the pixel voltage even when the number of pixels increases.
[0013]
[Problems to be solved by the invention]
In order to cope with various driving methods and display devices with various numbers of pixels as described above, separate control circuits are manufactured. However, if different control circuits are produced for each driving method and the number of pixels, the production amount of each type of control circuit decreases, resulting in a problem that the manufacturing cost of each control circuit increases.
[0014]
An object of the present invention is to provide a control circuit that drives an LCD by being divided into a plurality of horizontal regions as described above, and that is efficient in operation and versatile.
[0015]
[Means for Solving the Problems]
The present invention has been made in order to solve the above problems, and is a control circuit for controlling a display device based on a digital video signal inputted thereto, a splitting unit for splitting the digital video signal according to a predetermined rule, A plurality of memory units for storing the digital video signals, and a driver for converting the output of the memory unit and outputting a control signal for the display device. A write line memory having a predetermined number of words inputted to the read line memory, a read line memory having the same number of words as the write line memory in which the contents of the write line memory are transferred in parallel, and a plurality of different addresses of the read line memory. Control circuit for a display device that has a plurality of output terminals and outputs serially from one of the output terminals. .
[0016]
Further, the screen of the display device is controlled by being divided into a plurality of regions in the horizontal direction, and the number of memory units is determined according to the number of divisions in the horizontal direction.
[0017]
The number of memory units is the product of the number of regions for dividing the screen in the horizontal direction and the number of display primary colors of the display device. In each memory unit, digital video signals of different regions or different primary colors are stored. Entered.
[0018]
The output terminal of the read line memory is provided at an address having a number of words that can store data for 256 pixels or / and 320 pixels or / and 400 pixels.
[0019]
Further, a selector for selecting one of the plurality of output terminals is provided.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
First, as a first embodiment, a control circuit for controlling a horizontal 800 pixel SVGA panel with two phases divided horizontally and divided into a total of two phases will be described. FIG. 1A and FIG. 1B are block diagrams of a control circuit for performing horizontal two-region two-phase division. The control circuit according to the present embodiment includes a first multiplexer 1 as a dividing unit that divides an input signal into two parts in the first half and the second half of the horizontal scanning period, a first memory unit 2 to which the first half signal is input, and a second half signal. Are input to the second memory unit 3, the first multiplexer 2, and the second multiplexer 4 that outputs the combined outputs of the first and second memory units at the same time. A two-stage driver 5 is provided.
[0021]
The first and second memory units 2 and 3 are each a write line memory 2a and 3a as a first storage device that is serially input, and a second that outputs data of the write line memory in parallel and is output serially. Read line memories 2b and 3b.
[0022]
When the video signal is input to the multiplexer 1, the multiplexer 1 outputs a signal for the first half of each horizontal scanning period, that is, a video for 400 pixels displayed in the first region of the left half of the screen among the video signals for one row. The signals are sequentially output to the write line memory 2a of the first memory unit 2. The write line memory is a line memory having a capacity of 400 words, and an input signal is first written to the first address. In this specification, the line memory means that a predetermined number of storage areas are arranged in series. When the next signal is input, the signal written at the first address is transferred to the adjacent second address, and the next signal is written at the first address instead. Similarly, each time a new signal is input, the stored signal is transferred to the address of the next number, and serial input is performed. When a video signal for 400 pixels is input, the entire storage area of the write line memory 2a is written. Next, a signal in the second half of the horizontal scanning period, that is, a video signal for 400 pixels displayed in the second area on the right half of the screen starts to be input to the multiplexer 1. Are sequentially serially output to the write line memory 3a. When signals for 400 pixels are input to the write line memories 2a and 3a, respectively, and signals are input up to the 400th address, the write line memories 2a and 3a read all stored contents in parallel to the read line memories 2b and 3b. Forward to. The read line memory 2b has the same number of words (400 words in this embodiment) as the write line memory 2a, and each address of the write line memory 2a is connected to the address of the same number in the read line memory 2b. Transfer each address simultaneously. This transfer is performed during the horizontal blanking period. When the video signal of the next row starts to be input to the multiplexer 1 after the transfer is completed, the same processing is repeated.
[0023]
On the other hand, as for the data stored in the read line memories 2b and 3b, the data at the 400th address are output from the output terminals A-Out1 and B-Out1 to the multiplexer 4 and serially input to the two-stage driver 5. . Out-1 (here, Out-1 is a generic term for A-Out1 and B-Out1) is an output terminal connected to 400 addresses. The driver is a circuit that generates a control signal for the display device based on data output from the memory unit. By outputting the data at the 400th address, the data at the first to 399th addresses are transferred one by one to the next numbered address. The two-stage driver 5 buffers two pixels of data, performs digital-analog conversion, etc., and selects the voltage V1 according to the output of A-Out1 and the voltage V2 according to the output of B-Out1 as control signals. Output to the pixel electrode.
[0024]
FIG. 2 shows an LCD having two horizontal regions and two phases. The data line selector 11 is a selector which sets two of the 800 output terminals to high and simultaneously selects two of the data lines 12 extending in the vertical direction. The gate driver 13 is a driver that selects one of the plurality of gate lines 14 and applies a gate voltage thereto. Assume that the gate line 14a and the data lines 12a and 12A are selected. Now, V1 and V2 are data stored at the first address of each line memory. The output V1 of the control circuit in FIG. 1 is applied to the pixel in the first column (hereinafter, the pixel in the nth column may be referred to as pixel n) via the data line 12a, and the other output V2 is the data line. It is applied to the pixel 401 via 12A.
[0025]
Next, after two shift clock cycles, the data at the 400th address in the read line memories 2 b and 3 b is read again and input to the driver 5. At this time, the data written at the 400th address is data written at the 399th address immediately after the parallel transfer. Then, by reading the data at the 400th address, one piece of data at the second to 399th addresses is transferred. Based on the output data at the 400th address, V1 and V2 are output from the driver 5 again. In FIG. 2, the data line selector 11 switches to and selects the data lines 12b and 12B after two shift clock cycles. As a result, a voltage is applied to the pixels in the second and 402th columns.
[0026]
In the same manner, voltage is applied in the 3rd, 403th, 4th, and 404th columns, and when a voltage is applied to the 400th and 800th pixels, one row of voltage is applied. Ends. Thereafter, a horizontal synchronization signal is output, and the gate driver selects the gate line 14b of the next row and continues writing.
[0027]
Next, the role of the memory units 2 and 3 in the first embodiment will be described. The video signal is continuously input to the control circuit of FIG. In order to apply a voltage by dividing the screen into two left and right regions, the data applied to the pixels in the first column and the pixels in the 401th column can be simultaneously saved by temporarily storing them in the memory units 2 and 3. 5 can be output. Further, since data is serially input to the write line memory and transferred to the read line memory in parallel, data writing can be performed without delay.
[0028]
Next, the read operation from the read line memories 2b and 3b will be described more specifically with reference to the timing chart of FIG. First, until the timing A, the parallel transfer from the write line memories 2a and 3a to the read line memories 2b and 3b is completed, and pixel data for one horizontal line is stored together with the read line memories 2b and 3b. To do. When the shift clock becomes high at timing A, the 2b read clock input to the read line memory 2b becomes high. Then, the readout line memory 2b outputs the data of the pixel 1. At this time, the memory selection signal is high, the multiplexer 4 in FIG. 1 selects the output of the readout line memory 2b, and the data of the pixel 1 is output from the multiplexer 4. Next, at the timing B at which the shift clock once low becomes high again, the 3b read clock input to the read line memory 3b becomes high. Then, the readout line memory 3b outputs the data of the pixel 401. The memory selection signal is low at timing B, and the multiplexer 4 selects the read line memory 3b and outputs this data. Next, at the timing C at which the shift clock once low becomes high again, the 2b read clock becomes high, and similarly, the data of the pixel 2 is output from the multiplexer 4. Further, the driver 5 outputs a voltage corresponding to the data of the pixel 401 as the control voltage V1 and the data of the pixel 401 as the V2. The outputs of V1 and V2 are continuously output for two shift clock cycles. Thereafter, as shown in FIG. 3, the read operation continues in the same manner.
[0029]
Next, as a second embodiment, a control circuit for controlling a UXGA panel having 1600 pixels in a horizontal direction with a single four-phase division into a total of four phases will be described. 4 (a) and 4 (b) are block diagrams of a control circuit for performing horizontal four-region four-phase division. The first multiplexer 21 that divides the video signal into four parts, the first to fourth memory units 22, 23, 24, 25 to which the divided video signals are respectively input, and the outputs of the respective memory units are integrated and output. The second multiplexer 26 has a buffer and a four-stage driver 27 that performs digital-analog conversion. Each memory unit has the same configuration as the memory units 2 and 3 in FIG.
[0030]
When the video signal is input, the multiplexer 21 sends the video signal of the first 400 pixels, that is, the first area of the left 1/4 of the screen, to the first memory unit 22 and the next 400 pixels, that is, the center left of the screen. The video signal of the second area is sent to the second memory section 23 for the next 400 pixels, that is, the video signal of the third area on the right side of the center of the screen is sent to the third memory section 24 for the next 400 pixels, that is, The video signal in the fourth area on the right quarter of the screen is divided and output to the fourth memory unit 25. Each of the write line memories 22a, 23a, 24a, and 25a is serially input and transferred in parallel to the read line memories 22b, 23b, 24b, and 25b during the horizontal blanking period. The data of each first address is sequentially output from the A-Out, B-Out, C-Out, and D-Out output terminals to the multiplexer 26 and serially input to the four-stage driver 27. The four-stage driver 27 buffers data for four pixels and outputs voltages V1, V2, V3, and V4 applied to the pixel electrodes by performing digital-analog conversion or the like.
[0031]
FIG. 5 shows an LCD with four horizontal regions and four phases. The data line selector 15 is a selector that simultaneously selects four of the 1600 data lines. The gate driver 13 is a driver that selects one of the gate lines 14 and applies a gate voltage thereto. Assume that the gate line 14a and the four data lines 12a are selected. The pixel voltage V1, which is a control signal output by the control circuit of FIG. 1, is output to the pixel in the first column via the data line 12a, the output V2 to the pixel in the 401st column, V3 to the pixel in the 801th column, V4 Is applied to each pixel in the 1201th column.
[0032]
Next, the multiplexer 26 in FIG. 4 again reads the data at the 400th address of the read line memories 22b, 23b, 24b, and 25b (the data written at the 399th address immediately after the parallel transfer). Input to the driver 27. In FIG. 5, the data line selector 15 is switched to four data lines 12b after four periods of the shift clock. Accordingly, a voltage is applied to the pixel 2, the pixel 402, the pixel 802, and the pixel 1202.
[0033]
In the same manner, voltage application is continued. When voltage is applied to the pixel 400, the pixel 800, the pixel 1200, and the pixel 1600, the voltage application for one row is completed. Thereafter, a horizontal synchronizing signal is output, and the gate driver selects the next gate line 14b and continues writing.
[0034]
Next, as a third embodiment, a control circuit for controlling a horizontal 800 pixel SVGA panel with three horizontal phases divided into six phases in total is described. FIGS. 1A and 1C are block diagrams of a control circuit for performing horizontal two-region six-phase division. The method of outputting data from the read line memory and the point having the six-stage driver 7 are different from those of the first embodiment.
[0035]
When the video signal is input to the multiplexer 1, the first half of the horizontal scanning period is stored in the write line memory 2a and the second half of the video signal is stored in the write line memory 3a, respectively, as in the first embodiment. 2b and 3b are transferred in parallel. The multiplexer 6 serially reads the data at the first to third addresses in the read line memory 2 b, and then reads the data at the first to third addresses in the read line memory 3 b serially and outputs it to the six-stage driver 7. The six-stage driver 7 generates and outputs pixel voltages V1 to V6 based on the input data for six pixels.
[0036]
FIG. 6 shows a horizontal 2-region 6-phase LCD. The data line selector 16 is a selector that simultaneously selects six of the 800 data lines. The gate driver 13 is a driver that selects one of the plurality of gate lines 14 and applies a gate voltage thereto. Assume that the gate line 14a and six data lines connected to the output terminals 12a and 12A are selected. V1, V2, and V3 output from the control circuit of FIG. 1C are respectively applied to pixels in the first, second, and third columns via the data line 12a, and V4, V5, and V6 are 401, 402 via the data line 12A. , 403 column.
[0037]
Next, the multiplexer 6 in FIG. 1C again reads the data of the first to third addresses (data written to the fourth to sixth addresses immediately after the parallel transfer) of the read line memories 2b and 3b. Are input to the six-stage driver 7, and V1 to V6 are again output from the driver 7 based on this. In FIG. 6, the data line selector switches to and selects the data lines 12b and 12B after 6 shift clock cycles. As a result, a voltage is applied to the pixels in the fourth, fifth, and sixth columns and the 404, 405, and 406th columns.
[0038]
Thereafter, the voltage is applied in the same manner, and when a voltage is applied to the pixels in the 400th and 800th columns, the voltage application for one row is completed. Thereafter, a horizontal synchronizing signal is output, and the gate driver selects the next gate line 14b and continues writing.
[0039]
Next, the read operation from the read line memories 2b and 3b will be described more specifically with reference to the timing chart of FIG. First, until the timing A, the parallel transfer from the write line memories 2a and 3a to the read line memories 2b and 3b is completed, and pixel data for one horizontal line is stored together with the read line memories 2b and 3b. To do. When the shift clock becomes high at timings A, B, and C, the 2b read clock input to the read line memory 2b becomes high at each timing in synchronization therewith. Then, the readout line memory 2b sequentially outputs the data of the pixels 1, 2, and 3. During this time, the memory selection signal is continuously high, the multiplexer 6 in FIG. 1C selects the output of the readout line memory 2b, and the data of the pixels 1, 2, and 3 are sequentially sent from the multiplexer 6. Is output. Next, at the timings D, E, and F when the shift clock becomes high, the 3b read clock input to the read line memory 3b becomes high at each timing in synchronization therewith. Then, the readout line memory 3b outputs data of the pixels 401, 402, and 403. During this time, the memory selection signal is continuously low, and the multiplexer 6 selects the read line memory 3b and outputs this data. Next, at timing G, the 2b readout clock goes high, and similarly, the data of the pixel 4 is output from the multiplexer 6. Although not shown, from the timing G, voltages corresponding to the data of the pixels 1, 2, 3, 401, 402, 403 are output from the driver 7 as the control voltages V1, V2, V3, V4, V5, V6. . The outputs V1 to V6 are continuously output for 6 shift clock cycles. Thereafter, the read operation continues similarly.
[0040]
Incidentally, the number of horizontal pixels of the LCD may be different from the above, such as a VGA of 640 horizontal pixels and an XGA of 1024 horizontal pixels. In order to control an LCD having a different number of pixels for each of these, the number of words (total number of addresses) of the write and read line memories may be formed in accordance with the number of pixels. In other words, if division control is performed in two horizontal areas with VGA, the number of words in the line memory is 320 words, which is 1/2 of that, and if division control is performed in four horizontal areas with XGA, it is 256 words in 1/4 of that. You can do it.
[0041]
However, if a control circuit is created for each LCD having a different number of pixels, the production amount of each control circuit decreases, and the manufacturing cost of each control circuit increases. If the control circuit has general versatility and can be controlled by using the same control circuit for LCDs having different numbers of pixels, the production amount of the control circuit increases and the manufacturing cost can be suppressed.
[0042]
For this purpose, the read line memory of FIG. 1 has second and third output terminals Out2 and Out3, respectively. (Here, for example, Out1 is a generic name for A-Out1 and B-Out1.) The output terminals Out1 to Out3 serially output data at addresses whose numbers are smaller than the addresses to which the output terminals are connected. Then, as shown in FIG. 1D, selectors 8a and 8b are provided between the multiplexer 4 and the read line memories 2b and 3b, and one of the output terminals is selected and activated. The multiplexer integrates input data, and the driver is a driver having the above-described two stages, six stages, or other stages. The selectors 8a and 8b are set so as to select any one of the output terminals in accordance with the number of pixels and the control method of the incorporated LCD before being incorporated into the LCD.
[0043]
The first output terminal Out1 is an output terminal used as the output terminal of the above-described embodiment, and is an output terminal when all 400 words of the line memories 2b and 3b are used. The output terminal Out1 is used when the horizontal 800 pixel SVGA is divided into two horizontal regions as in the first embodiment, or when the horizontal 1600 pixel UXGA is divided into four horizontal regions as in the second embodiment. .
[0044]
The second output terminal Out2 outputs from the 320th address of the line memory. That is, the number of words of the line memory used in this case is 320 words, and the memory area from the 321st address to the 400th address is not used. When a horizontal 640 pixel VGA is divided into two horizontal regions, or when a horizontal 1280 pixel SXGA is divided into four horizontal regions, the output terminal Out2 is used.
[0045]
The third output terminal Out3 outputs from the 256th address of the line memory. That is, the number of words of the line memory used in this case is 256 words, and the memory area from the 257th address to the 400th address is not used. When the horizontal 1024 pixel XGA is divided into four horizontal regions, the output terminal Out3 is used.
[0046]
The position of the output terminal is not limited to the above example. For example, if an 800-pixel SVGA is divided into four horizontal regions, the required number of words is 200 words. In this case, an output terminal is provided at the 200th address. In addition, it is only necessary to provide output terminals at all addresses that are assumed to be necessary.
[0047]
Further, the total number of words in the line memory is not limited to 400 words. For example, when XGA is divided into two horizontal regions, the total number of words in the line memory is 512 words. For this purpose, a line memory having a total word number of 512 words is required. A plurality of similar output terminals may be provided in the middle.
[0048]
The position where the output terminal is provided may be connected to an arbitrary address as required. For example, 1/4 of SXGA and 1/2 of VGA are the same 320, UXGA 1/4 and SVGA. The same half is 400. When a video signal is processed by a computer or the like, 256 pixels are one standard. In other words, the current display device standard is often a multiple of 256, 320, or 400, and it is considered that this will be followed in the future. Therefore, by providing an output terminal at an address having a number of words that can store data for 256, 320, and 400 pixels, the possibility of being compatible with display devices having various numbers of horizontal pixels is increased. High control circuit. In this specification, the significance of setting the number of words in the line memory to 400 is this point. That is, if 400 words are set as the number of words in the line memory, any of the above-described 256, 320, and 400 pixels can be flexibly handled. Further, the number of pixels is often set in units of 256 times 512 pixels. Therefore, if the number of words in the line memory is 512, for example, any of the above numbers of pixels can be handled. Needless to say, however, the circuit area increases as the number of words increases, so it is better to keep the number of words in the line memory to the minimum necessary.
[0049]
Further, instead of providing the selectors 8a and 8b, unnecessary output terminals may be destroyed by laser irradiation or the like.
[0050]
By the way, as shown in FIG. 8A, when the horizontal two regions are divided, voltages are applied sequentially from the leftmost pixel. (Hereinafter, the scanning direction from left to right is called forward scanning, and the right to left scanning is called reverse scanning.) When forward scanning is performed in two areas, the left area is the last pixel in the center of the screen, and the right area is the screen. A voltage is first applied to the center pixel. This application time difference causes a luminance difference in the center of the screen, which degrades display quality. Therefore, if a voltage is applied to the center of the screen at the same timing by performing reverse scanning on either the left or right area as shown in FIGS. 8B and 8C, this luminance difference does not appear.
[0051]
For this purpose, each read line memory in FIG. 1A has Out4. Out4 is an output terminal that outputs from the first address of the read line memory. The output from Out4 is serially output in reverse order from the first address, contrary to Out1 to Out3. Then, the selectors 8a and 8b in FIG. 1D select one of the output terminals Out1 to Out4. When the selectors 8a and 8b select Out4, the data line selector accordingly selects the pixels in the reverse order.
[0052]
An example of controlling a three-phase, six-phase LCD in two horizontal regions will be described with reference to FIGS. Assume that the selector 8a selects A-Out1, and the selector 8b selects B-Out4. When a video signal is input to the multiplexer 1, the first half video signal is stored in the write line memory 2a and the second half video signal is stored in the write line memory 3a, and transferred to the read line memories 2b and 3b, respectively, as in the first embodiment. Is done. The multiplexer 9 reads data for three pixels from the respective read line memories 2b and 3b. Here, the data at the 400th, 399th and 398th addresses are read from the read line memory 2b, and the first, second and third data are read from the read line memory 3b. Based on these data, the driver 10 sequentially generates pixel voltages V1 to V6 and outputs them to the LCD of FIG. The data line selector 16 'selects six data lines connected to the left and right ends 12a and 12A. As a result, V1, V2, and V3 generated from the data at the 400th, 399th, and 398th addresses of the read line memory 2b via the three data lines connected to 12a are 1, 2, and 3 columns, respectively. Applied to the pixel electrode of the eye. In addition, V6, V5, and V4 generated from the data of the first, second, and third addresses of the read line memory 3b via three data lines connected to 12A are 800, 799, and 798 columns, respectively. Applied to the pixel electrode of the eye.
[0053]
After 6 shift clock cycles, the data of the 400th, 399th, and 398th addresses of the read line memory 2b (397, 396, and 395th addresses immediately after parallel transfer) and the first and second addresses of the read line memory 3b are read again. The data of the second and third addresses (the fourth, fifth and sixth) are read out, and the pixel voltage generated based on these is transmitted via the six data lines connected to 12b and 12B. This is applied to the pixel electrodes in the fifth, sixth, 897, 896, and 895th columns.
[0054]
The display control in FIG. 8C can be performed by repeating the same in the following.
[0055]
The display control in FIG. 8B can be performed in substantially the same manner when the selector 8a in FIG. 1D selects A-Out4 and the selector 8b selects B-Out1, respectively.
[0056]
Next, the read operation from the read line memories 2b and 3b when performing the reverse scan will be described more specifically with reference to the timing chart of FIG. First, until the timing A, the parallel transfer from the write line memories 2a and 3a to the read line memories 2b and 3b is completed, and pixel data for one horizontal line is stored together with the read line memories 2b and 3b. To do. When the shift clock becomes high at timings A, B, and C, the 2b read clock input to the read line memory 2b becomes high at each timing in synchronization therewith. Then, the readout line memory 2b sequentially outputs the data of the pixels 1, 2, and 3. During this time, the memory selection signal is continuously high, the multiplexer 9 in FIG. 1 (d) selects the output of the readout line memory 2b, and the data of the pixels 1, 2, and 3 are sequentially sent from the multiplexer 9. Is output. Next, at the timings D, E, and F, the 3b read clock input to the read line memory 3b becomes high at each timing in synchronization therewith. Then, the readout line memory 3b outputs the data of the pixels 800, 799, and 798. During this time, the memory selection signal is continuously low, and the multiplexer 6 selects the read line memory 3b and outputs this data. Next, at timing G, the 2b readout clock goes high, and similarly, the data of the pixel 4 is output from the multiplexer 6. Although not shown, from timing G, the driver 7 outputs voltages corresponding to the data of the pixels 1, 2, 3, 800, 799, and 798 as the control voltages V1, V2, V3, V4, V5, and V6. . The outputs V1 to V6 are continuously output for 6 shift clock cycles. Thereafter, the read operation continues similarly.
[0057]
The point of this embodiment is that it is possible to control an LCD that performs reverse scanning without changing the control circuit simply by changing the selection of the selectors 8a and 8b. Therefore, the same control circuit can be used for LCDs that perform reverse scanning and LCDs that do not, and manufacturing costs can be reduced.
[0058]
By the way, an electronic view finder (EVF) or the like such as a digital video camera can invert the EVF and direct the EVF display area to the photographing lens side in order to photograph the photographer himself. is there. The mainstream of EVF display at this time is a mirror image in which left and right are reversed. According to the LCD control circuit of the present invention shown in FIGS. 1A and 1D, such a mirror image display can be handled. The mirror image display control operation will be described below.
[0059]
When a video signal is input to the multiplexer 1, the first half video signal is stored in the write line memory 2a and the second half video signal is stored in the write line memory 3a, and transferred to the read line memories 2b and 3b, respectively, as in the first embodiment. Is done. Now, the selector 8a selects A-Out1, and the selector 8b selects B-Out4. The multiplexer 9 first reads the output of the selector 8b first, and then reads the output of the selector 8a. Therefore, the data is read in the order of the 400th, 399th and 398th address data of the read line memory 2b and the first, second and third address data of the read line memory 3b. Based on these data, pixel voltages V1 to V6 are generated in order. This is applied to the LCD of FIG. Initially, six data lines 12a and 12A are selected as described above. The pixel electrodes in the first, second, third, 798, 799, and 800th columns are sequentially provided with data at addresses 400, 399, and 398 of the read line memory 2b, and third, second, A pixel voltage generated based on data at one address is applied.
[0060]
Next, through the six data lines connected to 12b and 12B, the fourth, fifth, sixth, seventh, seventh, 796th, and seventh 95th pixel electrodes are sequentially accessed at the 400th, 399th, and 398th addresses (the read line memory 2b). Immediately after the parallel transfer, a pixel voltage generated based on data of 397, 396, and 395 addresses) and data of the third, second, and first addresses (sixth, fifth, and fourth addresses) of the read line memory 3b is applied. The mirror image display can be controlled by applying in the same manner.
[0061]
For switching between normal display and mirror image display, for example, an output circuit for outputting a mirror image signal for displaying a mirror image when the EVF is rotated is provided, and the operation of the control circuit is switched accordingly. .
[0062]
Next, the read operation from the read line memories 2b and 3b when performing mirror image display will be described more specifically with reference to the timing chart of FIG. 10 is different from the timing chart of FIG. 10 in that the read clocks 2b and 3b are switched and the phase of the memory selection signal is reversed. First, until the timing A, the parallel transfer from the write line memories 2a and 3a to the read line memories 2b and 3b is completed, and pixel data for one horizontal line is stored together with the read line memories 2b and 3b. To do. When the shift clock goes low at timings A, B, and C, the 3b read clock input to the read line memory 3b goes high at each timing in synchronism with this. Then, the readout line memory 3b sequentially outputs the data of the pixels 800, 799, and 798. During this time, the memory selection signal is continuously low, the multiplexer 9 in FIG. 1D selects the output of the readout line memory 3b, and the data of the pixels 800, 799, and 798 are sequentially sent from the multiplexer 9. Is output. Next, at the timings D, E, and F, the 2b read clock input to the read line memory 2b becomes high at each timing in synchronization therewith. Then, the readout line memory 2b outputs the data of the pixels 1, 2, and 3. During this time, the memory selection signal is continuously high, and the multiplexer 9 selects the read line memory 2b and outputs this data. Next, at timing G, the 3b read clock goes high, and similarly, the data of the pixel 797 is output from the multiplexer 9. Although not shown, from the timing G, voltages corresponding to the data of the pixels 800, 799, 798, 1, 2, and 3 are output from the driver 10 as control voltages V1, V2, V3, V4, V5, and V6. . The outputs V1 to V6 are continuously output for 6 shift clock cycles. Thereafter, the read operation continues similarly.
[0063]
The above description has been described separately for each driving method for easy understanding, but by combining each driving method into a single control circuit,
(1) Various number of pixels
(2) Reverse scan
(3) Mirror image display
Any one of the display methods can be handled by a single control circuit. That is, for example, the control circuit of FIG. 1B omits the selectors 8a and 8b, and the driver 5 is a multi-stage driver 10 that does not use the third and subsequent terminals.
[0064]
Further, the above description has been made with a monochrome display device for easy understanding, but it can of course be applied to a color display device. In this case, as many memory units as the product of the number of areas to be divided and the number of primary colors for color display are required. For example, when there are data of three colors of RGB and divided and displayed in two horizontal regions, two memory units are required for three colors, that is, a total of six memory units.
[0065]
In the above embodiment, the LCD is used as an example of the display device, but the present invention is not limited to this. For example, if the display device uses an organic EL (Electro Luminescence) element, the control signal is not “the voltage V1 applied to each pixel electrode” but “the voltage applied to the organic EL element of each pixel”. A display device using a cathode ray tube (CRT) can be read as “electron acceleration voltage” or the like and used as a control circuit for various display devices.
[0066]
【The invention's effect】
As described above, according to the present invention, the first storage device input serially and the second storage device in which the storage contents are transferred in parallel are provided, and a plurality of predetermined storage devices of the second storage device are provided. Since the memory unit that serially outputs from a plurality of output terminals provided in the address is provided, it is possible to cope with various control methods LCD having various numbers of pixels. Therefore, the manufacturing cost can be kept low.
[0067]
In addition, since the output terminal of the readout line memory is provided at an address having a number of words that can store data for 256 pixels or / and 320 pixels or / and 400 pixels, VGA, XGA, SXGA, etc. This is not only convenient for dividing control with an existing display method, but is also likely to be compatible with a display method to be adopted in the future.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a control circuit of the present invention.
FIG. 2 is a diagram showing a display device for horizontal two-region single-phase display.
FIG. 3 is a data output timing chart of the control circuit of the present invention.
FIG. 4 is a block diagram showing another embodiment of the present invention.
FIG. 5 is a diagram showing a display device for horizontal four-region single-phase display.
FIG. 6 is a diagram illustrating a display device for horizontal two-region three-phase display.
FIG. 7 is a data output timing chart of the control circuit of the present invention.
FIG. 8 is a diagram for explaining reverse scanning;
FIG. 9 illustrates a display device that performs reverse scanning.
FIG. 10 is a timing chart of data output of the control circuit of the present invention.
FIG. 11 is a data output timing chart of the control circuit of the present invention.
FIG. 12 is a diagram showing a conventional active matrix LCD and its control circuit.
FIG. 13 is a diagram showing a conventional 2-phase display LCD and its control circuit.
FIG. 14 is a diagram showing a conventional LCD for horizontal two-region single-phase display and its control circuit.
[Explanation of symbols]
1, 4, 6: Multiplexer, 2, 3, 22, 23, 24, 25: Memory part
2a, 3a: write line memory, 2b, 3b: read line memory
5, 7, 10: Driver

Claims (7)

A control circuit that receives a digital video signal and controls the display device based on the digital signal.
A dividing unit for dividing the digital video signal according to a predetermined rule;
A plurality of memory units each storing the divided digital video signals;
A driver that converts the output of the memory unit and outputs a control signal of the display device;
The memory unit includes a write line memory having a predetermined number of words to which the divided digital video signal is serially input, a read line memory in which the contents of the write line memory are transferred in parallel, and the read line memory are different. A display circuit control circuit comprising: a plurality of output terminals respectively connected to a plurality of addresses; and outputting serially from one of the output terminals. Dividing the screen of the display device into a plurality of regions in the horizontal direction and controlling the screen;
The display device control circuit according to claim 1, wherein the number of the memory units is equal to the number of divisions in a horizontal direction. The number of the memory units is a product of the number of regions dividing the screen in the horizontal direction and the number of display primary colors of the display device,
The display device control circuit according to claim 2, wherein the digital video signals of different regions or different primary colors are input to each of the memory units. 2. The display circuit control circuit according to claim 1, wherein one of the output terminals of the readout line memory is provided at an address having a number of words sufficient to store data for 256 pixels. The display device control circuit according to claim 1, wherein one of the output terminals of the readout line memory is provided at an address having a number of words sufficient to store data for 320 pixels. The display device control circuit according to claim 1, wherein one of the output terminals of the readout line memory is provided at an address having a number of words sufficient to store data for 400 pixels.   7. The display device control circuit according to claim 1, further comprising a selector for selecting one of the plurality of output terminals.

Images