JPH03153299A - Image processor - Google Patents

Abstract

PURPOSE:To display an enlarged or reduced image of optional magnification in an optional area on a screen without using any complex hardware by reading display control parameters out of a memory in synchronism with a raster scan on the screen and controlling access to an image memory. CONSTITUTION:The display control parameters which specify the correspondence between the screen of a display device 18 and image data in the image memory 15 in dot units are stored in a display control memory 12 in the form of a table. Then corresponding display control parameters are referenced in synchronism with the raster scan on the screen to control a read of the image memory 15. Consequently, the position and size of a display area are easily set and superposition and thinning-out positions of dots for enlargement and reduction are easily specified however they become complicated with the value of magnification.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an image processing device that can display moving images and still images useful for audiovisual information systems in any area on a display screen in any size.

An image that can be enlarged or reduced at any magnification in any area on the screen without using complicated hardware, and that does not cause double images even when displaying moving images. The purpose is to provide processing equipment.

In an image processing device using a display device.

an image memory for storing image data of dot images;
a display control memory that stores display control parameters including horizontal and vertical addresses of dot data to be read from the image memory for each dot position on the iI surface of the display device and a display bit that indicates whether single-screen display is possible; and a raster of the display device. The present invention has a configuration including a scan address generation circuit that generates horizontal and vertical scan addresses for reading and accessing the display control memory in synchronization with scanning.

[Industrial application field]

The present invention relates to an image processing device that can display moving images and still images useful for audiovisual information systems in any area on a display screen in any size.

(Problems to be solved by conventional techniques and inventions) Audiovisual information systems that use real images for learning training, advertising, etc. have been attracting attention recently. A screen is created by arbitrarily combining still images such as output data and moving images such as small AV output from video equipment, and the screen contents are changed according to the user's corresponding operations.

For example, audio-visual information for equipment operation training includes screens and audio that combine real images of the five equipment and messages about the names of the operation points of the 11I equipment, the order of equipment operation, what to do in the event of a failure, etc., depending on each training stage. It is composed of

The real image may be a moving image if necessary.

Also, depending on the screen configuration, image enlargement, S* reduction, and display area changes are performed as appropriate.

When enlarging or reducing an image, it is achieved by accessing the vertical and horizontal addresses redundantly according to the respective magnifications according to the raster scanning of 8 screens (enlargement), or by thinning out and accessing by one (reduction). There is. For example, to enlarge by 2 times, each dot is read out twice in the vertical and horizontal directions, and to reduce it by half, one dot is thinned out every two dots in the vertical and horizontal directions. .

In conventional image processing devices, when a separate CPU calculates a magnification constant from the position and size of the screen display area and the position and size of the data area to be displayed, and sends this to the image processing device, this magnification constant is is added at each rask and dot timing to obtain the next address. For example, if the magnification constant l/1, 25 = 0.8, then 0.8 to 1.6. L4゜3.2.4.0.4.8. The raster address is obtained by sequentially calculating... and converting it into an integer.

Since such a magnification constant is set in the magnification register and calculated, it becomes a fixed magnification such as 1/256 unit.
It was not possible to enlarge or reduce the display at an arbitrary magnification such as raster units. Further, in the conventional device, it was necessary to separately provide a magnification register, an adder, and the like. In particular, with conventional systems that perform interlaced scanning of the display screen using a 1-frame, 2-field method, double images occur between fields when a moving image is enlarged or reduced, resulting in a moving image. There was also the problem that comb-shaped noise appeared in some parts.

Furthermore, in conventional systems, the data in the image memory is read out in synchronization with the scanning of the screen of the display device, so it is not possible to read in advance the data of later rasters. It was not possible to perform a reduced display that required 100% of data. However, if reduced image data is thinned out and stored in an image memory in advance, reduced display is possible, but if enlarged display is performed from the data in the image memory, there is a drawback that the display quality deteriorates. One possible solution to this drawback is to provide two image memories, one for reduced display and one for enlarged display, but in this case, a problem arises in that the amount of hardware increases significantly.

The present invention is capable of displaying an image enlarged or reduced at an arbitrary magnification in an arbitrary area on a screen without using complicated hardware, and even when displaying a moving image.
It is an object of the present invention to provide an image processing device that does not generate double images.

[Means to solve the problem]

The present invention provides a memory that stores display control parameters that specify whether or not to read dot data from an image memory in which an original image is stored and an access position of the dot data, and displays the display control parameters stored in this memory. Access to the readout 1 image memory is controlled by synchronizing the n parameter with the raster scanning of the screen. As a result,
This makes it easy to associate any dot in the original image with any position on the screen, and eliminates the complicated overlap of dots that is required when enlarging or reducing an image at any magnification. j [Enables reading and thinning reading.

Furthermore, when enlarging or reducing a moving image, double images are generated by displaying the same image content in two connected fields using interlaced scanning, or by displaying only one field.

FIG. 1 is a block diagram illustrating the principle of the present invention.

In FIG.

10 is an image processing device according to the present invention.

11 is an MPU that calculates display control parameters for enlarging and reducing.

Reference numeral 12 denotes a display control memory that stores nine display control parameters in dot correspondence.

13 is a scanning address generation circuit that generates a scanning address for the display control memory 12; a counter A that counts the number of dots in the horizontal direction using a display dot clock;
It includes a counter B that counts the number of rasters in the vertical direction using a horizontal synchronization signal, and a toggle circuit C. Since screen scanning is performed in an interlaced scanning method of 1 frame and 2 fields, the vertical scanning address is set for each field. It is necessary to alternately generate sequences of only even addresses and only odd addresses.The toggle circuit C shown in the figure generates the least significant bit of the vertical scan address that defines even and odd numbers, and the upper bit of the vertical scan address. Display control memory 1 in combination with the value of counter B that constitutes the bit
2.

Further, the value of the counter A is directly supplied to the display control memory I2 as a horizontal scanning address.

Reference numeral 14 denotes a mode control circuit having two operating modes: a frame mode when displaying a still image and a field mode when displaying a moving image, and a toggle circuit C of the scanning address generation circuit 13.
In normal frame mode, the toggle circuit C is controlled to control the lowest bit of the vertical scanning address output from 0 for each vertical synchronization signal.

That is, O" and "1" are inverted for each field, and in field mode, it is fixed to either 0" or "1".

Reference numeral 15 denotes a word-structured image memory, in which image data from the video equipment is stored as a dot image based on a write address supplied from the MPU 1l.

Reference numeral 16 denotes a succession section that stores the word data read out from the two-image memory 15 and selectively outputs necessary dot data.

Reference numeral 17 denotes an analog section which A/D converts the dot data and outputs it as an analog format image data signal.

1B is a 9 display device.

Reference numeral 19 denotes a CPU having a function of setting the position and size of the display area 9.

Reference numeral 20 denotes an image superimposing section which combines the image data signal outputted from the analog section and a character data signal such as word processing data prepared separately in a raster format and supplies the synthesized signal to the display device.

The display control parameters corresponding to the screen dots in the display control memory 12 include a vertical scanning address and a horizontal scanning address that instruct the position of dot data to be read out from the one-image memory 15, and a sequence that instructs whether word data is to be read out from the one-image memory 15. It includes a bit and a display bit that indicates whether 8 display is to be performed, that is, whether the dot is in the display area or in the non-display area.

The vertical scanning address and the succession bit are supplied to the image memory 15, and the dot data of the raster line designated by the vertical scanning address is read out to the succession unit 16 in word units at a timing based on the instruction of the succession bit. Since the word data includes a plurality of dot data, reading is performed once for each plurality of dot positions.

The horizontal address is supplied to the succession section 16, which selectively outputs the corresponding dot data.

The display bit is supplied to the analog unit 17, and outputs analog data to the display device 18 only when one display is instructed.

[Effect]

The present invention will be explained in detail using FIG. 1 and FIG. 2.

First, it is assumed that the image memory 15 stores predetermined image data.

The CPU 19 selects a data area S to be displayed, as shown in FIG. ) and determine the display area S' as shown in 1
Set to MPU1l of image processing device flo.

The MPU II calculates the magnification of enlargement and reduction from the position and size of the data area S in the image memory 15 and the position and size of the display area S' on the screen of the display device 18, and calculates the magnification of each raster of the two display devices 18. For each dot position therein, it is determined whether it is inside or outside the display area S', and if it is inside, the dot data is stored in the image memory 15, taking into account duplication and thinning determined by the magnification of enlargement and reduction. Calculate the address in display control memory 1 as 1 display control parameter.
Store in the corresponding address of 2. The address of this display control memory 12 corresponds to the dot position on the screen of the display device 18, and is accessed by the scan address generated from the scan address generation circuit 13 according to the raster scan of the 9 screens, and the 9 display control parameters are read out. .

In this way, in the present invention, the display control parameters that give the correspondence between the screen of the display device 18 and the image data in the image memory on a dot-by-dot basis are tabulated and stored in the display control memory. It is easy to set the position and size of one display area because the readout of the image memory is controlled by referring to the corresponding display control parameters in synchronization with the raster scanning of the i-side.
Expanded again.

No matter how complicated the position of dot duplication or thinning due to reduction becomes depending on the magnification value, it is possible to easily specify the position.

Next, when displaying a moving image, the mode system 81 circuit 14
by setting it to field mode and fixing the least significant bit of the vertical scan address to, for example, l1tll, a sequence of odd vertical scan addresses, 1.3, 5, 7, .・
... are supplied to the image memory 12. For this reason, the same display control parameter string is read out in each field and the same dot data group in the image memory 15 is accessed, so double images do not occur between two fields in a frame that are interlaced. It disappears. However, the resolution will be half that of normal frame mode.

In the configuration shown in FIG. 1, the mode control circuit 14 operates the lowest bit of the vertical scan address for the display control memory 12; A similar effect can be obtained by manipulating the bits so that, for example, the least significant bit is always held at "l" in field mode.

〔Example】

Next, based on the basic configuration of the present invention shown in FIG.
An embodiment will be described with reference to FIG. 1 and FIGS. 3 to 13.

FIG. 3 shows an operation cycle of one image processing device IO, including one display side <8 parameter setting cycles and a display cycle.

(1) Six.

When the position and size of the display area on the screen are determined by the user, one display control parameter setting cycle is started. First, from cr'u l 9 to MPU 11,
As shown in FIGS. 4(a) and (b).

Horizontal and vertical position X of display data area S of image memory 15
i, Yi, horizontal and vertical widths Wi, H4 and 9 horizontal and vertical positions Xd of the display area S' of the display device.

Send each setting value of Yd, horizontal width, vertical width Wd, and Hd.

(2) In the display control parameter setting cycle of 6'perme, the primary MPU
II is based on each setting value sent from the CPU 19.
Display control parameters at the time of enlargement and reduction are calculated by a method to be described in detail later and stored in the display control memory 12. After this 1
Enter the cycle to display.

(3) Address counter A counts the number of dots by adding 1 for each display dot clock, and returns to zero (RS) when receiving a horizontal synchronization signal.

Counter B and toggle circuit C are set to 1 for each horizontal synchronization signal.
is added to count the number of rasters, and returns to zero (R3) when a vertical synchronizing signal is received.

(4) 6' The display control n memory 12 of memo 1 consists of a horizontal display control parameter holding section and a vertical display control parameter holding section, as shown in FIG. The former is specified by the output of counter A, and the latter is specified by the output of counter B (and toggle circuit C).

The address of the vertical display control parameter holding section specified by the output of counter B is obtained by adding the maximum value of the output of counter A to the output of two counters A as an offset.

The display control memory 12 is used to write vertical/horizontal display control parameters calculated from the MPU.

Any address specified by counter A or counter B can be specified.

(5) The bottom image memory 15 has a serial port output that is automatically read out when a continuous signal is issued after specifying the readout start address. It must be structured to read out a plurality of dots at the same time, where the plurality of dots is a value of 2 to the power of m, and 1m is an integer value. If the maximum value in the horizontal direction is represented by
*Represented by X1+x.

Further, when the number of simultaneously read dots is M, Xl is a multiple of M.

(6) The bottom analog section 17 has a function of not outputting the digital signal of the continuation section 16 read from the II image memory if there is a 9 display prohibition signal, or converting it directly into an analog signal if there is not. have.

(7) M stand variable I [L When entering the display cycle, the display control memory 12.

First, the vertical direction display control parameter is read out during the horizontal retrace time of one display device using the output of the counter B that counts the raster as the address.
As shown in the figure, it consists of a display bit and an image memory successive start address.

Control begins with the display bit. If the display bit is non-display, the display operation at the current raster position is stopped, and if the display bit is 1 display, then ! The i-image memory image memory successive start address is designated and the process moves to horizontal direction display control.

The horizontal scanning timing of the display device is shown in FIG.

(8) Water 1'/% makeup n When the horizontal retrace time shown in FIG. 7 has passed, the process shifts to the horizontal direction display control cycle.

During the horizontal display control cycle, the horizontal display control parameters are read using the output of counter A, which operates in accordance with the dot clock, as an address.

As shown in FIG. 8, the horizontal display control parameter is composed of a successive bit, a display bit, and a successive data selection bit.

The function of each bit is as follows.

・At a dot timing with successive bits, readout of one image memory is instructed.

- When the display bit is not displayed, the analog section prohibits display, and when 1 is displayed, the analog section displays.

- The selection bit selects successive dots when reading multiple dots from the image memory at the same time.

・If you select the same dot consecutively, it will be enlarged.

If you remove the memory dot, the display will be reduced.

- The number of selected bits is a base-2 logarithm of the number of bits simultaneously read from the image memory.

- If the image memory successive tracking speed allows, the reduction ratio can be reduced to 1/M, where M is the number of simultaneous successive bits.

(9) The display magnification of -Parme is calculated by HD/H1, but calculate the reciprocal of the 9 display magnification 5-H1/HD and add this S to the vertical display address of the image memory sequentially to set the vertical display address. calculate. Note that the number of decimal digits for the decimal part of S is determined by considering the maximum number of rasters and precision.

l) Raster N[lO~(Yd-1) Hide display bits. The address part can be any value since it is ignored.

2) Display the raster depth Yd to (Yd+Hd-1) display bits.

The start address in raster NaYd is Yi *XI+
The starting address in the raster NtlYd+q is indicated by Yi *XI+Xi +Q*Xi. Here, Q is the integer part of S*q.

3) Hide the raster hh (Yd + Hd) to YD display bits. The address part can be any value since it is ignored.

(10) - The display magnification of Perme is calculated as WD/Wl, but the reciprocal of 1 display magnification is calculated as 5-Wl/WD.The decimal part of S is a decimal number considering the maximum number of dots and precision. Determine the number of digits.

1) Dotsose O~ (Xd-1) Hide display bits.

Since the selection bit part and the successive bit part are ignored, any value may be used.

2) F7 tNaXd ~(Xd +Wd 1
) Set the display bit to display.

The value of the selection bit at dot HaXi is indicated by the lower m bits of binary number Xi, and the value of the selection bit at dot NnXd+p is indicated by the lower m bits of binary number (Xi +p). Here, P is the integer part of S*P.

The continuation bit indicates continuation of one image memory when the value excluding the first and lower m bits of the binary number P changes.

3) Raster NQ (Xd + Wd) to hide the XD display bits.

Since the selection bit part and the successive bit part are ignored, any value may be used.

A specific example of display control will be explained using FIGS. 9 to 13.

FIG. 9 shows an example of area setting for display control in the one-image memory 15 and the display device 18, respectively.

The display data area S of the image memory 15 is given by the horizontal position -100, the vertical position -35, the horizontal width -480, and the vertical width -380, and the display area S' of the second display device 18 is given by the horizontal position -35.
270 Vertical position - 100 Horizontal width = 672 Vertical width - 532 Given.

Figure 10 shows the correspondence of vertical addresses (number of rasters) between the image memory and the display screen when the area settings shown in Figure 1 are made, and Figure 11 shows the correspondence of horizontal addresses (number of dots). There is. That is, on the display screen, the vertical address is 100
~631. Horizontal addresses 270 to 941 are the display range, which corresponds to vertical addresses 35 to 4 of the image memory, respectively.
It is associated with display data in the range of 14° horizontal addresses 100 to 579. This requires a magnification of 1.4.

FIG. 12 shows part of the contents of display control parameters set in the display control memory based on the address correspondence shown in FIGS. 1O and 11. Note that here, the vertical address of the display screen is represented by a raster line, and the horizontal address is represented by a raster line.

In FIG. 12(a), the display bit "1" is set only in the 0 display screen display raster Na1OO to 631 indicating one parameter of vertical direction display control, and each raster bar is set to 1 in each of the image memory addresses 35 to 414. The maps are mapped with overlap for 4x magnification.

FIG. 12(b) shows the horizontal direction display control parameters.
Display bit “l” only on display dots Na270 to 941
is set, and the image memory addresses lOO to 579 are associated with each other including overlap for 1.4 times enlargement. As for the bits that keep coming.

The case is shown in which the number M of bits that are simultaneously output from the image memory is 8, and one selection bit specifies a selection position among each of the 8 bits.

(a), (b), and (c) in Figure 13 are each 1.0
For the cases of 2x, 1.25x, and 0.8x, the raster magnets (vertical addresses) for reading out the image memory corresponding to the raster depths of the 9 display screens are shown in each operation mode of frame mode and field mode. It is something.

How to switch between frame mode and field mode.

This can be done automatically in conjunction with the switch that selects the output of the video equipment.

Next, an embodiment of the image superimposing section 20 shown in FIG. 1 will be described using FIGS. 14 and 15.

FIG. 14 is a diagram showing the circuit configuration of the image superimposing section.
IO is an image processing device, and 17 is an analog section.

20 is an image superimposing unit, 21 is a CPU, 22 is a delay circuit, 2
3 is a NOR circuit, and 24 is an analog gate.

25 is an OR circuit.

Further, FIG. 15 is an operational waveform diagram of the circuit shown in FIG. 14, and the reference numbers ``■'' to ``■'' in the two figures indicate the correspondence between the nine circuits and the waveforms. The operation of the circuit shown in FIG. 14 will be explained below with reference to FIG.

The CPU 21 converts the character data signal ■' of the character data "A" shown at the top of FIG.
Output in GB format. At this time, the CPU 21 sets the non-black signal ■ to "1" when all of RGB are non-zero.
On the other hand, an image data signal (2) is output from the analog section 17 of the first image processing device 1O.

The non-black signal ■ output from the CPU 21 is sent to the delay circuit 22.
and is added to one input of the NOR circuit 23.

The delay circuit 22 delays the non-black signal (2) for a certain period of time and sends the signal (2) to the other input of the NOR circuit 23.

The NOR circuit 23 performs a NOR logic on the signals ■ and ■ to create a signal ■ and applies it to one input of the analog gate 24 . The analog section 1 is connected to the other input of the analog gate 24.
An image data signal (2) output from 7 is added. Analog gate 24.

Gating the signal ■ with the signal ■ and outputs the resulting signal ■.

The OR circuit 25 performs analog synthesis of the signals ■' and [F] to generate a signal ■ and outputs it to the display device 9.

As a result, when a 9-character data signal exists, the image data signal is prohibited, and as indicated by the shaded area in the waveform of signal A shadow is formed on the right edge of The character data that is shaded in this way has the same color as the background color of the image data that is superimposed with zero.

It becomes easier to see.

〔Effect of the invention〕

According to the present invention, the display data area of the 0-image memory and the display area of the screen are associated in units of dots.

This is easily realized using control display memory, and it is possible to use arbitrary magnification in raster units, eliminating the need for conventional hardware such as magnification registers and adders, and the restriction of fixed magnification. Like a lens effect that increases the magnification of the outer part and lowers the magnification of the outer part, the area on the screen is magnified.

It is easy to arbitrarily change the reduction magnification.

More sophisticated image processing can be achieved at lower cost than conventional methods.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the basic configuration of the present invention, Fig. 2 is an explanatory diagram of the operation of the present invention, Fig. 3 is an explanatory diagram of the operation cycle of the embodiment, Fig. 4 is an illustration of setting values of the area, and Fig. 5 is an explanatory diagram of the operation cycle of the embodiment. FIG. 6 is a configuration diagram of the display control memory, FIG. 6 is a configuration diagram of vertical display control parameters, FIG. 7 is an explanatory diagram of the horizontal scanning timing of the display device, FIG. 8 is a configuration diagram of horizontal display control parameters, and FIG. 9 is a configuration diagram of horizontal display control parameters. An explanatory diagram of the area setting side of display control, Fig. 1O is an explanatory diagram of address correspondence in the vertical direction, Fig. 11 is an explanatory diagram of address correspondence in the horizontal direction, Fig. 12 is an explanatory diagram of an example of the contents of the display control memory, and Fig. 13 is an explanatory diagram of the address correspondence in the horizontal direction. FIG. 14 is an explanatory diagram of the correspondence between display rasters and read rasters in frame mode and field mode at various magnifications, and FIG. 14 is a circuit configuration diagram of an image superimposing section. FIG. 15 is an operational waveform diagram of the circuit of the image superimposing section. 1O in FIG. 1: Image processing device 11: Mpu 12: Display control memory 13: Scanning address generation circuit 14: Mode control circuit 15: Image memory 16: Continuation section 17: Analog section 18: Display device 19: cPU 20: Image Superimposed part

Claims (4)

[Claims] (1) In an image processing device using a display device, an image memory that stores image data of dot images, horizontal and vertical addresses of dot data read from the image memory for each dot position on the screen of the display device, and whether or not the screen can be displayed. a display control memory that stores display control parameters including display bits that instruct the display, and a scan address generation circuit that generates horizontal and vertical scan addresses for reading and accessing the display control memory in synchronization with raster scanning of the display device. An image processing device comprising: (2) When the image processing device according to claim 1 is used in an interlaced scanning method with two fields per frame, an operation mode used when displaying a moving image is provided, and in this operation mode, two fields in each frame are 1. An image processing apparatus characterized in that a display control memory is accessed by generating scanning addresses of only one of odd or even address sequences in any of the fields. (3) When the image processing device according to claim 1 is used in an interlaced scanning method with two fields per frame, an operation mode used when displaying a moving image is provided; 1. An image processing device that converts a vertical address supplied from a display control memory to an image memory in any one of two fields into an odd numbered or an even numbered address. (4) In the image processing device according to any one of claims 1 to 3, when the image data signal and character data signal for each raster are superimposed and displayed on a display device, the character data signal for each raster is delayed for a certain period of time. A first means for synthesizing with the original character data signal and a second means for inhibiting the image data signal for each raster by the synthesized character data signal output from the first means are provided, and the character data is shaded. An image processing device characterized by displaying images.