SU1479926A2 - Device for displaying image on cathode ray tube screen - Google Patents

Abstract

The invention relates to automation and computing, can be used in devices for outputting alphanumeric and graphical information from a computer and is an improvement of the invention according to the author. N 1291956. The purpose of the invention is to increase the speed of the device. The device contains the first and second memory blocks, registers, two groups of prohibition elements, groups of elements AND, a group of elements OR, a control unit, a modulation unit, a CRT, a decoder, comparison units, elements AND, elements OR, prohibition elements with corresponding connections. mi In the mode of erasing an image or its part, the boundaries of the erasable area are entered into registers through elements AND groups. In the comparison blocks, erase pulse sequences are formed, corresponding to the erasable section, which control the prohibition elements, allowing the erase signals to pass to the memory blocks. 3 il.

Description

one

The invention relates to automation and computing and can be used in devices for outputting alphanumeric and graphic information from computers.

The purpose of the invention is to increase the speed of the device.

FIG. 1 and FIG. 3 shows a block diagram of the proposed device; Fig. 2 is a block diagram of the control unit.

The device contains the first block 1 of memory, the second block 2 of memory, the first register 3, the generator of 4 characters, block 5 of the permanent memory, shaper 6 raster line, block 7 of modulation, cathode-ray tube (CRT) 8, block 9 control, the first group of 10 elements AND, the second group 11 elements AND, the third group 12 elements AND, the group 13 elements OR, the second register 14, the first group 15 prohibition elements, the second group 16 prohibition elements, the third register 17, the first information input 18 of the device , outputs 19-30 of the control unit and input 31 of the control unit.

The control unit 9 contains a generator of 32 pulses, a counter 33 of the number of elements of decomposition of characters along the X coordinate, a counter 34 of the number of characters in the lines of the displayed symbolic information, a counter 35 of the number of elements of decomposition of symbols along the Y coordinate, a counter 36 of the number of lines of the displayed symbolic information, a decoder 37, block 38 memory of microinstructions (ROM), outputs 39-67 of the block 38 of memory of a microhill

3

CO SO

Yu

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Yu

mand, output 58 of the generator 32 synchronization pulses and outputs 69-74 of the counters of the control unit,

Reference numerals 75-78 indicate the connections between the elements of the device.

The device also contains the fourth group 79 of the elements And, the fourth register 80, the first comparison block 81, the tenth register 82, the first element And 83, the fifth group 84 of the elements AND, the fifth register 85, the second block 86 of the comparison, the first element OR 87, the sixth group of 88 elements And, the sixth

Reset the fourth sub-register, output 45 - signal Record the third sub-register, output 46 - signal

5 Reset the third sub-register, output 47 - signal Record the second sub-register, output 48 - signal Reset the second sub-register, output 49 - signal Record the first

Yu subregister, at output 50 - signal

Reset of the first sub-register, output 51 - signal General reset of register 3, output 52 - signal Read block 5, output 53 - signal register 89, third block 90 comparison, 5 signal Block 6 record, output 54 - eleventh register 91, seventh signal Beginning of a line, at the exit

Reset the fourth sub-register, output 45 - signal Record the third sub-register, output 46 - signal

Reset the third sub-register, output 47 - signal Record the second sub-register, output 48 - signal Reset the second sub-register, output 49 - signal Record the first

subregister, output 50 - signal

Reset of the first sub-register, output 51 - signal General register reset 3, output 52 - signal Read block 5, output 53 - signal 5 Write Block 6, output 54 - signal Beginning of the line, at output

a group of 92 elements And, the seventh register 93, the fourth block 94 comparison, the second element And 95, the second element OR 96, the second decoder 97, the eighth register 98, the third element And 99, the first element 100 prohibition, the twelfth register 101, the ninth register 102 , the fourth element And 103 the second element 104 prohibition, the third element OR 105 and the inputs 106-114,

During operation of the control unit 9, the generator of the synchronization pulses 32 generates pulses, synchronizing 1 ||; the operation of the entire device. From its output, the pulses arrive at the inputs of block 7 (output 68) and counter 33, and the transfer pulses from the second output of counter 33 arrive at the clock input of counter 34. The carry pulses from the second output of counter 35 arrive at the clock input of counter 36.

The status codes of the device from the first outputs of the counter 33 and 35 (outputs 69 and 72), the second outputs of the counters 34 and 36 (outputs 71 and 74) and the output of the register 14 (input 31) are fed to the inputs of the decoder 37 connected to the ROM 38,

With the help of a ROM 38 in which the codes of microinstructions are recorded, the signals controlling the operation of the device are generated.

On the first output 39 of the ROM, a signal is written. Record of memory block 2; at output 40, a signal is read of a block.

2pami, output 41 - signal Record of memory block 1, output 42 - signal Read memory block 1, output 43 - signal Record of the fourth sub-register of the first register

3 (register 3 consists of four sub-registers), output 44 is a signal

five

55- signal frame start, at the output

56- signal Reverse move on the line, on output 57 - signal Reverse

0 by frame, output 58 is a signal Reset of block 7, output 59 is a Ready signal to receive a code, output 60 is a signal Transfer for block 35, output 61 is a signal Reset

5 counters of block 9, output 62 - control signal of block 10, output 63 - control signal of block 11, output 64 - control signal of block 12, output 65 - signal Reset

0 block 17, output 66 .- signal Recording to the first discharge of block 17, output 67 - signal Recording to the second discharge of block 17.

The counters 34 and 36 form the addresses of the first memory block 1 (character memory) outputs 70 and 73, the counters 35 and 36 form the addresses of the second memory block 2 (raster memory) outputs 72 and 73. Additionally, the addresses generated by the counters 34 and 35, are used to control blocks 5 and b of the generator of 4 symbols (outputs 70 and 72).

From the outputs of the memory block 38, there are additionally pulses that control the first 10, second 11 and third 12 groups of elements AND (outputs 62-64) and control pulses with the third register 17 (outputs 66 and 67).

Block 9 implements four main

0 device operation modes and additional modes: erase and erase in the window.

The mode number that is currently being implemented records 5 seconds from the information input 113 of the device to the register 14 at its first input. The reset of register 14 is effected by a signal from the information input.

0

five

five

114 devices at its second input. Once upon a transition to a new mode of operation.

The device works as follows.

Through register 3 (the first sub-register) and a group of 16 prohibition elements, the character codes in the exchange mode with the information system (not shown) are fed to the input-first memory block 1. Here they are recorded in successive cells (in the order of arrival at its input) and according to the signals from the outputs of control unit 9 (in the raster generation mode) they are selected from memory block 1 and through the second register sub-register

3 pass alternately to generator

4 characters.

From the outputs of block 5 of the permanent memory, codes corresponding to the raster lines of the television decomposition of characters enter the raster line generator 6 and through it into the third group of 12 elements and, register 3 (the third sub-register), the first group of prohibition elements 15 and into the second block 2 memories. At this moment, registers 98 and 102 are communicated at input 112, And 99, And 103 elements are closed for passing signals from an output of an And 83 element, elements 100 and 104 of the zero barring their forbidding first inputs are open for passing control signals from the outputs of the register 17 to the second prohibiting inputs of the first 15 and second 16 groups of prohibition elements, register 17 is cleared and the information through groups 15 and 16 prohibition elements in memory blocks 1 and 2 passes unchanged, as well as on their second prohibiting inputs from the outputs of register 17 are zero.

one

In the mode of regeneration of the raster information from their outputs, the passage of codes

The processing words of length k m are bits through register 3 (fourth sub-register), the first group of 10 elements AND and a group of 13 elements OR arrive at block 7 (k; is the number of characters per line, m is the length of the line video code of one character). At this time, the second group of 11 elements is closed with the signal from the output of block 9, and the image is being reproduced on the screen of the CRT 8. With the help of groups 11 and 12 elements AND and group 13 elements OR of the device, the fourth mode of operation is realized.

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ten

15

6

In this mode, the third group of 12 elements And breaks the connection of the output of the generator of 4 symbols with register 3 and further with block 2 of memory.

Through the second group 11 of elements AND and the group 13 of elements OR, a direct connection of the 4-symbol generator with the modulation unit 7 is established to display the variable component of the images. Due to this (with the simultaneous implementation of the third and fourth modes) it is possible to combine the constant and variable components of the image,

In memory block 1, information may change many times with the same contents of memory block 2.

0

If it is necessary to erase the image on the screen of the CRT 8 completely or separately (variable or constant components), the device is transferred to the first additional erase mode, J, which is realized by commands from the information input 113 of the device, which enters the input of the register 14, previously cleared at the input 114, in the form of signs of modification of the numbers of the main modes (additional code bits).

The modified codes of the main mode numbers translate the addresses of the microinstructions memory unit 38 into the cell area, where microinstructions with units in the code bits are stored, which correspond to the outputs 38 connected via outputs 66 and 67 to the second input of the register 17.

The reset of register 17 is performed from the output of block 38 (output 65) connected to its first input through output 22 of block 9. This allows at the right moment to charge one or both of the trigger register 17 and prohibit sig0

five

0

five

through the first 15 or second 16 groups of prohibition elements or through both at once, depending on what is erased: the contents of the first memory block, the contents of the second memory block or both blocks simultaneously.

When erasing the entire image, the registers 98 and 102 are reset, the AND 99-103 elements are closed, and the prohibition elements 100 and 104 are opened for passing control signals.

Using blocks 79-105, the second additional mode of operation is realized: erasing the image in the window

(the window is part of a rectangular image).

It is possible to erase both a part of the image stored in the symbolic memory, giving the unit to the first input of the prohibition element 104, and a part of the image of the raster memory, giving the unit to the first input of the prohibition element 100, and both blocks of memory simultaneously.

Units are supplied from the outputs of the elements And 99 and 103 when the unit is at their first inputs and the units at the outputs coaxed to inputs 110 and 111 of registers 98 and 102. Elements 99 and 10 commute the signal from the output of element And 83 depending on the state of the registers. 98 and 102, which are cocked individually or together by signals from the information system after a reset. The signal at the output of the element 83 And is equal to one only within the window.

The size and position of the window is given with the coordinates of the upper left and lower right corners.

Coordinates of the window angles are entered into four receptions into registers 80, 85, 89 and 93 through groups 79.84.88 and 92 elements AND at input 106 from the information system after applying 109 pulses to the input General reset from the information system.

The first is the code for the X coordinate, the upper left corner of the window. In this case, the coordinate code is fed to the input 106, and the register number to which the coordinate will be written is fed to the input 107. The register number goes to the first input of register 101 and through it to the input of the decoder 97. The signal from the first output of the decoder 97 goes to the second input of the fourth group 79 of the And elements and opens it to pass the coordinate code to the register 80.

After recording the information in the register 80, the codes at the inputs 106 and 107 are removed, the register 101 by the pulse from the information system on the input 10-8 through the OR element 105 is reset and the new information is set at the inputs 106 and 107.

The second is the coordinate code Xc of the lower right corner of the window.

The signal from the second output of the decoder 97 through the fifth group

0

five

0

five

84 elements And it is written in Fifth register 85.

The third is the code for the coordinate U1 of the upper left corner of the window. The signal from the third output of the decoder 97 through the input 106 and the sixth group of 88 elements And it is recorded in the sixth register 89.

The fourth is the code for the y coordinate of the lower left corner of the window. The signal from the fourth output of the decoder 97 through the input 106 and the seventh group of 92 elements And it is recorded in the seventh register 93. After each entry, the register 101 is reset by a pulse from the output of the information system, coming through the first input of the register 101. The codes from the outputs of the registers 80, 85, 89 and 93, respectively, are fed to the inputs of the comparison units 81, 86, 90 and 94.

During operation of the device, the signals from the outputs of the counters of block 9 are fed to the inputs of the blocks 81, 86, 90 and 94 of the comparison. At the output of the comparator unit 81, a logical 1 signal appears when the X coordinate coincides with the current contents of counter 33 and 34, and at the output of the comparative block 86 when the X coordinate coincides with the current contents of these same counters,

At the output of comparator block 90, a signal appears when the Coordinate V1 coincides with the current contents of the counters 35 and 36, and at the output of Comparator 94, the signal appears when the Coordinate Vg coincides with the contents of the same counters.

The signal from the output of the comparator block 81 each time sets the tenth register 82 at its first input, the signal from the output of the comparator block 86 through the first element OR 87 resets the register 82 at its second input.

The active state of register 82 corresponds to the left and right edges of the window and its contents in the image decomposition rows.

The signal from the output of the comparison block 90 cocks the eleventh register 91 at its first input, and the signal from the output of the comparison block 94 resets the register 91 at its second input through the second element 95 and the second element OR 96.

The signal from the output of the compare block 90 corresponds to the upper edge of the window, the signal from the output of the compare block 94

corresponds to the lower edge of the window, the signal from the output of the element And 95 corresponds to the lower right corner of the window. The signals from the outputs of the registers 82 and 91 are fed to the inputs of the element L 83.

Upon completion of the cycle of operation of the device in the second additional mode, registers 80, 85.8-9.93,101. 82, 91,98,102 and 14 are dumped all together or in groups, depending on the task to be solved at the next stage of the device operation. The signal at the output of the element And 83 is equal to

unit within a window.

Claims (1)

The invention The device for displaying information on the screen of a cathode ray tube by the author. St. No. 12191956, characterized in that, in order to increase the speed of the device, it contains the fourth to seventh groups of elements AND, the fourth to twelfth registers, the first to fourth comparison blocks, the first to fourth elements of AND, the first, second and third elements of OR, the first and . the second elements of the prohibition, the second decoder, the first - the fourth outputs of which are connected to the first inputs of the elements K, respectively, of the first to fourth groups, the outputs of which are connected to the information inputs of the fourth and seventh registers, respectively; The first inputs are connected to the first inputs of the first to fourth comparison blocks, the second inputs of which are connected to the tenth output of the control unit, the output of the first comparison block is connected to the information input of the tenth register, the output of which is connected to the first input of the first And element, the output of which is connected to the first the inputs of the third and fourth elements And, the outputs of which are connected to the first inputs of the first and second elements of the prohibition, respectively, the outputs of which are connected to the second 0 five 0 five 0 five 0 five 0 the inputs of the prohibition elements of the first and second groups, respectively; the recording control inputs of the fourth to the seventh registers and the first inputs of the first to the third elements OR are the control input of the device, the input of the coordinates X, whose point is the second inputs of the elements AND of the fourth to the seventh groups The first input of the tenth register is connected to the output of the first element OR, the second input of which and the first input of the second element AND are connected to the output of the second comparison unit, the second input of the first element AND is connected to the output one The nineteenth register, the control input of which is connected to the output of the second OR element, the second input of which is connected to the output of the second element AND, the second input of which is connected to the output of the fourth comparison unit, the output of the third comparison unit is connected to the information input of the eleventh register, the second decoder input is connected to the output of the twelfth register, the control input of which is connected to the output of the third OR element, the second input of which was the first device reset input, the information input of the number The pinpoint of which is the information input of the twelfth register, the second input of the third element And is connected to the output of the eighth register, the second input of the fourth element I is connected to the output of the ninth register, the control inputs of which and the eighth register are the second input of the device reset, the first input is the setting of 1 which is the information input of the eighth register, the information input of the ninth register is the second input of the setting of 1 device, the second input of the first prohibition element is connected to the first one the course of the third register, the second output of which is connected to the second input of the second element of the prohibition. Fiz.Z