SU1525728A1 - Device for display of information on cthoe-ray tube screen - Google Patents

Abstract

The invention relates to automation and computing and can be used in devices for outputting alphanumeric and graphic information on a screen of a cathode ray tube (CRT). The purpose of the invention is to increase the speed of the device by the introduction of the fourth and fifth registers 79, 80, the first and second decoders 81, 82, the first and second groups 78, 89 of the AND elements, the second element OR 90, and the corresponding functional connections. The invention allows the accumulation in the second block of a fixed memory of several constant components of images with their subsequent use individually or in combination in the formation of complex images on a CRT screen. It also allows you to memorize the image of the same constant component several times (to reproduce images) or to combine several images on the screen of a CRT at the same time, which creates certain usability of the device and increases its speed. The operation of the device does not require repeated access to the information system, since once recorded, the set of constant components can be used in various combinations with variable components for a long time without renewal. 3 il.

Description

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: The invention relates to computerized automation and can be used in devices for outputting alphanumeric and graphic information on a screen of a cathode ray tube.

 The purpose of the invention is to increase the speed of the device by reducing the volume of information exchange with the external system due to the possibility of accumulating the constant components of the images and their further use in the formation of complex images.

FIG. 1 and 2 shows a block diagram of the proposed device; in fig. 3 is a block diagram of the control unit.

The device contains the first and second 2 memory blocks, the first register 3., a 4-character generator consisting of sequentially connected memory block 5, a raster line imager 6, a video signal imager 7, a CRT 8, a control block 9, first, second , the third elements AND 10-12, the first element OR 13, the second register 14, the first block 15 of the prohibition elements, the second block 16 of the elements of the ban, the third register .17, Positions 18-31 in the drawing indicate the second information input and the first output of the device, respectively , control unit outputs, input control unit. The device also contains a generator of 32 synchronization pulses, a counter 33 of the number of decomposition elements of characters on the X coordinate, a counter 34 of the number of characters in the display information line, a counter 35 of the number of decomposition elements of characters along the Y coordinate, a counter 36 of the number of rows of displayed information, a decoder 37, block 38 constant nodny memory of microinstructions. At positions 39-67 in the drawing, designate the outputs of the block 38 of the constant memory sync. rokoma1, position 68 — generator output 32, positions 69-74 — meter outputs 33–36, position 75 — fourth input of the first register 3, position 76 — output of the first group of prohibition elements, position 77 — first input of the second memory block 2 .

The device also contains the first group of 78 And elements, the fourth register 79, the fifth VO register, the first and second decoders 81, 82. Positions 0

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MIs 83-88 denote elements AND of the first and second groups 78, 89 of elements I. The device also contains a second element OR 90. The positions 91-95 in the drawing denote, respectively, the first information, control, second, third and fourth information inputs of the device.

In operation of the control unit 9, the generator of the synchronization pulse 32 produces pulses that synchronize the operation of the entire device. From its output, the pulses arrive at the inputs of the imaging unit 7 of the video signal (output 68) and the counter 33. The transfer pulses from the second output of the counter 33 arrive at the first input of the counter 34. The transfer pulses from the second output of the counter 35 arrive at the first input of the counter 36. Device status codes From the first outputs of the counters 33 and 35 (outputs 69 and 72), the second outputs of the counters 34 and 36 (outputs 71 and 74) and the output of the register 14 (input 31) are fed to the inputs of the decoder 37 connected to the microcommand memory block.

Using the block 38, in which the codes of micro-commands are recorded, the signals are read Block 1 (exit 39), Block 1 write (output .40), Block 2 read (output 41), Block 2 write (exit 42), Record the fourth sub-register ( not shown) register 3 (output 43), Reset the fourth sub-register of register 3 (output 44), signal Record the third sub-register (not shown) of register 3 (exit 45), signal Reset the third sub-register of register 3 (exit 46), Record the second sub-register of the register 3 (exit 48), Record of the first sub-register (not shown) of register 3 (exit 49), Reset of the first sub-register Level 3 (output 50) 9 General reset of register 3 (output 51), Reading block 5 (output 52), Record forcing 6 (output 53), Beginning of the frame (exit 54) j Beginning of the line (exit 55), Reverse 50 lines (output 56), Frame retraction (output 57), Shaper record 7 (output 58), Ready to receive a code (output 59), transfer signal for counter 35 (you- 5 turn 60), reset signal counters (output 61), the control signal of the first element And 10 (output 62), the control signal of the second element And 11 (you

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stroke 63), the control signal of the third element And 12 (output 64), the signal Reset register 17, the control signal of the second block 16 of the prohibition elements (output 66), the control signal of the first block 15 (output 67).

Counters 34 and 36 form the addresses of the first memory block 1 (outputs 70 and 73), counters 35 and 36 form the addresses of the second block. 2 memories (outputs 72 and 73). Additionally, the addresses generated by the counters 34 and 35 are used to control blocks 5 and 6 of the 4-character generator (outputs 70 and 72).

The control unit 9 implements four. The main modes of the device operation and the additional mode - erase images.

The mode number that is currently being implemented is recorded from the output of the information system to register 14 (input 102) at its first input. The reset of register 14 is effected by a signal from the information system at its second input 103 every time when switching to a new mode of operation.

Blocks 79-82 form an additional control block. This block implements control of memory block 2. In this case, it becomes possible to record information in block 2 and read information from it.

Before using the device

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They pass without change, since the signals at their prohibiting inputs from the outputs of register 17 are zero.

In the regeneration mode of the raster informational words with a length of kxm bit through the register 3, the first element AND 10, the first element OR 13 enter the shaper 7 of the video signal. Here k is the number of characters in a string, m is the length of the inline video code of one character.

At this time, the second element And 11 signal from the output of block 9 is closed.

Using the elements AND 11, 12 and OR 13, the device implements the fourth mode of operation.

In this mode, with the help of the third element And 12, the connection of the output of the 4-character generator with register 3 and further with the memory block 2 is broken.

Using the second element AND II and the first element OR 13, a direct connection of the generator of 4 symbols with block 7 is established to display the variable component of the images. Due to this, when simultaneously implementing the third and fourth modes, it is possible to combine the constant and variable components of the image. In block 1, information may change many times with the same content of block 2.

If necessary, erase the image on the screen of a CRT device re30

all registers are automatically reset to optional erase mode 1525728

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They pass without change, since the signals at their prohibiting inputs from the outputs of register 17 are zero.

In the regeneration mode of the raster informational words with a length of kxm bit through the register 3, the first element AND 10, the first element OR 13 enter the shaper 7 of the video signal. Here k is the number of characters in a string, m is the length of the inline video code of one character.

At this time, the second element And 11 signal from the output of block 9 is closed.

Using the elements AND 11, 12 and OR 13, the device implements the fourth mode of operation.

In this mode, using the third element And 12, the connection of the output of the 4-character generator with register 3 and further with memory block 2 is broken.

Using the second element AND II and the first element OR 13, a direct connection of the generator of 4 symbols with block 7 is established to display the variable component of the images. Due to this, when simultaneously implementing the third and fourth modes, it is possible to combine the constant and variable components of the image. In block 1, information may change many times with the same content of block 2.

If necessary, erase the image on the screen of a CRT device re0

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Through register 3 and the second block of 16 barring elements, character codes in the exchange mode with the information system (input-18) are fed to the input of the first memory block 1. Here they are recorded in successive cells in the order of arrival at its input. According to the signals from the outputs of the control block 9 in the raster generation mode, they are selected from block 1 and pass alternately through register 3 into the 4-character generator.

From the code of block 5 of the permanent memory, the codes corresponding to the raster lines of the television decomposition of characters go to the raster line shaper 6, and through it the third element I 12 to the register 3, through the first block 15 prohibition elements to the second block 2 of memory . At this moment, the register 17 is cleared and the information through the blocks of prohibition elements in memory blocks 0

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nor the image, which is implemented by commands from the output of the information system T, received at the input of the register 14 through the input 102 in the form of signs of modification of the main modes (additional code bits).

The modified codes of the main mode numbers transfer the addresses of block 38 to the cell area where microcommands with units in the code bits are stored, which correspond to the outputs 66 and 67 of the block 38 connected to the second input of the register 17. Reset, register 17 is emitted by a signal from the output 65 unit 38 connected to its first input.

When erasing, automatic recording of zeros is made from the outputs of the first or second block of prohibition elements into memory cells without the fate of the information system.

If the next constant component of image 5 is to be recorded into the device, the zone number of memory block 2, to which information should be recorded, is simultaneously supplied to the inputs of the decoder P | 81 and 82.

In this case, only descrammer 81 will work, since its Edge code differs from the input code of the decoder 82 by a special sign. If 1: the sign is equal to one, the decoder 81 is triggered; if zero, the decoder is 82.

From the output of the decoder 81, the unitary code is written into register 79, after which in one of the first elements: Fuppa 78, whose number corresponds to:) the unit bit number of the unitary code, conditions are created; 1 passing information from the output of 16 V block 2.

After the recording of the current 10-POST component is completed, the procedure is repeated on the inputs of the decoders 81 and 82.

I The new unitary code, from the output of the decoder 81, configures the device to record information in the new zone of block 2. The process of accumulation of permanent deliveries stops after the last constant component is written | In the same way. You can organize the accumulation of any images.

Information is recorded in zones at addresses from block 9.

If from block 2 it is necessary to read the information and display it on the screen of a CRT 8, the code of the number of the corresponding zone with a modified access code is supplied to the inputs of the decoders 81 and 82; familiar

In this case, the unitary code from the output: yes, the decoder 82 will go to register 80. Conditions will be created for the passage of information from the output of the selected zone through the open elements AND of the second group to one of the inputs of the second element OR 90 in the direction of the register 3 and CRT eight.

After each write or read operation is completed, pulses from the information system at input 95 realize a reset of registers 79 and VO simultaneously or separately, depending on the problem being solved.

It is easy to implement the accumulation of several unitary codes in registers 79 and 80. To do this, it is enough to submit zone codes to the inputs of the decoders.

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take turns several times. This makes it possible to memorize the image of the same constant component several times in different zones (to multiply images) or to combine several images on the screen of a CRT simultaneously, which creates certain usability of the device and saves time. system operation.

Thus, the proposed device in comparison with the prototype has a higher speed. Its operation does not require repeated treatment of the information system, since once a set of constant components is stored, it can be used in various combinations with variable components for a long time without renewal. The process of managing information exchange is fully automated.

Here, the information exchange time when using several constant components of the image is reduced by K times, where K is the number of accumulated constant components.

Claims (1)

Invention Formula A device for displaying information on the screen of a cathode-ray tube (CRT), containing the first and second memory blocks, the first register, a symbol generator, consisting of a block of permanent memory and a raster line driver, a video signal generator, the output of which is connected to a modulator CRT, the first, second, third elements AND, the first element OR, the second register, the first and second block. Inhibit elements, the third register, the first information input of the second register is the first information input of the device, the control input of the second register is the control input of the device, and the output of the second register is connected to the input of the control unit whose first output is connected to the control input of the first a memory unit whose output is connected to the first information input of the first register, the second information input of which is the second information input of the device, the second output of the control unit with one with the control input of the second memory block, the first output of the first-of-register is connected to the information input of the fixed memory block, the control input of which is connected to the third output of the control block, the output of the fixed memory block is connected to the information input of the raster line former whose control input is connected to the fourth upstream control unit, and the output is with the first inputs of the second and third elements AND, the output of the second element AND is connected to the first input of the first element OR whose output is connected to the video input of the video signal conditioner, the output of the third element AND is connected to the third information input of the first register, the second input of the third element I is connected to the fifth output of the control unit, the sixth output of which is connected to the second input of the second element I, the seventh output to the first input of the first element I, the second input of which is connected to the second output n the primary register, the output of the first element I is connected to the second input of the first element OR, the control input of the video signal generator is connected to the eighth output of the control unit, the ninth output of the control unit is connected to the control input of the first register, the tenth output of the control unit is output devices, information inputs of the third register are connected to the eleventh and twelfth outputs of the control unit, the first output of the third register is connected to the first input of the second block of prohibition elements, the second input of which union of a third output first register, output 0 0 . 5 n 0 The block of blocking elements is connected to the information input of the first memory block, the fourth output of the first register is connected to the first input of the first block of bans, the second input of which is connected to the second output of the third register, characterized in that, in order to increase the speed of the device, contains the fourth and fifth registers, the first and second decoders, the first and second groups of AND elements, the second OR element, the output of which is connected to the fourth information input of the first register, the input of the first decoder in The third information input of the device is connected to the input of the second decoder, the output of the first decoder is connected to the control input of the fourth register, the information input of which is the fourth information input of the device and connected to the information input of the fifth register, the control input of which is connected the output of the second decoder, the outputs of the fourth register connected to the first inputs of the corresponding elements And the first group, the second inputs of which are connected to the output of the first block of elements apreta, outputs of elements AND of the first group are connected respectively to the information inputs of the second memory block, the outputs of which are connected to the first inputs of elements AND of the second group, the second inputs of which are connected to the corresponding outputs of the fifth register, and outputs of the elements AND of the second group are connected to the corresponding inputs of the second element OR. ft LiM Phi.1