SU1401514A1 - Indicator - Google Patents

Abstract

The invention relates to automation and computing and can be used in automated control systems for displaying information on a matrix display panel screen. The purpose of the invention is to increase the information capacity of the device. The goal is achieved by introducing a code converter, frequency divider into a device containing an input unit, a memory unit, keys of the first and second groups, a decoder, a first indicator, a counter, two character generators, a counter, a trigger, a second indicator and loops. master-code, counters, differentiating elements, two adders and logic elements, which ensures by displaying the read address and the write address in accordance with the selected mode specified from the input unit, the display on the first indicator the torus of one line selected in the memory block and its number on the second indicator. or sequential display of Rceii information by shifting it on the first indicator. 1 il. (ABOUT

Description

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The invention relates to automation and computing, in particular to indicator devices, and is intended to display information in automated control systems for various purposes, in reference information systems and automatic control systems.

The purpose of the invention is to increase the information capacity of the device.

Combus OR is supplied to memory block 9 and the character code from input block 1 is recorded at the address of the first familiarity of the first line. With the falling edge of the "Record arriving through the third element OR 32, counter 14 of the record address, the familiarity character is transferred to the next state and the code at its output 00 ... 01 corresponds to the second familiarity. When the next signal is sent, the Record is recorded, the drawing is shown in the drawing, 10 at the address of the second familiarity

on the device diagram.

The device contains an input unit 1, a clock pulse generator 2, a read address address counter 3, a decoder 4 familiarity keys of the first group 5, first indicator 6, keys of the second group 7, first character generator 8, memory block 9, code converter 10, second character generator 1U the second indicator 12, the trigger 13, the counter 14 addresses the address familiarity, counter

lines. With the falling edge of the signal, the Record counter 14 of the address of the familiarity record is transferred to the next state and the code at its output 00 ... 10 corresponds to the third familiarity, etc.

The address code of the line entry from the outputs of the second block of 21 OR elements is fed to a 10 code converter that converts the binary code of the line number to the binary-decimal code.

15 lines, setpoint 16 code, first 17 and 20 character generator 11 performs

second 18 accumulators, frequency divider 19, first 20 and second 21 blocks of elements OR, first 22, second 23, third 24, fourth 25, fifth 26 and sixth 27 blocks of elements AND, first 28, second 29, fifth 30, fourth 31 and third 32 elements OR, third 33, fifth 34, fourth 35, first 36 and second 37 elements AND, second 38, third 39 and first 40 elements NOT, first 41 and second 42 differentiating elements, block 43 elements OR NOT .

The device works as follows.

In the initial state, in memory block 9, the information capacity of which is greater than the number of familiarity N on the first indicator 6, the information is not entered. By the signal “At installation O, coming from block 1 of input through the fourth Element OR 31, trigger 13 is set to one, the counter of 15 lines and counter 14 of the address of the record of familiarity are reset.

In the device, the recording of the information on the conversion of the binary-decimal code into the drawing code arriving at the second indicator 12. The indicator's width is determined by the maximum number of lines. When the code at the output of the counter 15 lines 00 ... 00

25 0 ... 0 is displayed on the indicator.

In the absence of a "Write" signal, information is read from memory block 9, the character code is converted into an outline code ("graphic code) and the information is displayed on the first indicator 6. If the number of characters written in memory block 9 is less than the information capacity of the first indicator 6, the code at the output of the counter 15 lines 00 ... 00. At the outputs of the block 43 elements OR NOT level logical "1, the third element NOT 39 - logical" O, p that element AND 34 - logical "O. To the transfer input of the first adder 17, the second input of the third block 24 of the elements AND, and the first input of the fourth block 25 of the elements of AND are fed through the first 35

exists in the sequential mode 40

or page by page.

Sequential write mode.

In the sequential recording mode, the output signal “Afterbirth. block 1 input has a logical value of "1, and at the outputs of" Post. and “Subsequent. - logical "O. To the input of the second block 23 elements I, the code of the address of the familiarity record from the output of the counter 14 of the address of the record of the familiarity is given, and through the fifth block 26 elements And the second block of 21 elements OR the code of the address of the record line from the output of the counter 1-5 lines. When a signal is fed from the input block 1 "Recording from the output of the second element I 37, an enabling signal is supplied to the second block 23 of the elements And, and through the second

45

50

"ABOUT. Therefore, at the outputs of blocks 24 and 25 elements, AND is a logical level “O, at the outputs of the first adder 17, the code corresponds to the code at the output of the counter 3 read address familiarity, and at the outputs of the second adder 18 - the code at the outputs of the counter 15 lines, i.e. 00 ... 00.

Let counter 3 of the address of familiarity reading be in the zero state, i.e. the code on its exits is 00 ... 00. Regarding this

a signal is present at the first output of the digester 4 and a signal is fed through the keys of group 5 to the control electrode of the first familiarity of the first indicator 6. Address familiarity code of the familiarity 00 ... 00

the element NOT 38 to the first block 22 of the elements 55 of the address of reading of the line 00 ... 00 is AND AND is fed a logical zero level. Code cut first block 22 elements And and first

an OR block 20 is supplied to a memory block 9. From the outputs of block 9 of the memory of the write address from the output of the second block of 23 elements I, through the first block of 20 elements OR is fed to block 9 of the memory and the sign code from the input block 1 is recorded at the address of the first familiarity of the first line. With the falling edge of the "Record arriving through the third element OR 32, counter 14 of the record address, the familiarity character is transferred to the next state and the code at its output 00 ... 01 corresponds to the second familiarity. When the next signal is sent, “Write is written to write the code at the address of the second familiarity first

lines. With the falling edge of the signal, the Record counter 14 of the address of the familiarity record is transferred to the next state and the code at its output 00 ... 10 corresponds to the third familiarity, etc.

The address code of the line entry from the outputs of the second block of 21 OR elements is fed to a 10 code converter that converts the binary code of the line number to the binary-decimal code.

20 character generator 11 performs

the conversion of the binary-decimal code into the tracing code, arriving at the second indicator 12. The indicator width is determined by the maximum number of lines. When the code at the output of the counter 15 lines 00 ... 00

25 0 ... 0 is displayed on the indicator.

In the absence of a "Write" signal, information is read from memory block 9, the character code is converted into an outline code ("graphic code) and the information is displayed on the first indicator 6. If the number of characters written in memory block 9 is less than the information capacity of the first indicator 6, the code at the output of the counter 15 lines 00 ... 00. At the outputs of the block 43 elements OR NOT level logical "1, the third element NOT 39 - logical" O, p that element AND 34 - logical "O. To the transfer input of the first adder 17, the second input of the third block 24 of the elements AND, and the first input of the fourth block 25 of the elements of AND are fed through the first 35

 40 left element OR 28 logical level

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50

"ABOUT. Therefore, at the outputs of blocks 24 and 25 elements, AND is a logical level “O, at the outputs of the first adder 17, the code corresponds to the code at the output of the counter 3 read address familiarity, and at the outputs of the second adder 18 - the code at the outputs of the counter 15 lines, i.e. 00 ... 00.

Let counter 3 of the address of familiarity reading be in the zero state, i.e. the code on its exits is 00 ... 00. Regarding this

a signal is present at the first output of the digester 4 and a signal is fed through the keys of group 5 to the control electrode of the first familiarity of the first indicator 6. Address familiarity code of the familiarity 00 ... 00

The character code recorded at the first familiarity address of the first line and fed to the inputs of the first character generator 8. At the outputs of the first character generator 8, an outline code is formed, which through the keys of group 7 is fed to the information inputs of the first indicator 6 and a sign is displayed at the first familiarity panel.

When entering from the oscillator. 2 clock pulses of the next pulse counter 3

The first inputs of the second adder 18 are supplied from the outputs of the master 16 codes through the third block of 24 elements AND an additional code 1, i.e. if the address of the write address is two-digit, then 11, three-digit 111, four-digit 1111, etc. At the output of the second adder 18, the code is equal to the sum of the code value of the current address of the row entry and the code from the output of the master of the 16 code, taking into account the value of the transfer signal from the reading address, the familiarity goes to Yu of the first adder 17. With the code value at the output of the counter 3, the address of familiarity 00. ..00 the code at the output of the first adder 17 is 00 ... 00- | -00 ... 004-1 (transfer) 00 ... 01, and at the output of the second, the alternate state, the code at its output corresponds to 00 .. .01. A signal appears at the second output of the decoder 4 and through the keys of the first group 5 a signal is sent to the second

Yes, at the output of the counter 3 of the address of familiarity reading 00 ... 00, the code at the output of the first adder 17 is 00 ... 00- | -00 ... 004-1 (transfer) 00 ... 01, and at the output of the second sum-control electrode of the first indicator 6 from the mater 18 00 ...... (transfer)

and reading out from the memory block 9 a character code written at the address of the second familiarity of the first line, converting it in the first character generator 8 to the markup code and feeding through the keys of the second group 00 ... 00. In the absence of a signal "Write to the inputs of the memory block 9, the read address code of the second familiarity of the first line is supplied. Accordingly, the code of the sign 7 is read from the output of the memory block 9 to the information inputs of the indicator. 20 ka recorded at the address of the second sign A sign is displayed on the second familiarity sign, etc. Since the frequency of the signals at the output of the generator 2 clock pulses is chosen from the condition of connecting familiarity with a frequency exceeding the critical frequency of regeneration, the image on the indicator is perceived as non-fading.

After writing the character code to the last familiarity of the first line on the leading front of the first line, which is converted to the mark code and displayed on the first familiarity of the first indicator 6, since the code at the output of the counter 3 of the familiarity address is 00 ... 00. Upon receipt of the next clock pulse from the generator 2 pulses, the code at the output of the counter 3 of the read address of the familiarity 00 ... 01 and the second sign displays the sign recorded at the address of the third sign of the signal Record counter 14 of the first row and so on . If

on

writing the familiarity goes to the zero state when the code at its output is 00 ... 00, and the transfer signal from its output switches the counter of 15 lines to the next state, the code at its output 00 ... 01 corresponds to the second

the output of the counter 3 code 11 ... 11 at the output of the first adder 17 code 00 ...... 11 + 1 (transfer) 00 ... 00 and the signal at the output of the transfer, and the output of the second adder 18 code 00 ... 01 So at the last

line. A sign is displayed on the second indicator 12 on the 5th position of the panel, the line number 0 ... 1 is clamped.

When filing a signal from the input block "Recording through the second block 23 elements AND and the first block 20 elements OR, the memory address 9 is supplied with the address code of the familiarity place 00 ... 00 from the outputs of the counter 14 and the line code 00 ... 01 from the outputs of the counter 15 and recording the character code coming from the input unit 1. In this case, the number of recorded characters in memory block 9 is greater than the information capacity of the indicator. At the output of block 43 of the element OR NOT the level of logical “O, the third element of NOT 39 is logical“ 1, of that element AND 34 is logical “1. At the input of the transfer of the first sum of ator 17, the first input is the third 40

45

written to the address of the first familiarity of the second line, i.e. last recorded mark. The process of recording and displaying subsequent characters is similar, with the indicator displaying the last N characters recorded last, with the last character recorded displayed on the last, N-M, place of the first indicator 6.

After the last character is written, the counter 14 of the address of the familiarity record is set to the state when the code at its output is 00 ... 00, the counter 15 of the address for writing lines to the state when the code is at its output 00 ... 00, and from its output the transfer signal is fed to the first differentiating element of the block 24 elements And and the first input of CQ ment 41. The front of the signal of transfer, selection - the fourth block of 25 elements And through the first differentiating element, through

the third element AND 33 and the fifth element OR 30 are applied to the R input of the trigger 13, converting it to the zero state. The logical level of "O supplied to one input

The new element, OR 28, is supplied with a logic level of "1. At the output of the first adder 17, the code is equal to the sum of the codes at the output of the counter 14 of the write address of the familiarity and the output of the counter 3 of the read address of the 55-sign of the second element I 37, prohibits the passages, which are increased by one, the signals from the Record from the input block 1.

bit (the logical level "1 at the input, this eliminates the repeated recording of the information transfer of the first adder 17) of the mapping to the previously recorded one.

The first inputs of the second adder 18 are supplied from the outputs of the master 16 codes through the third block of 24 elements AND an additional code 1, i.e. if the address of the write address is two-digit, then 11, three-digit 111, four-digit 1111, etc. At the output of the second adder 18, the code is equal to the sum of the code value of the current address of the row entry and the code from the output of the master 16 of the code, taking into account the value of the transfer signal from the output of the first adder 17. When the value of the pass of the first adder 17. When the code value at the output of the counter 3 is the familiarity address reading 00 ... 00 code at the output of the first adder 17 is 00 ... 00- | -00 ... 004-1 (transfer) 00 ... 01, and at the output of the second adder 18 00 ... (transfer )

Mater 18:00 ...... (transfer)

00 ... 00. In the absence of a signal "Write to the inputs of the memory block 9, the read address code of the second familiarity of the first line is supplied. Accordingly, the memory code of the first row is read from the output of the memory block 9, which is converted to the markup code and displayed on the first familiarity of the first indicator 6, since the code at the output of the counter 3 of the familiarity address is 00 ... 00. When the next clock pulse arrives from the pulse generator 2, the code at the output of the counter 3 of the read address of the familiarity 00 ... 01 and a sign written at the third familiarity of the first line, etc., is displayed on the second decimal place. If

on

that first line, etc. If

the output of the counter 3 code 11 ... 11 at the output of the first adder 17 code 00 ...... 11 + 1 (transfer) 00 ... 00 and the signal at the output of the transfer, and the output of the second adder 18 code 00 ... 01 So at the last

the familiarity of the panel displays a sign for 0

five

written to the address of the first familiarity of the second line, i.e. last recorded mark. The process of recording and displaying subsequent characters is similar, with the indicator displaying the last N characters recorded last, with the last character recorded displayed on the last, N-M, place of the first indicator 6.

After the last character is written, the counter 14 of the address of the familiarity record is set to the state when the code at its output is 00 ... 00, the counter 15 of the address for writing lines to the state when the code is at its output 00 ... 00, and from its output The transfer signal is fed to the first differentiating element.

In the page-by-page recording mode, the signal at the output of “Post line block 1 input has a logical value of "1, and the outputs of" Sequential. and "Last, selected. - logical "O. The address of the entry that arrives at the second inputs of the second block 23 of the AND elements is determined by the code at the output of the counter 14 of the address of the familiarity entry and the line code supplied from the input block 1 through the sixth

the element OR 28 is fed to the transfer input of the first adder 17 and permits the passage through the fourth block 25 elements AND to the first inputs of the first adder 17 of the code from the output of the counter 14 of the address of the familiarity record and through the third block 24 elements AND to the first inputs of the second adder 18 of the code from the setpoint 16 code. On the signal "Post, a show. Coming through the second element OR 29 from the output

block 27 elements AND and the second block of ele unit 1 input to the second inputs of the adder of the OR 21 pulses. The number of the line to which 18 is through the sixth block 27 elements AND and the second

block 21 of the elements OR, the code is output from the counter of 15 lines. Change of code at the output of the counter 14 address recording familiarity

the characters are recorded, displayed on the second indicator 12. After the information of the entire line is recorded, the counter 14 of the record address goes to the status 00 ... 00 f. carried out with a frequency of following them - and at its second output a pulse signal arises at the input of counter 14

through the first element AND 36 and the third element OR 32 from the output of the divisor 19 of the mass transfer. The front of the renor signal, separated by the second differentiating element 42, through the fourth element And 35 and fifth. the element OR 30 is applied to the R input of the trigger 13, bringing it to the zero state. 20 yes, the frequency divider 19 is selected from us- the signal from the output of the flip-flop 13 prohibits reliable perception of the driving pulse following from the output of the signal "Recording through the second element 37" and thus eliminating the repeated recording of information within the selected line. The trigger 13 enters a single state with the signal “Line feed when selecting a new line or with the signal“ Setting O, I enter 25

from the information on the first indicator 6. The read address supplied through the first block 22 AND elements and the first block 20 OR elements to the memory block 9 is determined by the current code values at the output of the counter 8 of the familiarity address and counter 14 of the write address by the block sign 1 input through the fourth slot, taking into account the transfer signal from the first cop OR 31. summator 17 and lines -. code value with

At the output of the fifth element And 34 and the per-outputs of the setter 16 of the code and the current knowable element OR 28 is the logic level of the code at the output of the counter 15 lines

"O, which is fed to the input of the transfer signal taking into account the transfer signal from the second sum of the first adder 17, the first inputs of the third torus 18. This provides the display

its block of elements, And 24, and the first inputs to the last, N-M, familiarity of the first

the fourth block of elements is 25. As the indicator has 6 characters recorded at the address, the first inputs of the first adder 17 are with, the code of which is equal to the current code value at the output of the counter 14 of the address of the familiarity record and the counter of 15 lines. On the N-1st, familiarity displays the previous information. When the next pulse arrives from the output of the frequency divider 19, the 00 ... 00 code and the code for its new sign are also displayed on the last block of the third block 24 elements 40, N-M, the decimal place of the panel, and the previous information

shifts one familiarity to the left. Thus, in the sequential display mode, an operative viewing of the information recorded in the memory block 9 is performed, and the line number, the information of which is displayed on the first indicator, is reproduced on the second indicator 12.

.Technical and economic benefits

Neither the signal at the output "Postb. 0 The decomposable device is enclosed in the input unit 1, which has the meaning of the logical possibility of displaying information in the sequential recording mode, in which the last entered character and the previous entered characters are reproduced on the indicator, within its information capacitance. , in the page-by-page recording mode, when information on a separate line is reproduced on the non-40 element of the NOT 40, the projection indicator plays back, and the sequential display mode, in which

is given from the outputs of the quarter-block block of 25 elements AND the code is 00 ... 00, then the code at its outputs is equal to the code at the second inputs supplied from counter 3 of the address of familiarity. At the first inputs of the second adder

outputs equal to the code on its second inputs, i.e. address code line at the outputs of the second unit 2 elements OR. This ensures that the first entered character is displayed on the first decimal place of the indicator, the second entered sign is displayed on the second familiarity, etc.

Sequential display mode.

In the sequential display mode: 1, at the outputs “Last. and “Logical line“ On, at the output of the first element AND 34 - the level of the logic “On, and the first element OR 28 - the logic level“ 1.

signal “recording from input block 1”. The logical signal "1 from the output of the first

the element OR 28 is fed to the transfer input of the first adder 17 and permits the passage through the fourth block 25 elements AND to the first inputs of the first adder 17 of the code from the output of the counter 14 of the address of the familiarity record and through the third block 24 elements AND to the first inputs of the second adder 18 of the code from the setpoint 16 code. On the signal "Post, a show. Coming through the second element OR 29 from the output

block 1 input to the second inputs of the adder 18 through the sixth block 27 elements And the second

during the counter 14 addresses records familiarity

carried out with the frequency of the pulses following the input of the counter 14

. frequency divider 19 is selected from the us- and reliable perception of the "driving" pulse period from the output. 20 yes the frequency divider 19 is chosen from the condition of reliable perception of the “driving” 25

From the information on the first indicator 6. The read address supplied through the first block 22 elements AND and the first block 20 elements OR to the memory block 9 is determined by the current code values at the output of the counter 8 of the familiarity address and counter 14 of the write address, the information is reproduced lines, character by character, with the additional indicator displaying the number of the line, the information of which is reproduced on the gas discharge display panel.

Claims (1)

An invention of a display device comprising an input unit whose input is an input of a device, and an information output connected to an information input of a memory unit whose address input is connected to the output of the first block of OR elements, the first input of which is connected to the output of the first block of AND elements, and the second entrance - to the exit the input of which is connected to the control input of the memory unit whose output is connected to the information input of the first character generator, the keys of the first group whose outputs are connected to the control inputs of the first indicator, whose information inputs are connected to the outputs of the keys of the second group whose inputs are connected to the outputs of the descrambler familiarity, the inputs of which are connected to the information output of the address counter of the familiarity reading, pulse generator, line counter, second character generator, second indicator, trigger, differing Moreover, in order to increase the information capacity of the device, a divider is inserted into the second control output of the input unit, and the second input is connected to the output of the first element NOT, the output of the third element OR is connected to the counting input of the address of the familiarity entry, the setting input of which is connected with the third control output of the input unit, with the installation input of the row counter and with the first input of the fourth OR element, the second input of which is connected to the fourth control output of the input unit, and the output connected to Set 1 trigger, the output of which is connected to the third input of the second element AND, the overflow output of the write address counter is connected to the second block of AND elements, the first input of the row counter and to the input of the first differentiating element, the output of the overflow line counter is connected to the input of the second differentiating element the outputs of the differentiating elements are connected to the first inputs of the third and fourth elements, respectively, And, the second inputs of which are connected respectively to the fifth and the second control the outputs of the input block, and the outputs to the inputs of the fifth OR element, the output of which is connected to the input “Setup - About trigger,” the fifth control output of the input block is connected to the second input of the second OR element and to the first input of the fifth jd element, the second input of which is connected to the output of the third element NOT, the input of which is connected to the output25 you, the code converter, the third, the fourth, the unit block of the elements OR NOT, the inputs of which the fifth, fifth and sixth block of the AND elements, the first and second adders, the second block of OR elements, the three elements NOT, the five AND elements, the OR elements, the first and second differentiating elements, the address count of the familiarity record, the block of OR elements -NOT and code setter, the output of which is connected to the first input of the third block of elements AND, the second input of which is connected to the output of the first element OR, to the first input of the fourth block of the element is connected to the information outputs of the row counter And to the first inputs of the fifth block of elements And, the secondthe stroke of which is connected to the output of the second OR element, and the output is connected to the first input of the second block of OR elements, the second input of which is connected to the outputs of the sixth block of elements AND, the first input of which is connected to the address output of the input block and the second input to the control output of the input block, the output of the second block 45 The first information input is 40 elements OR is connected to the first information of the first adder, the second information input of which is connected to the output of the fourth block of I elements, the third information input of the first adder is connected to the information output of the read address counter familiarity, the counting input of which is connected to the output of the pulse generator, and the overflow output is connected to the input of a frequency divider, the output of which is connected to the first input of the first element I, the second input of which is connected to the first control the output of the input block, with the input of the first element NOT and with the first inputs of the first and second elements OR, the output of the first element AND is connected to the first input of the third element OR, the second input of which is connected to the input of the second element NOT and with the second input of the second block of elements AND the output of the second element And, the first input of which is connected to The second input of the second adder, to the second input of the second block of I elements and to the information input of the code converter, the output of which is connected to the information input of the second character generator, the output of which is connected to the second indicator input, overflow output of the first adder to the second information input of the second adder, third information whose input is connected to The CQ outputs of the third block of elements And, the outputs of the first and second adders are connected to the first input of the first block of elements And, the second input of which is connected to the output of the second element NOT, the information outputs of the record address counter of the 55 places are connected to the second inputs of the fourth and second blocks of And, respectively the outputs of the first character generator connected to the inputs of the keys of the first group. the second control output of the input unit, and the second input is connected to the output of the first element NOT, the output of the third element OR is connected to the counting input of the record address counter familiarity, the installation input of which is connected to the third control output of the input unit, the installation input of the row counter and the first the input of the fourth OR element, the second input of which is connected to the fourth control output of the input unit, and the output is connected to the input “Setting 1 trigger, the output of which is connected to the third input of the second element AND, output The address counter of the familiarity record is connected to the counting input of the row counter and to the input of the first differentiating element; the output of the row counter overflow is connected to the input of the second differentiating element; the outputs of the differentiating elements are connected to the first inputs of the third and fourth elements, respectively; the second inputs of which are connected respectively to n to the same control outputs of the input block, and the outputs to the inputs of the fifth OR element, the output of which is connected to the input “Installation - About a trigger, the fifth control yusch.y output of the input unit connected to the second input of the second OR gate and to the first input of the fifth element jd, the second input of which is connected to the output of the third NOT element, whose input is connected to vyho5 ,, do block of elements OR NOT, which inputs connected to the information outputs of the row counter and to the first inputs of the fifth AND block, the second input of which is connected to the output of the second OR element, and the output connected to the first input of the second block of OR elements, the second input of which is connected to the outputs of the sixth block of elements And, the first input of which is connected to the address output of the input block, and the second input to the other control output of the input block, the output of the second block 40 elements OR connected to the first 45 40 elements OR connected to the first The second input of the second adder, to the second input of the second block of I elements and to the information input of the code converter, the output of which is connected to the information input of the second character generator, the output of which is connected to the second indicator input, overflow output of the first adder to the second information input of the second adder, third information whose input is connected to The CQ outputs of the third block of elements And, the outputs of the first and second adders are connected to the first input of the first block of elements And, the second input of which is connected to the output of the second element NOT, the information outputs of the record address counter of the 55 places are connected to the second inputs of the fourth and second blocks of And, respectively the outputs of the first character generator connected to the inputs of the keys of the first group. / J