SU1354241A1 - Device for displaying information on television set screen - Google Patents

Abstract

The invention relates to the field of computer technology, in particular to image processing devices, and is intended for use in information display systems when outputting it to a television screen. The purpose of the invention is to increase the speed and simplify the device, which is achieved by introducing registries of the 8 and 2 registers to the start of scanning on the frame and on the line and counters 3 and 9. the current address on the line and on the frame, and the corresponding functional links. The invention allows simultaneously displaying arrays of data that are larger than the information capacity of the screen, and reducing the delay of the counter 3 current addresses on the line to the delay of one chip of the memory block 5 reduces the time required for the information on the screen of the television receiver 7. -2 Il. i (l oo ate

Description

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The invention relates to computing technology, in particular to image processing devices, and is intended for use in information display systems when outputting it on a television screen.

The purpose of the invention is to improve the speed and simplify the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 diagrams on the operation of the device.

The device contains a synchronization unit 1, a scan register 2 on a line, a counter 3 current addresses on a line, a switch 4 addresses on a line, a memory block 5, a video signal generator 6, a television receiver 7, a scan start register 8 frame, the counter 9 of the current address per frame, the switch 10 addresses per frame, the counter 11 of the address of the entry per line, the counter 12 of the address of the entry per frame, a block 13 of the interface with the computer.

The device works as follows.

When writing information to block 5, the memory and reading information from it, the recording mode takes precedence.

Let information be recorded in memory block 5. When this information is read, the frame damping pulses (Knj) from the output of synchronization unit 1 are input to the write control input of the counter 9 of the current address on the frame and the binary code is written to it at the beginning of scanning on the frame from the register 8 output.

Lower quenching pulses (SGI) from the output of block 1 are fed to the counting input of counter 9, and during the forward path of the EJ beam, a binary code is generated at the output of counter 9 that uniquely identifies the position of the vertical decomposition element.

The GIS also enters the control input of the record of the counter 3 of the current address per line and records the binary code of the start of scanning per line from the output of register 2.

The clock pulses from the output of the block .1 arrive at the counting input of counter 3, and during the forward path of the CRT beam, a binary code is formed at the output of counter 3 that uniquely identifies the position of the horizontal expansion element.

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From counter 3, the binary code goes through switch A to the lower bits of memory block 5, and from counter 9 via switch 10 to the high bits of block 5.

The data from the output of block 5, defined by the address coming from the switch 4 of the address and the switch 10 of the address, are transmitted to the shaper from the video signal, the sync input of which receives the sync pulses from the output of block 1, and the output produces a standard television signal that is supplied to the video input of the television receiver 7.

Suppose that memory block 5 has a capacity m x n, where m is the number of decomposition elements in a line, n is the number of memory lines, and the information capacity of the television screen is k x 1, where k is the number of decomposition elements in the line on the screen , 1 - the number of woodchuck on the screen. Moreover, k -; m, 1 n, i.e. screen information capacity is less than memory capacity.

Let us denote the binary code of the start of scanning on the line by a, and the binary code of the beginning of scanning on the frame by b. The memory area displayed on the television screen is expressed by the formula

(a + k) (b + l) -b k x 1.

The binary start and scan codes for the line and frame defining the image area displayed on the television receiver screen recorded in the memory block 5 can be changed programmatically or from the computer remote control via the interface block 13.

When writing information to block 5, the binary code defining the address of the element number per line from the output of counter 11 is fed to the input of switch 4, from the output of which goes to the lower address bits of block 5.

The binary code defining the address of the line number from the output of the counter 12 goes to the switch 10, from the output of which goes to the higher address bits of block 5,

The data to be recorded and the recording signal are received from the computer through block 13.

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The recording in block 5 is performed in two modes: recording data at an arbitrary address and recording a data array,

In the first mode, two cycles of accessing the computer to the device are required for recording data in block 5,

In the first cycle, counters 11 and 12, with a signal from the output of block 13, write the address code of the record coming from the computer through block 13 to the information inputs of these counters.

In the second cycle, the data code from the computer through block 13 is recorded in block 5 by a signal coming from the third output of block 13 at the address coming from counters 11 and 12 over switches 4 and 10 to the address inputs of block 5,

The address code of the entry generated by the counter is incremented by one after each computer access cycle to memory block 5.

Thus, to record a sequential array of data, there is no need to additionally refer to the counters 11 and 12 of the write addresses,

In the proposed device, counters with parallel writing of a binary code allow to realize a pipelined memory organization, which provides speed when reading data corresponding to the output speed, and when dynamically strobing an address, prepare the address in advance (Fig. 2, where 14 is the decomposition element number at a given moment of time on the television receiver screen, 15 is the time diagram of the signal strobe the leading edge of the data addresses in the memory block, 16 is the time diagram of the signal strobe declining high order bits in the memory block).

Thus, the delay of the counter 3 of the current address per line is reduced to the delay of one chip of the memory unit and, therefore, the time for displaying information on the television receiver is reduced.

Claims (1)

The device for displaying information on the screen of a television receiver, comprising a synchronization unit, the first output of which is connected to the sync input of the video signal generator, the output of which is connected to the video input of the television receiver, a memory block, a row address address counter, the outputs of the group of which are connected with the information inputs of the first switch group of the address by line, the address counter of the record for the frame, the outputs of which are connected to the information inputs of the first, the switch group of the address by frame, which, in order to improve speed and simplify the device, it contains the scanning start registers on the frame and on the line and counters of the current address on the line and on the frame, the outputs of the counters of the current address on the line and frame are connected to the information inputs of the second groups, respectively, of the switch address and the row switch and the address of the frame, the outputs of which are connected respectively to the address inputs of the first and second groups of the memory block, the outputs of which are connected to the information inputs of the driver The signal, the first output of the interface block is connected to the control inputs of the recording of the write address counter on the row and frame, the second output to the counting input of the write address counter on the line, the output of which is connected to the counting input of the frame write address counter, with the control inputs of the address switches line and frame and memory control input of the memory block, the third and fourth outputs - with the recording control inputs, respectively, of the scanning start registers in the line and frame, the outputs of the junction block group are connected to the memory inputs of the address of the entry for the row and frame, the start scan registers for the row and frame of the memory block, the input of the interface block is the input of the device, the outputs of the scan start registers for the row and frame are connected to the information inputs of the current address of the current row and frame, the second output of the synchronization unit is connected to the control input of the current address counter recording by the frame, the count input of which and the control input of the current address counter recording are connected to the third you by the synchronization block, the fourth output of which is connected to the counting input of the current address counter by line. +0 Compiled by I.Zaginayko Editor N, Tupitsa Tehred L. Oliynyk Proofreader V. But ha Order 5699/46 Circulation 433Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Yu four 50 56