SU1251062A1 - Device for displaying information - Google Patents

Abstract

The invention relates to computing and can be used for implementing graphic information from a computer. The aim of the invention is to improve the speed. The device contains two pulse generators, a synchronization block, a counter, a block of buffer memory, three switches, a register, a gateway block, a video game shaper; alov, trigger, element OR, and shaper number zero. The speed response is provided by the introduction of elements that provide an accelerated zeroing of the buffer memory block, 2-yr.

Description

The invention relates to computing technology and can be used to output information from a computer to control panels, for example, numerical control devices for controlling machine tools.

The purpose of the invention is to increase the speed of the device.

1 shows a block diagram of the device; Fig. 2 is a block diagram of the conjugation block.

The device contains the first pulse generator 1, synchronization unit 2, counter 3, buffer memory block 4, first switch 5, register 6, interface block 7, video signal generator 8, second pulse generator 9, second switch Yu, first trigger 11, element OR 12, the unit 13 code number zero, the third switch 14, the channel transceiver 15, the decoder 16 commands, the second trigger 17, the third trigger 18 output 19 of the device.

The oscillators 1 and 9 are pulse generators, for example multivibrators, the frequency of the second generator 9 being higher than the frequency of the first generator 1. The frequency of the first generator 1 is chosen so that the frame rate of the image corresponds to the standard frequency of 50 Hz. The frequency of the second generator is chosen as high as possible to ensure the minimum zeroing time of the block 4 of the buffer memory and is limited by the speed of the memory elements.

The synchronization unit 2 comprises in its basis a counter (frequency divider) and logic elements for generating synchronizing pulses of the required duration and frequency. From the first output to the counting input of counter 3, the frequency is received, determined by the number of points on the screen, from the second output, the frequency of the video signal is received from the third output through the element OR 12 to the installation input of the counter 3 to O, the frequency equal to the frame scan frequency - 50 Hz „Counter 3 is completed according to the scheme of a binary non-reversible counter with sequential transfer, having a counting input and an installation input to O.

The buffer memory unit 4 is a set of memory elements, static or dynamic. Register 6 is a static register with parallel recording of information and output of information in a parallel code. Switches 5, 10, and 14 are a set of switching logic gates; elements and are distinguished with only the number of switchable bits. The number of bits of the first switch 5 is equal to the number of address bits of the block 4 of the buffer memory. The number of bits of the third switch 14 is equal to the number of bits of the data of block 4 of the buffer memory. Second switch 10

5 switches only one circuit. Video driver 8 is a parallel-to-serial code converter and basically contains a shift register,

0 which is controlled by signals from synchronization unit 2.

The trigger i1 is a trigger with the separation inputs of the installation in O and 1. Setpoint 13

5, the number zero code is an element at the output of which potential O is permanently set.

The interface block 7 consists of channel transceivers I5 for

0 coordination with the mainline of the computer (not shown), decoder 6 commands trigger. -1.7 to generate the control signal of the first switch and trigger 18 for generating the Read-Write signal for the buffer memory unit 4 (the device has increased the decoder's capacity for generating the Reset signal, which is stored in the trigger 11).

Q The device works as follows.

In the first mode, information is output from the computer to the block 4 of the buffer memory. The trigger 11 is in the initial state; therefore, the output of the interface unit 7 is connected to the information input of the block 4 of the buffer memory through the third switch 14. The address of the cell into which information is to be entered is recorded in register 6. Record mode is set at the control input of the buffer memory block 4, the address input is connected to register 6 via the first switch 5, which switches over the signal of the first output of the interfacing block 7, after which at the second output of the conjugation block 7 occurs

five

data which, via the third switch 14, is written to the buffer memory unit 4 at a given address.

In the second mode, the device operates autonomously, since trigger 11 is in the initial state, the frequency from the first generator 1 is fed to the input of the synchronization unit 2 via the second switch 10. The address input of the subconnect buffer memory unit 4 through the first switch 5 to the counter output 3, the contents of which are sequentially changed from zero to a number defining the maximum address of the memory location. The third output of block 2 of synchronization with the frame-frequency of the frame-evertka receives the impulses of setting the counter 3 to 0, the control input of the block 4 of the buffer memory is set to Read, and the data from the block 4 of the buffer memory is fed to the input of the imager 8 of video signals and the clock pulses from the output of the synchronization unit 2 arrive at the output 19 of the device. Thus, all the information recorded in the block 4 of the buffer memory enters the output 19 of the device to which the display unit is connected (not shown). The frequency of oscillator 1 is chosen such that the output of the entire array of information from block 4 of the buffer memory occurs at the standard frequency of 50 Hz.

In the third mode, by a computer command, a trigger 11 is set from the fourth output of the interface 7 and the counter 3 is set to O through the element OR 12. The third switch 14 switches on the output signal of the trigger output and sets the output of the setter to the information input of the buffer memory 4. 13 codes of the number zero. To the input of the synchronization unit 2, the second generator 9 is connected through the second switch 10, which has a higher frequency relative to the generator 1. The counter 3 sequentially goes through all the addresses of the memory cells and sets the trigger 11 to its initial state after overflow. cell block 4 of the buffer memory is recorded O. The frequency of the generator 9 is selected isho

5 10 15 20 25 h

50

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d of memory card items.

Claims (1)

Invention Formula A device for displaying information, containing the first pulse generator, a synchronization unit, the first output of which is connected to the counter 1m input, and the second output connected to the clock input of the video signal generator, the output of which is the device output, the first switch, whose address input is connected to the output the counter, the information input is with the register output, and the control input is with the first output of the interface block, the first input of which is the device input, the buffer memory block, the address input of which is the output of the first switch, and the output of the information input of the video signal imaging unit and the second input of the Interface block, the second output of which is connected to the register input, and the third output with the control input of the buffer memory block, in order to speed, it contains the second pulse generator, the second switch, the trigger, the OR element, the setting code of the zero number and the third switch, the address input of which is connected to the second output of the interface unit, the information input - with the output of the setting device The number zero, the output is for the information input of the buffer memory block, and the control input is for the trigger output, the first input of which is connected to the fourth output of the interface block, and the second input is for the counter overflow output, the first and second information inputs of the second switch connected to the outputs of the first and second pulse generators, respectively, the control input to the trigger output, and the output to the input of the synchronization unit, the third output of which is connected to the first input of the OR element, the second input of which is connected to the quarter The output of the interface unit and the output are with the installation input into the About counter. Editor E. Kopcha Compiled by L.Abrosimov Tehred O. SopkoCorrector S, Cherni 4411/45 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, d, 4/5 Production and printing company, Uzhgorod, st. Project 4 LLF 2