SU1499398A1 - Device for displaying information on crt screen - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in devices for displaying information on a screen of a cathode ray tube (CRT) from a computer. The purpose of the invention is to increase the speed of the device. The device contains the first 1 and second 2 blocks of RAM, the first 3, second 11 and third 23 registers, 4 symbol generator, modulation block 7, CRT 8, control block 9, adder 10, first 12 and second 13 blocks of AND elements, the element OR 24 with the corresponding links. The control unit 9 generates the read addresses of the memory unit 1, according to which the character codes are read from the memory unit 1 and pass through the register 3 to the input of the 4-character generator. The binary representation of the characters is written through register 3 into memory block 2, from where modulation block 7 is read into CRT 8. When writing information, the write address is entered at input 28 into register 11, and, as it passes through adder 10, enters the address input of the block 2 memory, for the information input of which the code of the information being changed is fed. Thus, an increase in speed when recording information in the process of image formation is provided. 1 il.

Description

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holds the first 1 and second 2 blocks of the RAM, the first 3, the second il and the tertiary 23 registers, the 4 character generator, the modulation block 7, the CRT 8, the control block 9, the adder 10, the first 12 and the second 13 blocks of elements And, the element OR 24 with related communications. The control unit 9 generates the readout addresses of the memory unit 1, according to which the codes SIM1 of the tin are read from the block. 1 memory and passed through register 3 to the input of the generator 4 characters. Binary representation of characters

is written through register 3 to the block. 2 memory, from where the modulation unit 7 is read onto the screen of the CRT 8. When writing information, the write address is entered at input 28 in register 11 and, pass worm, adder 10, is fed to the address input of block 2 memory for information the input of which is given the code of the information being changed. Thus, a higher speed of writing information is provided in the process of imaging. 1 il.

The invention relates to automation and computer technology and can be used in devices for displaying information on a screen of a cathode ray tube from a computer.

The purpose of the invention is to increase the speed of the device.

The drawing shows a functional block diagram of the device.

The device contains the first RAM block 1, the second RAM block 2, the first register 3, a 4-character generator consisting of the first permanent memory block 5 and the raster line former 6, the modulation unit 7, the cathode ray tube . (CRT) 8, control block 9, adder 10, second register 11, first block 12 of elements I, second block 13 of elements I.

Control unit 9 contains a pulse generator 14. pulses 15, the number of elements of the expansion of characters along the X coordinate, counter 16, the number of characters in the rows of displayed symbolic information, the counter 17 of the number of elements. decomposition of characters along the Y coordinate, counter 18 of the number of lines of displayed symbolic information, decoder 19, second block 20 of the constant memory of control microcommands, decoder 21 of the main mode codes, register of the 22 main mode codes, third register 23, the OR 24 element. The circuit also denotes the inputs 25-32 of the device, the outputs 33-38 of the counters of the control unit 9, the inputs 39-61 of the second fixed memory unit 20, the outputs 62-64 of the decoder 21, the outputs 65 and 66 of the second register 11, output

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67 of the second block 13 elements And, the output 68 of the generator 1A synchronization pulses.

The device works as follows.

During operation of the control unit 9, the generator 14 generates pulses that synchronize the operation of the entire device. With his release im. The pulses arrive at the inputs of the modulation unit 7 (input 68) and the counter 15. The pulses of transfers from the second input of counter 15 arrive at the first input of counter 16, the pulses of transfers from the second output of counter 17 arrive at the first input of counter 18.

The device status codes from the first outputs of the counters 15-18 (outputs 33-36) are fed to the first, second, third and fourth inputs. a decoder 19 connected to the memory unit 20.

With the help of block 20, in which the codes of microinstructions are recorded, all the main signals controlling the operation of the device are generated.

At output 39 of block 20, a signal is written to Write 2, at output 40 a signal is read from block 2, on. output 41 - signal Record in block 1, output 42 - signal Read from block 2, output 43 - signal Read from block 5, output 44 - signal Record in driver 6, output 45 - signal Record in block 7, on output 46 - the signal is the beginning of the line, and output 47 - the signal is the beginning of the frame, at the output 48 - the signal is a return stroke on the line, at the output 49 - a signal

50 - signal Record of the fourth sub-register of register 3, output 51 - signal Reset of the fourth sub-register, output 52 - signal Record from the third sub-register, output 53 -. signal Reset the third sub-register, output 54 - signal Record the second sub-register, output 55 - signal Reset the second sub-register, output 56 - signal Record the first sub-register, at course 57 - signal Reset first sub-register, output 58 - the Tubney signal, the first trigger of register 11 is charged, the second is reset.

Through register 3 (the first sub-code of the characters in the exchange mode with the J1O EB, input 26 goes to the first I of memory 1, where they are written in successively located ki in order of arrival at its input.

According to the signals from the outputs of block 9 in the mode of the formation of ras, they are selected from block 1 and pass alternately through register 3

The initial reset of register 3 (register 3 so-15 (second sub-register) to generator 4 is from one of three subregisters), on; Output 59 is the output signal of Ready characters.

From the output of block 5 of the permanent memory, the codes corresponding to the rows of the television decomposition

 to receive a code for a computer (not shown |), at output 60, the signal to transfer to counter 17 from counter t6j at output 61 is the reset signal of counters 15-18.

Counters 16 and 18 form addresses of the first memory block 1 (memory of characters 1vol) at outputs 37 and 38, counters i16 and 18 form addresses of the second memory block 2 (raster memory) at: outputs 35 and 38. Additionally addresses generated by counters 17 and 18 are used to control blocks 5 and 6 of the 4-character generator (outputs 35 and 37).

The control unit 9 implements three basic modes of operation of the device. The mode number that is currently being implemented is recorded from the computer to register 22 at input 27. Register 22 is reset by a signal from the computer at input 30 all

From the output of block 5 of the permanent memory, codes corresponding to the raster lines of the television symbol decomposition of the symbols of the ox, are fed to the former 6 of the solution line and through register 3, (the third sub-register) are entered into the second memory block 2.

In the regeneration mode of the raster, information words with the length of kht bits go through register 3 (fourth sub-register) into modulation unit 7 (k is the number of characters per line, m is the length of the line for one code character).

thirty

Using the register 11, the first and second modes of operation of the device can be modified. Platoon on entry 28 and dropping on

By entering 32 triggers of register 11, the device can be brought out of the ground state and transferred to modified states. In these cases, a tur -: device dock may be reflected when switching to a new mode of operation 0, since the output 65 of the first bit of register 11 controls the passage of addresses in block 1 through the first block 12

; After switching on the device, its general reset is made, and to the registers

22, 11 and 23 are written zeros.

I

A4puls Obptsy reset comes from the computer at input 28. In register 11, this pulse enters the element OR 24. Then, the register 22 records the main mode code at input 27, which enters the input of the decoder 21. From the outputs of the decoder, the corresponding signal at the outputs 62, 63 or 64 enters the inputs of the depotfrater 19 and transfers the memory block 20 to the area of micro-instructions serving the selected mode. Register 11 on input 28 writes device basic status code 10. Register 23 remains cleared. Mainly 1

elements And from the outputs of the counters 16 and 18 of the control block 9, and the output 66

45 of the second bit of register 11 controls the passage of addresses in block 1 through the second block 13 of AND elements from the output of register 23.

This allows you to record or

50 reading information in block 1 in the order of formation of addresses in the counters of block 9 ip in an arbitrary order depending on the contents of register 23 entering the device from

55 computers at the entrance 31. If only one register trigger 11 is cocked, adder 10j through which the addresses arrive at the input of block 1, serves as the OR element; And passes the addresses into block 1 without iz;

They are the first trigger register 11 is cocked, the second is reset.

Through register 3 (the first sub-code of character codes in the exchange mode with the J1O computer, input 26 is received at the first input of memory block 1, where it is written into successive cells in the order of arrival at its input.

According to the signals from the outputs of the control block 9 in the raster formation mode, they are selected from block 1 and pass alternately through register 3

(second sub-register) to generator 4

characters.

From the output of block 5 of permanent memory, codes corresponding to the raster lines of the television decomposition of symbols are fed to the former 6 of the solution line and through register 3, (the third sub-register) are entered into the second block 2 of memory.

In the raster regeneration mode, information words with a length of kht bits go through register 3 (fourth sub-register) into modulation unit 7 (k is the number of characters in the string, m is the length of the video code of one character).

Using the register 11, the first and second modes of operation of the device can be modified. Platoon on entry 28 and dropping on

input 32 triggers register 11, you can withdraw the device from the ground state and transfer to the modified state. In these cases, the tur -: device docking may be as the output 65 of the first bit of the register 11 controls the passage of the addresses in block 1 through the first block 12

one

elements And from the outputs of the counters 16 and 18 of the control block 9, and the output 66

45 of the second bit of register 11 controls the passage of addresses in block 1 through the second block 13 of AND elements from the output of register 23.

This allows you to record or

50 reading information in block 1 in the order of formation of addresses in the counters of block 9 ip in an arbitrary order depending on the contents of register 23 entering the device from

55 computers at the entrance 31. If only one register trigger 11 is cocked, adder 10j through which the addresses arrive at the input of block 1, serves as the OR element; And passes the addresses into block 1 without iz;

jeneni If both the triggers of Registry 11 are set, the current addresses from the block are added to positive or triad addresses that come from the computer through blocks 23 and 13. In this case, the information can be recorded and read in any order in relation to the addresses formed by the counters of block 9 (for example , with the purpose of the shift is depicted on a CRT screen),

In case both triggers are reset, AND elements of blocks 12 and 13 stop passing addresses from both sources and write or read in block 1 is stopped.

After completion of the modification of the mode, register 11 is reset by a pulse from the computer at input 32 and a code corresponding to the new state of the device is written to it. After completion of the exchange, the contents of register 23 are reset every time by a pulse from a computer at input 25 and a new address is written to it at which new information will be written or recorded at the new stage of operation of the device.

Thus, the invention provides an increase in the speed of the device by recording information at arbitrary moments in time during the formation of a graphic image.

Claims (1)

Invention Formula A device for displaying information on the screen of an electron-beam tube containing the first and second blocks of RAM, the first register, the symbol generator, the modulation unit, the control unit, the adder, the first block of elements And the second block of elements AND, the second register, the recording control input which is connected to the output of the OR element, the first input of which is the first input of a device reset, the information input of the character code of which is the first information input of the first register, the first and second outputs of which connect They are connected to information inputs of the first and second RAM blocks, respectively, whose outputs are connected to the second and third information inputs of the first register, the control input of which is connected to the first output of the control unit, the second output of which connected to the sync input of the modulation unit and is the output of the device's frame pulse, the third output of the control unit is connected to the recording control input of the first RAM block, the recording control input of the second RAM block is connected to the fourth output of the control unit, the fifth output of which is connected the first input of the first block of elements And, the second input of which and the first address input of the second RAM block are connected to the sixth output of the control unit and are the first address input of the device oystva, rhod second address of the second block RAM memory and the first address generator input the characters are connected to the seventh output of the control unit, the eighth output of which is connected to the clock input of the character generator, the read and write control inputs are connected respectively, with the ninth and tenth outputs of the control unit, the eleventh output of which is connected to the recording control input of the modulation unit, whose information input connected to the third output of the first register, the fourth output of which is connected to the second address input of the character generator, the output of which is connected to the fourth information the input of the first register, the gate input of the control unit is connected to the output of the second register, the information input of which is the input of the status code of the device, the input of the mode code of which is an information input of the control unit, the first reset input of which is the second input of the device reset, the twelfth output of the control unit is connected to the clock input of the modulation unit whose output is connected to a cathode-ray tube modulator, in order device, it contains a third register, the output of which is connected to the first input of the second block of elements And, the output of which is connected to the first input of the adder, the output of which connected to the address input of the first memory block the output of the first block of elements AND connected to the second input of the adder, the second input of the element OR, the control inputs for 9 149939810 the control unit and the third input of the device, the second input the register is the control input of the second block of elements AND is connected recording the device, the third input to the output of the second register, the thirteen scrambling of which is the reset input, the output of the control unit is the third register, the information output of the ready signal of the input device of the second address.