SU1432529A1 - Apparatus for monitoring logical modules - Google Patents

Abstract

The invention relates to computing and automation and can be used in the construction of automated systems for monitoring and diagnostics of digital units. The aim of the invention is to increase the depth of control. The device contains a multiplexer 2, a signature analyzer 3, first, counter 4, second counter 5, switch 6, test generator 7, mask register 8, elements IL 9, 10, AND-NE elements 11, 12, delay element 13, trigger 14, a generator of 15 sync pulses and a mask setting unit 16. Not only is the generalized signature of the inputs-outputs of logic block 1 formed, but also the signature of any of the inputs-outputs of block 1, as well as the signature of any control point inside block 1, which greatly expands the diagnostic capabilities of the device. Switching manipulations are significantly simplified when block 1 is connected to a device. The switch consists in setting a mask in the register by means of an input device for entering the data on the inputs-outputs of block 1. In addition, the user can test the test generator using a signature analyzer when writing to the mask register of logical zeroes and the absence of block 1 In this case, the information from any of the outputs of the test generator can be analyzed using a signature analyzer and compared with the standards of 1 sludge. (L

Description

W. W

The invention relates to computing technology and automation and can be used in the construction of av. 1 | The automated systems for monitoring and diagnostics of digital: blocks.

The purpose of the invention is to increase the depth of control of the device. ; The drawing shows a functional block diagram of the device.

The device contains a controllable logical block 1, a multiplexer If a signature analyzer 3, counters A and 5, a switch 6, a generator

7 tests, mask register 8, elements 1 and 9 and 10, AND-NOT elements 11 and 12, delay element 13, trigger 14, clock generator 15, mask setting unit 16.

I The device operates as follows.

When the power is turned on, the state of the counters 4 and 5, the generator 7 tests of the signature analyzer 3, register

8 masks and trigger 14 - arbitrary pulses from generator 7 through IL-9 and 10 elements arrive at the counting inputs of counters 4 and 5. The occurrence of a logic level 1 at the high-order output of counter 5 blocks passage through the element OR 9 to the counting input of counter 5. Last remains in a fixed state.

; A short-term level I logical O output overflow of counter 4 (where n is the number of inputs and outputs of block 1) causes the trigger 14 to be set to one after which the pulses from the generator 15 through the element OR -10 are stopped to the summing input of the counter 4. The L-active signal level at the input of the initial installation of the device, the counter 4 and the signature analyzer are reset to the zero state and the test generator 7 is set to the initial state. The device is ready for further work.

Through block 16 to register 8

masks record information on the input-output of block 1. The outputs correspond to logic levels 1, inputs to logical O. Since the outputs of register 8 of the mask are connected to the control inputs of switch 6 with output states, it is either with high output resistance at level

0

0

0

5 0 5

0

not logical 1 at the control input, or in the mode of information transfer from the information input to the output at the logic level O at the control input. The recording, in register 8 of the information mask in this manner, provides for the transfer of test information from the generator outputs 7 tests to the contacts of the information connector of block 1, which is the inputs, and the high-resistance state on the contacts of the information connector of block 1, which are outputs.

Further operation of the device is possible in two modes: Monitoring and Diagnostics.

Control mode.

By the L-active signal level at the input of the setting of the operating mode. The control of the device trigger 14 is reset to the zero state, thereby allowing the passage of pulses from the generator 15 through the element. OR 10 to the summing input of the counter 4 and through the element AND-NOT 11 and the element 13 of the delay to the synchronous input of the signature analyzer Z. With the arrival of each pulse, the counter 4 changes its state. The code n the lower bits of counter 4 is supplied to control multiplexer 2, the input state of the multiplexer, which is connected via a probe to the control point of block 1, is transmitted to the information input of the signature analyzer 3, which is synchronized with a delay time determined by the response time of the block 1, comes a clock pulse.

Next, multiplexer 2 performs enumeration of input-outputs of unit 1 in accordance with the address generated by counter 4. Signature analyzer 3 generates a signature 2 -1 of input-outputs of unit 1 as a response to the initial test effect of the test generator 7, and at the same time controls the generator. 7 tests . After passing 2–1 pulses, the counter 4 interrupts the short-term L-active signal, which arrives through the AND-HE element 12 to the synchronous input of the generator 7 tests. The latter changes its state and sets the following test pattern at the outputs. The polling process using multiplexer 2 of block 1 is repeated. Signature analyzer 3 continues to form a generalized

signatures. The process of forming a generalized signature of the control object continues until 2-1 test generator combinations of 7 tests are exhausted (where k is the number of tests) and counter 4 forms a short-term L-active signal that sets trigger 14 into one state, what prevents the passage of sync pulses from the generator 15 to the summing input of counter 4 and through the NANDI element 11 and the delayed element 13 to the synchronous input signal of the signature analyzer 3. The formation of the generalized input-output signature is completed. The numerical value of the signature is provided to the user for decision. The matching of the signature with the reference one corresponds to the good condition of the control object, the discrepancy indicates the presence of defects inside the control object, i.e., operation mode. The device control allows the control to be carried out according to the principle of good or bad.

Further, the Device Control operation mode can be repeated by forming an L-active screen at the input of the Device Control operation mode assignment.

Diagnostics mode.

In this mode, the user is given the opportunity to localize the defect in block 1 with exact- (I / O step, and using the information probe with the accuracy of the control object circuit. In diagnostics mode, counter 4 is used to set the I / O address of block 1 s using pre-set inputs. The output code of the counter determines the input-output of unit 1 connected to the information input of the signature analyzer, or the input of multiplexer 2, which is an information probe. The input-output address is given by After forming the initial setup signal with the L-active level at the device setup input, Device Diagnostics, counter 5 is reset to zero, which blocks the passage of pulses from the generator 15 through the OR element 9 to the counter input of the counter 5, through the AND-NOT elements 12 and 11 to the generator clock inputs of 7 tests and, through element 13, the delay to the clock signal of the signature analyzer 3, respectively

stately. In response to each test action with a time delay (element 13), which is necessary for testing the test unit 1, a sync pulse arrives at the input of the signature analyzer. The number of testing cycles is determined by the counter size of the counter 5. After 2-1 pulses (t-number of monitoring cycles), the output of the higher bit of the counter 5 sets the logic level 1. Pulses passing to the test generator 7 and the signature analyzer 3 are blocked. The generated signature of any input-output unit 1 or any point of the circuit connected to the information probe is provided to the user for decision.

Claims (1)

Invention Formula 25 thirty 35 40 A device for controlling logical blocks, comprising a clock generator, test generator, multiplexer, signature analyzer, two counters and a delay element - the information input of the signature analyzer is connected to the output of the multiplex-exore, the output of the delay element is connected to the synchronous input of the signature analyzer, a group of address inputs of the multiplexer A group of bits of outputs of the first counter is characterized in that, in order to increase the depth of control, the device contains two AND-NOT elements, two IL elements, which Mutator, trigger mask register, specifying unit 45  masks, the outputs of the mask setting block are connected to the information inputs of the mask register, the output of the mask change attribute of the mask setting block is connected to the synchronous input of the mask register, the outputs of which are connected to the switch inputs, the information inputs of which are connected to the test generator outputs connected to the group of information inputs of the multiplexer and is a group of outputs of the device for connection to the inputs-outputs of the controlled logic unit, the first inverse bit output the stroke of the first counter is connected to the first input of the first NAND element, the output of the ifOTOporo is connected to the synchronous input of the test generator, the second input is first 50 55 I-NOT element is connected to the output of the rjtepBoro element ШШ, with the counting input of the second counter not by the first input of the second AND-NE element, the second bypass of which is connected to the output of the second OR element and with the counting input of the first counter, the output of the second I-NE connected to the input element The inverse reset trigger input is the input of the device control mode setting, the signature analyzer reset input is connected to the device initial setup input, with the reset inputs of the first counter, with input- test generator initial setup house, second counter reset input sockets, the first input of the first element is the input of the setting of the Diag mode OR connected to the output of the clock generator and to the first input of the second element or; the second input of the first element OR is connected to the high output of the second counter, the second input of the OR element is connected to the trigger output, the inverse stroke of which is connected to the second inpac jibiM discharge of the first counter of the device, the information inputs of the first counter are connected With the bus for setting the starting address of the input-output of the monitored logical unit of the device, the information input of the multiplexer is the input of the device for connection to the control point of the monitored logic unit. The inverse reset input of the trigger is the input of the setting of the Device Control mode, the reset input of the signature analyzer is connected to the input of the initial installation of the device, with the reset inputs of the first counter, with the input. test generator initial setup house, second counter reset input is the diag mode setting input; it is the device diagnostics mode setting input, the information inputs of the first counter are connected to the initial input address address of the monitored logical block of the device, the multiplexer information input is the input of the device for connection to the control point of the monitored logic block. Editor E. Papp Compiled by A.Sirotska Tehred M.Didyk Proofreader V.Romanenko Order 5442/42 Circulation 704 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Vaushsk nab., 4/5 Subscription