SU1256032A1 - Device for checking logic units - Google Patents

Abstract

The invention relates to automation and computing and can be used in the control of microchips. The purpose of the invention is to expand the functionality by enabling the control of logic blocks with different pin assignments, ground and power. The device comprises a synchronization unit, a clock pulse generator, input / output detection units, power switching units, a key, a signature analyzer. When the synchronization unit is turned on, the logical "O" switches over the key and goes to any input of the logical unit that is different from the output "power and ground." Due to the presence in the design of a controlled logic block (LAZ chip 155), for example, a diode, between the input and the common ground bus, this logical "O passes to the ground bus" to which one of the power switching units is connected, turns it on, and the power and "O is automatically connected with to the corresponding pins of the chip. The remaining switching units do not affect the controlled chip due to the high impedance state at the output. 1 h. apt. 5 il. (Lu you ate about from 1HE

Description

The invention relates to computing and automation and can be used to automatically monitor the health of digital integrated circuits.

The purpose of the invention is to expand the functionality by enabling the control of logical blocks that are different in location to the earth and power terminals.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block synchronization diagram; in fig. 3 is a block diagram of an input / output detection unit; in fig. 4 - key scheme; in fig. 5 is a diagram of a power switching unit.

The device for controlling logical blocks (Fig. 1) contains a clock pulse generator 1, a counter 2, an input / output detection block 3.1-З.p, a signature analyzer 4, a synchronization block 5, a monitored block 6, a key 7, blocks 8.1-8. P / 2 switching "power (n - the number of outputs of block 6).

Synchronization unit 5 (Fig. 2) contains a switch 9 and one-shot 10-12, implemented on integrated circuits (IC) K155AGZ.

The input / output detection unit (Fig. 3) contains an emitter follower 13, which includes a transistor 14 (type KT325) and a resistor 15 (100 Ω), an element NOT 16 implemented on an IC K155LAZ, elements AND-NOT 17 and 18 implemented on the IC K155LA8 and D-trigger 19.

The key (Fig. 4) contains a transistor 20 and a resistor 21 and is a transistor switch assembled according to a circuit with a common emitter and an open collector.

The power supply switching unit (FIG. 5) contains a D-flip-flop 22 implemented on an IC K155TM2, and switches 23 and 24 assembled according to a circuit with a common emitter and an open collector and containing transistors 25, 26 and resistors 27, 28.

The operation of the device is based on the principles of signature analysis. All possible binary combinations are fed to the inputs of the monitored block, the signals from all outputs of the monitored block are converted using a parallel signature analyzer into a four-bit hexadecimal code (signature), which is compared with a reference value calculated or obtained from a known good block.

When switch 9 is in the “Reset” position (as shown in FIG. 2), all units of the device are disconnected from monitored unit 6 (the corresponding pins are in a high impedance state). When the switch 9 is closed, the one-shot 10 and 11 are started. The duration of the pulse generated by the one-shot 11 must be less than the length of the pulse at the output of the one-shot 10.

A positive impulse at the output of the single-vibrator 10 turns on the key 7, which causes the supply of a logical zero to a different output from the monitored block 6. The power and the monitored block are not yet connected. In this case, a logical zero appears at the output of the ground of the monitored block 6 (due to the presence of a diode between the inputs of the chip and the common bus) and passes to the corresponding block 8.

On the leading edge at the inverse output of the one-shot 11, the trigger 22 of the block 8 is set to the zero state, the keys 23, 24 are opened and the power supply and the ground are supplied to the corresponding outputs of the monitored block. The remaining blocks 8 do not affect due to the presence of high impedance at the outputs of the keys 25 and 26.

At the end of the pulse at the output of the single-vibrator 10, the one-shot 11 is started. On the leading edge of the pulse at the inverse output of the one-shot 12, an I / O detection block opens, which begins to transmit signals generated by the counter 2 to the inputs of the monitored unit 6. By the output signal the overflow of counter 2 signals from the inputs and outputs of the monitored block 8 begin to flow into the signature analyzer 4. On the next edge of the overflow signal of the counter 2, the reception of signals into the signature analyzer 4 ends and s Gatura, formed on the basis of received signals, is displayed on the indicator board of the signature analyzer. On the next front of the overflow signal of the counter 2, the reception of the signals to the signature analyzer begins again; this procedure is repeated periodically. Blocks 3 are made so that each of them opens with the signal of the one-shot 12 only if at the moment prior to the arrival of this signal a potential characteristic of the block input is present at the corresponding output of the monitored block 6 (for TTL-logn, order 1, 3 V) . Otherwise, if there is a potential at the output of the monitored block characteristic of the output of the block (0.4 V or 2.3 V), the detection block 3 of the inputs remains closed and has no effect on the monitored block 6.

The difference in the input from the output is as follows. If the output of block 3 connected to the monitored block 6 contains a zero potential (0.4 V), the latter sets the element AND- NOT 17 to a state in which a high voltage level appears at its output, which is supplied to D the trigger input 19, as a result of which, at the moment the control signal arrives from the single vibrator 12, the trigger 19 is set to one (which corresponds to a low level at its inverse output), and the open collector element 18 remains closed. The same thing happens if at the output connected to the monitored block 6 there is a single potential (2.4 V), only in this case the low level at the input of the AND-NOT element 17 comes from the output of the element 16. If the output controlled block 6 is the input potential, then the last at the output of the emitter follower 13 assembled on the transistor 14 and the resistor 15, where the voltage drops from 0.7 to 1.0 V, will be equal to about 0.4 V. the appearance at the output of the element is NOT 16, and consequently, at one of the inputs of the element and AND-17 high level. Since the current at the second input of the NANDI element 17 is practically absent, a low level will be set at its output, as a result of which, after the arrival of the control signal from the single-oscillator 12, the flip-flop 19 is set to the state at which the element 18 opens and thus the submission of test combinations to these findings of the controlled block.

The power switching units are designed so that the keys 23 and 24 are opened only if there is zero potential at the corresponding output of the monitored block 6 before the arrival of the control signal from the one-shot 11. Otherwise, the power switching unit remains closed and has no effect on the monitored unit.

Connecting the "power and" land is as follows. When entering a non-monitored output of a monitored block (for K series 155 microcircuits, you can select, for example, the first output as such output) of a zero potential, this potential is obtained at the output of the monitored unit’s ground and passes to the O-input of the trigger 22 of one of the blocks 8. When the control signal is received from the single vibrator 11, the trigger 22 of this block 8 will go to the zero state, the keys 23 and 24 will open and the corresponding terminals of the monitored block 6 will be energized and grounded. (The potential at the output of the power supply will be equal to E, and at the output of the earth it will be zero, since the value of E takes into account the voltage drop on the open transistors 25 and 26 of the current switches 23 and 24). In the remaining blocks of the “power and ground” switch 8, the current at the O input of the flip-flops 22 is practically absent; therefore, these flip-flops remain in one state, and the corresponding keys 23 and 24 are closed.

In the device, it is possible to completely get rid of co-mutations due to the fact that not only the inputs and outputs, but also the outputs of the power supply and the earth of the monitored unit are automatically identified and connected. Also, a separate reference block is not required for each type of controlled

blocks. Anyway, the device can be used to automatically identify logical blocks, since each type of CC blocks:,) has its own signature.

Claims (2)

1. A device for monitoring logic blocks, containing a synchronization block, 0 counter, n blocks of input / output detection n - number of outputs of the monitored logic block), clock generator, the output of which is connected to the counter input of the counter, which bit outputs are connected to information 5 inputs I / O detection block, the synchronization inputs of which are connected to the first output of the synchronization block, the outputs of the one-output detection blocks are connected to the corresponding inputs / outputs of the monitored .ugistic  block, characterized by the fact that, in order to extend the functionality by enabling control of logic blocks with a time, the first arrangement of the terminals "power and power", the device contains a key, n / 2 b, power supply switches and a signature analyzer the second output of the synchronization unit is connected to the inputs of the initial installation of all input / output detection units and power switching units, the third synchronization unit is connected to the control input of the key, whose information input is connected to zero Device for a building .roystva, the key output is connected to the input /-.m ((1 ... n) controlled by a logic unit, first and second outputs of blocks 5, the power switching is connected to the corresponding inputs / outputs of the monitored logic block and the information inputs of the signature analyzer, the synchronization inputs of the power switching units are connected to the fourth output of the synchronization unit, the output of the clock generator is connected to the synchronous input of the signature analyzer, the enable input of which is connected to the overflow output of the counter.  : 2. The device but paragraph 1. is different that the power switching unit contains a D-flip-flop and two keys, the inverse S-input of the trigger is connected to the input of the initial installation of the block, the synchronization input of which is connected to the synchronous input) tri1 0 ger, the direct and scientific outputs of which are connected to the control inputs the first and second keys, the information input of the first one is connected to the first unit potential, the information input of the second key is connected to the zero potential bus, the output 5 of the first k. 1ucha connected to the first output of the block, the output of the second key with the D-c. Trigger code and the second output b. yuk FIG. fig.g /four If fig L D 26 28 Editor S. Patrusheva Order 4825/49 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, 4/5, Raushsk nab. Branch PPP "Patent, Uzhgorod, st. Project, 4 Srig. Compiled by A. Sirotsk Tehred I. VeresKorrektor M. Maksiminshnets Circulation 671 Subscription