SU1709318A1 - Device for checking digital units - Google Patents

Abstract

The invention relates to digital technology and can be used to control digital blocks containing a structure with arbitrary logic, microprocessor-based LSIs and feedback circuits. The purpose of the invention is to expand the functionality by detecting the circuits involved in the short circuit. The device allows detecting situations of increasing the internal current of the monitored unit without using a reference. 3 il.

Description

The invention relates to digital technology and can be used to control digital blocks containing a structure with arbitrary logic, microprocessor-based LSIs and feedback circuits.

A device for monitoring logic blocks is known, comprising a clock pulse generator, a control unit, a reference block, input / output detection units, a counter, display elements, and consumption measurement units. The invention is based on the use of the phenomenon of a sharp increase in the current consumption of a logic unit made on TTL elements with a short circuit-type fault, provided that the values of the logic signals in the closed circuits do not match.

However, the device is characterized by the presence of a reference chip for each chip being tested, which ultimately will lead to an increase in the cost of control.

The closest in technical essence to the present invention is a device for monitoring digital blocks containing a switching element, a resistor, a modulo-two adder, a HE element, a D-flip-flop, and in each input-output determination unit, the output of the switching element is connected to the first input of the adder module two and through a resistor with the second input of the modulo two adder, the output of the modulo two adder is connected via the NOT element with the inverse S-input of the D-flip-flop, whose D input is connected to the device zero-potential bus, inverse R- course of D-flip-flop is connected to the reset input determining unit inputs-outputs.

The drawback of the device is the impossibility of determining the number of sources of logical signals in the monitored circuit necessary for detecting a fault type of short circuit.

The purpose of the invention is to extend the functionality for detecting circuits involved in a short circuit in a monitored digital block when diagnosing mounted circuit boards without using a reference digital block or chip and a second control point, which is required for traditional diagnostic methods.

The goal is achieved in that a device for controlling digital blocks containing a switching element, a resistor, a modulo two, a HE element, a second D-flip-flop, and the output of the switching element is connected to the first input of a modulo-two and through a resistor with a second input adder modulo two, the output of adder modulo two is connected through the element NOT to the inverse S-input of the second D-flip-flop, whose D-input is connected to the zero potential bus of the device, the inverse R-input of the second D-flip-flop is connected to the reset input introduced, the threshold element, the first D-flip-flop, the one-shot, the NAND element, the first and the second indication element, the AND element, the information input of the threshold element connected to the second output of the resistor and the second input of the modulo two and the information input the device, the output of the threshold element is connected to the C-input of the first D-flip-flop, whose D-input is connected to the zero potential bus of the device, the inverse R-input of the first D-trigger is connected to the high logic level bus, the inverse C-input of the first D-flip-flop combined with the inverse R inlet of the second D-flip-flop and is the device reset input, the inverse output of the first D-flip-flop is connected to the first input of the second And element and through the one-shot with the second input of the IEE element, the C input of the second D-flip-flop is connected to the zero potential bus device, the direct output of the second D-flip-flop is connected to the first display element, the inverse output of the second D-flip-flop is connected to the first input of the NAND element and the second input of the second And element, the output of which is connected to the second display element, the output element and I-IU is connected to a control input of the switching element, an information input of which is connected to zero potential bus device.

FIG. 1 shows a block diagram of a device for controlling digital blocks; in fig. 2 and 3 are time diagrams of the device operation.

The device contains information input 1, the threshold element 2, D-flip-flop 3, input 4 reset the device, one-shot 5, the element Y-NOT 6, the switching element 7, the resistor 8, the adder 9 modulo two, the element HE 10, the D-trigger 11 , the display element 12, the element And 13, the display element 14 (see Fig. 1).

On time diagrams (figure 2 and 3)

0 the following notation is accepted: 4 - signal level at input 4 of the device reset;

3- signal level at the inverse output of the trigger 3; 11 - signal level at the forward trigger output 11; 1 - signal level on

5 information input 1 device; 2 signal level at the output of the threshold element 2; 5 - the signal level at the output of the one-shot 5; 6 - the signal level at the output of the element 6 AND-NOT; 7-level signal at the output of the switching element 7; 9 the signal level at the output of the adder 9 is modulo two: a is the state of the elements after switching on the device, and the outputs of the flip-flops 3 and 11 can be in an arbitrary state; b - the state of the elements after the input to the reset input of the device of a short zero pulse; c - the state of the elements after the appearance of logical zero at the information input 1 of the device;

0 g - the state of elements after the appearance of a logical unit on the information input 1 of the device; e - the state of the elements after analyzing the magnitude of the current flowing through the resistor 8, the signal level

5 at information input 1 can be arbitrary.

The information input of the threshold element 2 is connected to the second output of the resistor 8 and to the second input of the adder 9 along

0 to module two and is the information input 1 of the device, the output of the threshold element 2 is connected to the C input of the D-flip-flop 3, the D input of which is connected to the zero potential bus of the device, the inverse R input

5 D-flip-flop 3 is connected to a high logic level bus, the inverse S-input of Dtrigger 3 is combined with the inverse R-BXO of D-flip-flop 11 and is a reset input

4 devices, the inverse output of the D-flip-flop 0 3 connected to the first input element And 13

and through the one-shot 5 with the second input of the element AND-HE 6, the C and D inputs of the D flip-flop 11 are combined and connected to the zero potential bus of the device, the direct output D5 of the flip-flop 11 is connected to the indication element 12, the inverse output of the D-flip-flop 11 connected to the first input of the element AND-NIS; second input of the element AND 13, the output of which is connected to the display element 14, the output of the element AND-NOT 6 is connected to

the control input of switching element 7, the information input of which is connected to the zero potential bus of the device, the output of switching element 7 is connected to the first input of modulator two adder 9 and through a resistor 8 to the modulo two second input of modulator 9, output of modulator two adherent two is connected through the element NOT 10 with the inverse S-input of the D Trigger 11.

Threshold element 2 is a device whose high logic level is set at the output when the voltage at its information input is greater than or equal to the minimum acceptable signal level of the logical unit, for example, the known device included in integrated circuit 521 САЗ.

As D-flip-flops 3 and 11, for example, a known device incorporated into an integrated circuit K155TM2 can be used.

As an element of AND-HE 6, for example, a known device included in an integrated circuit chip K155LAZ can be used.

The three state switching element 7 is a switch, the logic level at the output of which is equal to the logic level at its information input provided that a logic zero signal is applied to the control input, otherwise the output assumes a high impedance state element included in the integrated circuit K155LP8.

As an adder 9 modulo two, for example, a known device incorporated in an integrated circuit K155LP5 can be used.

As an element of HE 10, for example, a known device incorporated into an integrated circuit chip K155LN1 can be used.

As display elements 12 and 14, for example, a known device for displaying binary information with logic levels corresponding to TTL circuits can be used.

As an element And 13 can be used, for example, a known device included in an integrated circuit K155I1.

A single vibrator 5 is a device that, when a signal is dropped at its input from a low logic level to a high one, produces a single pulse. The impulse duration Himp should satisfy the following relationship:

Tact 1imp te.n,

where 1 tick. the duration of the feed cycle input actions;

5te.n. - time the device is exposed to

a controlled circuit, which is determined by the total switching time of the following elements:

tB.n. t3 (9) + t3 (10) + t3 (11) + t3 (6) + t3 (7).

where t3 (9) is the maximum delay time of the adder 9 modulo two when switching from a state of logical zero to a state of logical one (for TTL 1z (9) 22 not);

t3 (10) is the maximum delay time of the element HE 10 two when switching from the state of a logical unit to the state of a logical zero (for a TTL, gz (10) 15 not);

t3 (11) is the maximum delay time of the D-flip-flop 11 two at the transition From the state of logical zero to the state of logical one (for TTL, gz (11) 25 mn);

t3 (6) - maximum delay time

element 6 I-N E two when moving from the state of a logical zero to the state of a logical unit (for TTL gz (6) 22 not);

t3 (7) is the maximum delay time of the switching element 7 for the transition from

the state of a logical zero to the third state (for TTL 1s (7) 25 no).

Thus, for TTL te.n. 109 is not. The operation of the device is based on the fact that in the presence of a short circuit between M (M 2) circuits in the formed path;

- there are M source of logical signals at each moment of operation of the monitored digital unit;

- high logic level (log.CH) is present only when all M logical signal sources are set to one. In the remaining cases, either a low logic level is present (log.O),

or the third state (Z is the state).

The appearance of two or more logical signal sources in a circuit can be detected as follows.

At the time of occurrence in a controlled

chain log. 1, for example, when first occurring, it is necessary to estimate the amount of current flowing through the resistor 8, the first output of which is connected through the open lower transistor of the output stage of the switching element 7 to the device zero potential bus, and the second to the controlled circuit. In this case, a current flows through the resistor, the value of which is proportional to the number of sources of logical signals in the circuit. If the current flowing through a single logical signal source is called nominal, then the actual value exceeds the nominal one two or more times indicates the presence of two or more logical signal sources in the monitored circuit or the presence of a defect) short circuit between the circuits.

The device works as follows.

In the initial state, information input 1 is not connected to the monitored circuit of the digital unit.

To the reset input 4 of the device, a signal is sent in the form of a short zero pulse (Fig. 2.4a; Fig. 3.4a), which sets the inverse output of the D-flip-flop 3 (Fig. 2.3b; Fig. Z.Zv) and the direct output D- trigger 11 (Fig. 2.116; Fig. 3.116) to zero.

At the information input 1 of the device there is a Z-state (Fig. 2.16; Fig. 3.16). The level of the log, O from the inverse output of the D-flip-flop 3 goes to the first input of the element I 13 and to the input of the one-shot 5 (fig. 2.56; fig. 3.56)

The zero from the direct output of the D-flip-flop 11 is fed to the first pin of the display element 12. At the inverse output of the D-flip-flop 11, there is a unit that goes to the second input of the AND 13 element and to the first input of the NAND element 6, At the output of the AND 13 element there is a zero that goes to the first output of the display element 14. At the output of the element AND-NE 6 there is a unit (Fig. 2.66; FIG. 3.66), which sets the switching element 7 to the Z-state (Fig. 2.76; Fig. 3.76), the level of which goes to the first input of the adder 9 module two. At the second input of the adder 9 modulo two, there is also a Z-state, and therefore the output of the adder 9 modulo two is at zero (Fig. 2.96; Fig. 3.96).

The modulo two output signal of the adder 9 is inverted by the HE 10 element and there is a one at the inverse S input of the D flip-flop 11. The device will set the standby mode for the occurrence of the unit at information input 1.

Thus, after a short zero pulse is applied to the reset input 4 of the device, the elements 12 and 14 of the display are in the quenched state.

Then, the information input 1 of the device is connected to a controlled circuit of a digital unit, to the input contacts of which input inputs are applied, which can be generated, for example, by an external test actions generator.

In the process of control two situations are possible:

- the controlled point is in the state log, O (Fig. 2.1 c; Fig. 3.1 c), which will go to the second input of the adder 9 modulo two, then the potential difference across the terminals of the resistor 8 is:

ALP

R

in

where 1 in is the current flowing from the first input of the adder 9 modulo two to the controlled circuit (for a TTL 1.6 mA).

R is the value of the resistor 8, the calculation of which is the next;

di ° and

pore

where Unop is the minimum potential difference between the inputs of adder 9 modulo two, at which its output is in a logical unit (for TTL Unop. 2.0 V), therefore, in the device for controlling digital blocks there are no changes in the states of logical levels will not happen (Fig. 2c; Fig. Sv);

- the controlled point is in the state of log.1, or the level of log.1 by wils at some time step of control (fig.2.1 g, fig, 3.1 g), then at the output of threshold element 2 there will be a change from log to zero, 0 to the log, 1 (fig, 2.2g, fig, 3.2g), the differential from zero to one will go to the C input of the D flip-flop 3 and transfer its inverse output from zero to one, with the subsequent parapads from log.0 to log, 1, arriving at the C-input of the D-flip-flop 3. will not cause changes in the state of its outputs and thus ensures a single operation of the device from the first high logic level in the controlled circuit.

Drop from log. About log, 1 from the inverse output of the D-flip-flop 3 (FIG, 2.3 g, FIG. 3.3 g) will go to the first input of the element I 13 and to the input of the one-shot 5, which will generate a single pulse with a duration of 1imp FIG, 2.5 g; FIG. 3.5 g) At the output of the element 6, the IS-NOT is assigned a zero (Fig. 2.6 g; Fig. 3.6 g), which will transfer the output of the switching element 7 to the zero state (Fig. 2.7 g; Fig.

5 3.7 g).

Then, depending on the number of sources of a logical signal in a circuit, two situations are possible.

In the monitored circuit there is one source of the logical signal. Since the lower transistor of the output stage of the switching element 7 is in saturation, the potential at the output of the switching element 7 weakly depends on the amount of current flowing into it. Therefore, we can assume that the first pin of the resistor 8 and the first input of the adder 9 modulo two are connected to the source log. O. Then, at the input of the indicated elements, the potential difference is

Ai 1n.

R,

Max

where 1n max is the rated maximum current through resistor 8 in the absence of a short circuit between circuits (for TTL 1n max 35 mA cm), and

AI and

since then

which is not enough to change the logic level at the output of the adder 9 modulo two (Fig. 2.9) and, therefore, the levels of the logic signals at the outputs of the D-flip-flop remain unchanged (Fig. 2.11 g).

Then the test time of the circuit is determined by the duration of a single pulse Timp., Produced by a single vibrator 5 (Fig. 2.5 g). The appearance of the log. About at the second input of the element, AND-NOT 6 will cause the appearance at its output of log.1 (Fig. 2.6 g), which will lead to the switching of the output of the switching element 7 to the third state (Fig. 2.7 g) and the completion of the circuit control process.

Thus, in the absence of a short circuit in the circuit, the device will respond as follows: the display element 12 is turned off, and the display element 14 is turned on.

More than one signal source is present in the monitored circuit. When reaching the current flowing through the resistor 8, the value:

(since Unop / R,

where R is the value of resistor 8, which must satisfy the condition:

Unop / lnop R ipor / 1n.max. Inop - 2 1n.max

the logical level at the output of the adder 9 modulo two changes from zero to one (Fig. 3.9 g). This will lead to the appearance of a drop from one to zero at the output of the NOT 10 element, which will set the direct output of the D-flip-flop 11 to the unit (Fig. 3.11 d) v will turn on the indication element 12.

At the inverse output of the 0-flip-flop 11 in Wits log. Oh, which will go to the first input of the element AND-NOT 6 and to the second entry of the element I 13, therefore, at its output, it is zero. At the output of the element INE 6, the Wits difference from zero to one

(Fig. 3.6 g) and the switching element 7 will enter the third state with a high impedance output (Fig. 3.7 g). This completes the process of checking the presence of a short circuit in the monitored circuit before the end

pulse generated by a single vibrator 5.

Thus, if there is a short circuit in the circuit, the device will respond as follows: display element 12

on, and display element 14 is off. After the end of the circuit test, the device will go into the control results display mode (Fig. 2 d: Fig. 3 d) and the process of submitting test actions can be stopped. To perform subsequent checks, it is necessary to send a signal in the form of a short zero pulse to the reset input 4 of the device, connect the information input 1 of the device to the monitored

circuit, start the supply of test effects on the input contacts of the digital unit, if the process of supplying the input effects was stopped.

The effect of a device on a controlled circuit is similar to the mode of induction of a logical zero on the output of an integral element in the state of a logical unit. The duration of zero pointing to the output of the IC is: Nimp., In the case

the absence of a short circuit between the circuits (Fig. 2.1 g) and te.n. in the event of a short circuit between the circuits of the monitored digital block (Fig. 3.1 g). It is known that such a mode is integral

the transistor can withstand no more than 1 s and, therefore, the effect of the device on the output of the IC is valid.

Claims (1)

Claims An apparatus for monitoring digital blocks comprising a switching element, a resistor, a modulo two, a NOT element, and a first D-flip-flop, the output of the switching element being connected to the first input of a modulo-two and through a resistor with a second input of a modulo-adder two, the output of which is NOT connected to the inverse input of the installation of the first D-flip-flop through the element, the D-input of which is connected to the zero potential bus the device, the inverse reset input of the first D-flip-flop is connected to the reset input of the device, characterized in that, in order to expand the functionality, the device further comprises a threshold element, a second D-flip-flop, a one-shot, the NAND element and the AND element, with the information input the threshold element is connected to the first output of the resistor and to the second input of the modulo two adder and is the information input of the device, the output of the threshold element is connected to the synchronization input of the second D-flip-flop, the D-input of which is It is connected to the zero potential bus of the device, the inverse reset input of the second D-flip-flop is connected to the unit potential potential bus, the inverse input of the second D-flip-flop is combined with the inverse reset input of the first D-flip-flop and is the reset input of the device, the inverse output of the second D-flip-flop connected to the first input of the AND element and through the one-shot with the second input of the NAND element, the synchronization input of the first D-flip-flop is connected to the zero potential bus of the device, the direct output of the first D-flip-flop is connected to the first output of the device, the inverse output of the first D-flip-flop is connected to the first input of the NAND element and to the second input of the AND element, the output of which is connected to the second output of the device, and the output of the NAND element to the control input of the switching element The information input of which is connected to the zero potential bus of the device. Fi & .1 FIG. 2 1)