SU1248061A1 - Device for checking pulse counters - Google Patents

Abstract

The invention relates to instrumentation engineering devices and can be used for monitoring pulse counters in their mass production. The purpose of the invention is to increase the reliability of the control results - it is achieved by providing / 5 ON-NIN the completeness of monitoring and diagnosing the nature of faults. The device contains a control unit 1, a generator of 2 pulses, a conversion unit 4, a contact unit 5 for connecting a test counter, a comparison unit 9, a delay element 13, a fault recorder 14, an input bus 5 and an output 16, to achieve the set value the device is additionally introduced by switch 3, blocks 6 and 7 of the transfer of signals and transfer signals, respectively, multiplexer .8, blocks iO, 11 and 12 comparisons. This provides information on any malfunctions, increases the reliability of the control and creates prerequisites for changing the technological process of making counts of pulses in the event of detection of technological failures, II Il, S S (L ISD 4 00 o O5

Description

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The invention of measurement instrumentation and instrumentation for controlling pulse counters during their mass life span. One of the main requirements for devices of this purpose is to ensure high accuracy of the tested meters, performance, the control of the reliability of the results, as well as the possibility of carrying out the causes of the failures of a technical nature, which is the place in the mass production of the counting signals,

The aim of the invention is to improve the reliability of monitoring results by ensuring the completeness of monitoring and diagnosing the nature of malfunctions.

This goal is achieved by introducing new construc- tive features, which do not only provide more complete control of the efficiency of the counters by taking into account a number of faults 5 that were not previously used, but also give information about the nature of any faults, i.e. establish the type of malfunction, which, in turn, 5 makes the control reliable and creates prerequisites for changing the technological process of manufacturing pulse counters in the event of detection of technological failures,

FIG. 2 shows a block diagram of the proposed device, d, n control of impulse counters, ria FIG. 2 - 10 - try: execute individual units and blocks; on Fig temporary diantagram device.

Device control (Zlok 1 control, impulse generator 2, switch 3, conversion block 4, contact block 5 to turn on the test counter, blocks 6 and 7, 11 of the signals Transfer: Borrow, respectively, multiplexer 8. blocks 9 1 2 comparisons; elements: 13 delay 13, reject recorder 14, input bus 15 and output pin 1 i 6

FIG. 1 first input of the I; rn-coy, p, inn with BXOJ; I; HOE bus 15 second input of the 1-control unit is connected to the output of the reject recorder 14 and the output bus 16 first output of control unit 1 is connected to the generator 2 input pulse, the output of which is connected to the input of block 4

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conversions, inputs, dy, unit 9 comparing soy, are dinene to the group of first outputs of contact block 5, the output of delay element 13 is connected to the first input of reject recorder 14, the first inputs of block 6 of the transfer signal transfer and block 10 of comparison are connected to the second output of contact block 5, the second inputs of block 6 are more vividly; the signal of Transfer; the comparison unit 10, the first input of comparison unit II and the input of delay element 3 are connected to the first output of conversion unit 4, the second output of which is connected to the third input W of block

Signal extraction 6 Transfer and block 10 cpaBHeiiHH. the outputs of blocks 6 and

Selection of signals Transfer and blocks 10-12 comparisons and first, | -, output of switch 3 are connected respectively to the second, third i, fourth, fifth, sixth and seventh rejects of the registrar 14, fourth fourth input of comparator 10 5 wto ,, .. -th input of the comparison unit 1 1 and the third input of the control unit 1 are connected to the first output commutator 3, the first input of which is connected to the output of the pulse generator 2, the second input of the switch 3 is connected to the second output of the control unit 1, , the third output of which is connected to the third inlet house switch; 3, the first input of the mu; -1 plexer 8; Fifth input of the comparator unit 10 and eight meters / entrance of the reject recorder 4, the second output of the switch 3 is connected to n: The vertical contact of the contact block 5, the third output of the co-switch 3 is connected to the second; the input of the contact block 5 and the first inlet, the block of the signal extraction block 7, the second loop of which is connected to the third code of the contact block. 5 second output unit 7 zschelspi sigtt, e.p. The loan is connected to the third-party input of the multiplexer 8. trp: input, which is co-0

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connected to the output of the comparison unit S, the output of a muffler 8 connects to the third inputs of the signal extraction unit 7 Loan, unit I, the comparison and the first input of the comparison unit 12, the second input of which is connected to the third output of the unit 4 conversions.

The control unit 1 serves to coordinate the operation of the units and units of the device, which is controlled by a pulse counter. (Functional block diagram of the control unit 1 control. Tech on

Fig, 2). The control unit 1 consists of the start node t7, the Forming signal 18 of the Prohibition signal and the switch control node 19 3. The start node 17 is complete on the serially connected logical element HE, RS trigger, two delay elements (one-oscillators) and logic elements AND, AND-NOT ; Shaper signal generator 18 consists of a delay element (one-shot) of a two-input logical element OR, a Restriction element (mounting AND-NO), two RS-flip-flops and a three-input logic element AND; The control node 19 of the switch consists of an NAND gate and an RS flip-flop,

The pulse generator 2 is designed to generate a series (pack) of rectangular pulses and is implemented on the basis of a waiting multivibrator with a quartz frequency stabilization.

The switch 3 serves to transmit a series of square pulses from the generator 2 outputs to the forward and reverse counts of the checked pulse counter placed in the contact unit 5, and the switching of the pulses is effected by the enable signals from the control unit 1. (A functional diagram of the switch 3 is shown in FIG. 3). The switch consists of a logical element NOT and two elements NAND,

The pulse series-to-square pulse conversion unit 4 is used to generate reference information for the monitored counter (logical O (O), logical 1 (I) signals and pulse for controlling the Transfer signal) by converting the control information (specified counting code) to a time interval of one impulse (Functional diagram of the conversion unit 4 is shown in FIG. 4). The conversion unit 4 consists of a register, a reversible counter, a D-flip-flop and logic elements AND, AND-NOT.

The contact unit 5 for switching on the checked pulse counters is a relay switching matrix, which provides the connection of the outputs of the checked counter to the corresponding nodes of the device.

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The elements of block 5 are used reed switches, block 6 of signal extraction Transfer is intended to determine the presence of a signal Transfer, characterizing the operability of the counter being tested in the direct counting mode. Block 6 consists of input and output logic elements NOT, elements -SHI, And and RS-flip-flop (see, figure 5),

The signal extraction block 7 Borrow is used to determine the presence of a Borrow signal, which characterizes the counter in the countdown mode and generates a resolution signal for multiplexer 8 to pass signals from the comparison block 9 to the I1, 12 comparison blocks through it,

Fig, 6 shows a functional block diagram 7, Block 7 consists of the input logic element AND, the element OR, and the output RS-flip-flop,

Fig, 7 shows the scheme of the multiplexer 8. The multiplexer, 8 consists of two logical elements AND-NOT.

Comparison unit 9 serves to compare signals installed at the bit outputs of the counter being tested, and is performed on a multi-input (by the number of counter bits) OR element

Comparison unit 10 serves to compare signals coming from the counter to be tested (from the output of contact block 5) and block 4 of converting a series of pulses into a direct impulse, and generating a signal to the reject recorder 14 that carries information about the type of reject. The comparison unit 10 consists of three NAND elements and an EXCLUSIVE OR element (see FIG. 8),

Comparison unit 1 is designed to compare the signal arriving through multiplexer 8 from the output of comparing unit 9 with the signal arriving

from the output of block 4 converting a series and 5 pulses into a rectangular pulse, and issuing to the recorder 14 of the signal a signal carrying information about the presence of a marriage. Block II Comparison 5 is implemented on the elements EXCLUSIVE OR, NOT and NAND (see FIG. 9)

Comparison unit 12 is used for comparative analysis of signals inputted from its inputs from the pulse train-to-square pulse unit 4 and from the comparison block 9 (through multiplexer s), and forming, according to the results of the analysis of the signal carrying fault information, counting. Comparison unit 12 is implemented on a logical element.

The delay element 13 serves to generate for the reject recorder 14 a signal delayed relative to the trailing edge of a rectangular pulse generated from a series of pulses by the conversion unit 4. Element 13 of the delay is complete on one-shot.

The reject recorder U is designed to record the presence of a reject and indicate the type of malfunction, (Reject recorder 14 is shown in Fig. 10 / Reject recorder 14 contains an AND-NOT element, a rejection signal generating unit, which is fulfilled on the D and RS triggers, the node indicator on the indicator lamps, LEDs, and the multi-input element I, which is connected to the output of the recorder 4. Rejects. The number of flip-flops in the node f-orming the rejection signal, the display elements and the inputs of the element K is determined by the number of types of faults and in this case in addition, the indicator is equal to, and the low speed of the checked counter is indicated by means of an indicator lamp, the indication of the absence of the signals Transfer and Loan - by lamps 14-2514-3, respectively, the indication of failure - by lamp 14-4 indication of untimely occurrence of the signal Transfer - by lamp 14-5 ,

The device works in a manner that

In the initial state in the register of block 4, the conversion of a series of pulses into a rectangular pulse is recorded information about the number of pulses that must be fed to a controlled counter (recording information to the register in the simplest form is carried out by means of mechanical switches, not shown in Fig. 4). . At the output of the element IS-NOT of the launch unit 17 included in control unit 1, the level is set to 1 (see fig, 1 1 J ,, time to time). Discharge by power)

(FIG. 2, not shown) on the direct outputs of the RS-flip-flops of the Forbidden signal generator 18, set O, the direct output of the RS-flip-flop of the switch control circuit 19 is O, and the inverse is 1 (FIG. 11 b and I, respectively ), One-vibrators of the launch unit 17 and the signal generator 18 of the Prohibition are in a single state (FIG. E, "respectively). At the output of the reversible counter of the conversion unit 4, (11 and) are installed at the forward output of the D-trigger: Oh, and on inv.ernom - 1 fig. P k, l respectively) L1a output inverter of block 6 signal extraction Transfer is set O (fig.Pm), on the direct output of the RS flip-flop of block 7 signal extraction Loan - O, and on the inverse I - (Fig. 1 (L, o respectively.) At the outputs of the blocks 10 and P of the comparison, the delay element 13 and the reject recorder 14 are installed (FIG. P i, p. c, m respectively),

Controlling the -1YM counter, ayut in the contact block 5, the Operator presses the Start button connected through the input 15 to the control unit (the Start button is not shown), At the same time, the S-input of the RS-trigger of the node 17 A trigger pulse (see fig, 1 1, time t) J which puts the trigger into a single state, the signal from the R output of the trigger triggers a single vibrator of the node 17 of FIG. 5 which) -; b, it operates a reset pulse for the triggers of the Forming signal 18 of the Inhibitor, switch control node 19, block 6 Signal Transfer, block 7 of the signal allocation of the Loan and the registrar 14 of the marriage, preparing those blocks listed above to work. The duration of the reset pulse is determined by the switching time of the elements of the contact block 6 and is in the order of 3 ms. But when the reset pulse arrives at the S inputs of the triggers of the former 18, they are set to one, resulting in the output of the three-input logic element And also installedP1 which prepares the NAND gate of launch node 17. At the end of the reset pulse at the output

element H-} 1E, a pulse is generated by the generator 2 start (Fig. 1 fT, time tj), during which a train of pulses is formed (Fig. 11 y) fed to the inverter of the switch 3 and to the first inputs of the NAND elements, And and D-flip-flop block 4 conversion. The passage through the inverter and one of the I-NB elements of the switch 3, the pulses through the contact block 5 arrive at the input of the direct account of the monitored counter. In the conversion unit 4, the reference information for the monitored counter is formed by converting a series of pulses into a rectangular pulse, the duration of which is determined number written in block 4 register.

Information from the outputs of the monitored counter bits arrives at the inputs of comparator unit 9, and a single pulse is formed at the output of the latter, the duration of which is determined from the time of appearance of the pulse at the lower level of the controlled counter to the moment of the end of the pulse at its highest discharge (FIG. 119 ) - A single impulse from the output of the comparison block 9 is fed to the combined in-turns of the AND-NOT multiplexer 8 logic elements, on. the output of which impulse O appears (Fig. II) at the resolution signals j. arriving at the second inputs of the AND-NOT elements from the RS-flip-flops of the control unit 9 to the switchboard of the control unit 1 and the signal allocation block 7 of the Loan. In this example, the resolution signal () for the passage of pulses from the comparison block 9 through multiplexer 8 comes from the control block (Fig. 11). At the falling edge of this pulse at time tj, the RS-flip-flop of block 7 is reset through the logic element of this block. This same pulse, which is the real information of the controlled counter, goes to the inputs of blocks II, 12 comparisons, in which the comparison takes place real information from the reference, formed by the unit 4 converting a series of pulses into a rectangular impulse. As a result of comparing the durations of the impulses, the meter is checked for operability (the possibility of bitwise counting),

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If the duration of the comparable pulses is equal, the monitored counter is considered to be godt-gm.

If the duration of the real J-IM pulse is less than the duration of the reference pulse, then at the output of the AND-NOT element of the comparison unit 1 a signal is generated. An O dial (Fig. 1-1), according to which the RS-trigger of the defect recorder 14 is set to the zero state on the inverse output, as a result of which the indicator light comes on, indicating a fault due to the failure of the controlled counter (during counting the pulses, one of the bits of the counter, having been set to 1, remains in one state, the output pulses (the pulses arriving at its input) remain. Logical zero from the fault registrar 14 (Fig.Pt) through the AND element of the Interlock signal bar 18 and the IS-NOT of the start node 17 stops the pulse generator 2 and resets the RS trigger of the start node 17.

If the duration of the real pulse exceeds the duration of the reference, then at the output of the comparison unit 12 a signal 1 is generated, which with a delay defined by element 13 is written to the D-trigger of the reject recorder 4, resulting in an indicator 5 light 14 decrease byst0

of the counter, caused by clones of its parameters, with the possibility of effective ambient temperature, supply voltage, etc.

Upon the arrival of the last pulse with

Generator 2 to a controlled counter (FIG.), it generates a signal Transfer s which from the output of the contact block 5 (figure 11c) is fed to the first inputs of blocks 6, 10 (through the IPI element to the RS trigger of the signal extraction unit 6 and EXCLUSIVE OR block 10 comparison), The other integrated inputs of these blocks receive reference information from the conversion unit 4 from the output of the reversible counter of block 4, the signal O arrives at the OR element of block 6 and at the input

The IS-NOT element of block 10 compared with the direct output of the D-flip-flop of block 4 (signal 1 is fed to the input inverter of block 6 and to the combined inputs of the elements of IS-NOT block 10 of the squirrel). But the leading edge of the reference pulse arriving at the input inverter of the signal extracting unit 6 Transferring 5 sets the RS-- trigger | 5a to one state. At the simultaneous input of the number of blocks 4 and 5 to the inputs of the OR element of block 6, the RS TpHrre is reset It returns to the initial zero state, in which the indicator lamp 14-2 does not light up, which indicates the validity of the meter. In the absence of a signal from the monitored counter to the RS flip-flop of block 6, it remains in one state. The signal from the output of block 6 is transmitted to a D-trigger with a delay of element 13 and is recorded.

indicator lamp 14fixed no signal Transfer caused by internal breaks of conductors in the circuit of the controlled counter,

In block 10, the comparison of the residual ets-SI is the comparison of the durations of the real and reference pulses. Coming from the contact block 5 k from the block 4 converting a series of pulses into a rectangular pulse. If the durations are equal at the output element, the NAND is set to 1, the RS-trigger status of the fault recorder 14 does not change, which indicates the validity of the counter, In the event of a marriage; due to the premature signal occurrence of the Transfer, caused by internal communication breaks in the output matching circuit, the controlled counter, a change occurs in the RS-TpHrrepa registration status of the reject tracer 14, the control lamp lights up and the monitoring process stops,

Signal extraction The loan is carried out by applying a series of pulses to the input of the counting counter of the monitored counter when the generator of 2 pulses starts up. This is accomplished as follows. Upon termination of a series of pulses, suppressed at the input of the direct account of the monitored counter, the one-vibrator of the suppression signal generator 18 (FIG. 11, time t) transfers the RS trigger of the switch control node 19 to one state. (Fig.Pg), by Which time through the time determined by the delay of the one-vibrator of the node 17 start Sfig.11e, the moment

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time tf), the following is performed: second start of the generator of the pulse 2 (FIG. PU) and preparation of the components of the IS-NOT switch 3 for passing a series of pulses to the input of the counting counter of the controlled counter, G e the generator of 2 pulses produces a series of pulses S which is transmitted in 1 way to block 4 of pre formation and through commissator 3 to the input of the counting counter account e-1-south of the counter and to the input of the element OR of the signal extraction block 7 Loan / The other input of this element t of the controlled counter receives a signal Loan (), In the case of As soon as the inputs of the element OR of the zero levels, the QW-trigger of the 7n unit state unit is installed (Fig. PSo-S from the open OUT) and the RS-trigger the zero level signal is fed to the input of the AND-NOT element of the reject recorder 14, Since The two other inputs of the NAND element are set to 1 (via signals from control unit 1 and switch 3) J then the output status of the NAND element and the corresponding RS RS of the goder do not change and the indicator light 14-3 does not light up s which indicates the presence of a loan signal, a single level signal with direct output of the RS flip-flop of block 7 permits the passage of pulses from block 9 of comparison to blocks 11, 12 of the comparison jies element of multiplexer 8. When this happens, the counting of the counter in the counting mode is also j this direct account (see above)

In the absence of a signal, the RS-flip-flop of block 7 does not change its state, as a result of which the RS-flip-flop of the defect recorder 14 is set to the zero state on the inverse output, the indicator lamp 14-3 lights up. from the generator 2 in the mode of reverse counting the one-vibrator of the signal generator 18 The prohibition forms a pulse (FIG. 1 H, time tg), which through the Prohibition element establishes the corresponding trigger of the RS-flip-flop to the initial state, in which the element And the inverter node 17 run occurs the RS-TpHj-rep cast and the initial state, and;) the output of the AND-NOT element is set to 1 (Fig. 1 15} The monitoring process is over. Thus, the meter is monitored in the forward and reverse counting modes. The proposed device allows not only to fix the defect, but also to carry out diagnostics, which is especially important when using the device to control the counters in the process of their mass production.In case of persistent technological failures, it is possible to analyze the causes of failures and, if necessary, issue and recommendations to change the meter technology.

Claims (1)

Invention Formula A device for monitoring pulse counters containing a control unit, a pulse generator, a contact unit for switching on a test counter, a conversion unit 5, a first comparison unit, a fault recorder, a rear element, an input and output terminals, the first input of the control unit connected to the input bus, the second the input of the control unit is connected to the output of the defect recorder and the output bus; the first output of the control unit is connected to the input of the pulse generator, the output of which is central to the input of the conversion unit, the inputs of the first the comparison unit is connected to the group of the first outputs of the contact block, and the output of the delay element is connected to the first input of the defect recorder, characterized in that, in order to increase the reliability of the control results by ensuring complete monitoring and diagnostics of the nature of malfunctions, the units for signal allocation Loan, Transfer, second , third, fourth comparison units, a switch and a multiplexer, with the first inputs of the signal extraction unit Transferring to the second unit compared with the second output of the contact unit , the second inputs of the signal transfer unit Transfer, the second comparison unit, the first input of the third comparison unit and the input of the delay element are connected to the first output of the conversion unit, the second output of which is connected to the third 10 inputs of the block, signal extraction Transfer and the second comparison unit, outputs the units for selecting the Borrow and Carry signals, the second, third and fourth comparison blocks and the first 15 output of the switch are connected to the second, third, fourth, fifth, sixth and seventh inputs of the fault recorder, quarters, respectively the input of the second comparator unit, the second input 20 of the third comparator unit and the third input of the control unit are connected to the first output of the switch, the first input of which is connected to the output of the Pulse generator, the second input of the switch 5 of the mutator is connected to the second output of the control unit, the third output of which is connected to the third the switch input, the first multiplexer input, the second input of the second comparison unit 0 and the eighth input of the defect recorder; the second output of the switch is connected to the first input of the contact block; the third output of the switch is coi inden with the second input of the contact block 5 and the first input of the signal conditioning block, the second input - which is connected to the third output of the contact block, the second output of the signal extraction block; the loan is connected to the second input of the multiplexer, the third input of which is connected with the output of the first comparator unit, the output of the multiplexer is connected to the third inputs of the Border signal extraction unit, the third comparator unit and the first input of the fourth comparison unit, the second input of which is connected to the third output of the conversion unit. To UNI meoS Generation2 TtucmaB Torach SpaKS K aOWff, 6,10, sjMfjymcffS --- s- KSmKOM 5, 7  1 A L OnmGffmHO p  di on y 5 j Cffmnf f уfwa Olenin 9ijf.S Sedoka 5 Shtach CSpoc Kie Si / cm rotor j 5 rak FIG. five CSmm 1 / Rules /  srd / S5lok 7 Fiyo.7 Ь „1--1 TLzi ™„ 7 With J managements K5lokan , nj2 „1--1 TLzi 7  l  Domopai SpOffO 3i / sJ From switch j S5loka  onn gpstow 3 NZ Kpesi / cmffOmo- pyf §rack Fi.d CoMkfffl CpaSHewl  S s ifHmojJ CBffQffOS C switchgear S c7 / Cha7 L. .It. - "a- ™ SflOKQ CfflO -fffi c / oaSf / em Cff / fme fO Ki / myf  board, to memenK - ™ {nnm sh ...,   ™ 1G - Sh Editor M. Bandura  I Chkaz 4141/58 Circulation 816 Subscription VNIIPI GosudarsnenoG About 1 USSR Committee on matters of inventions and discoveries G 1303 5 5 Moscow; c F - 35, Raup; ska pab. d. 4/3 Production and printing office, Uzhgorod, ul GGroyEstna, 4 TG. //