SU1234840A1 - Device for continuous diagnostic checking of uniform logic units - Google Patents

Abstract

This invention relates to the field of technical diagnostics. The purpose of the invention is to increase speed by eliminating the dependence of the diagnosis time of each k -th block (...., ii, n is the total number of diagnosed blocks). Each block is assigned a counter, which stops in the event of a fault, which is fixed by the comparison circuit. From each of the m equalization schemes (.fn is the number of times the kth block), the signal from the same outputs of the diagnosed blocks is received. When a failure is detected, the clocking generator and test generator are automatically stopped. The operator replaces the faulty unit with another diagnosed unit and starts the device. Since the i test generator operates on a ring cycle, and logical blocks are combination type circuits, there is no need to make diagnostics from the initial test. 1 il. SL

Description

This invention relates to the technical diagnostics of logic blocks.

The purpose of the invention is to increase the speed by eliminating the time dependence of diagnosing each k -th diagnosed block from each other (k 1,,.., Ti 5 where k is the number of logical blocks being diagnosed).,

The drawing shows a diagram of the device. one ...

The device contains and monitored logic blocks 1 ... 1 ", a generator of 2 tests, a generator of 3 clock pulses, W circuits 4 ... 4 comparisons, switch 5, block 6 of the display, and switches 7, ... element OR 8, n counters 9 ... 9 „.

The device works as follows.

All 1 counters 9 ... 9 are reset, dl. of which all the switches 7 ... 7p are set to the position at which the negative potential is applied to the installation inputs n of the counters 9 (... 9 and the resolution input m of the 4 J ... 4 "comparison circuit. Then all the h switches are set to at which the positive potential is fed to the resolution inputs m of the comparison circuits 4 ... 4 and the reset inputs and counters 9, .., 9 ,. After this, the generator of 3 taut pulses is started. The clock pulse generator begins to calculate the clock signals frequencies that go to generator 2t ists and n counters 9,.. ..9. 2 test generator outputs the test exposure to the inputs diagnosed logic blocks in case of serviceability of all the blocks 1,... 1 (signals at identical uk

If at some kth output of any of the diagnosed logic inputs, a signal appears on the Jth cycle that does not match the signals of the 1st outputs of the rest, (n-1) logical blocks 1. that works out p-from m comparison schemes 4 ...- D. The output signal of the k -s comparison circuit via the element OR 8 stops the generator of the 0 torus of 3 clock pulses, stopping the clocking of the device. Wherein . counters 9, ... 9), record the number of the cycle on which the mismatch of the output signals of the diagnostics module of blocks 1 ... 1 „was recorded, and the display unit 6 indicates the code of the test signal of the test generator 2. Since the circuit of the entire device is fixed when the output signals and blocks 1 ... 1 are not falling, the logical signals are stored at their outputs. . (O or 1), characterizing the state of each of the n blocks 1. .. one ,. These signals are presented to the operator.

 .videopt-dimensional binary codes of the display unit 6. Compare these codes,. displayed, for example, by means of LEDs, bitwise one below the other, the operator sets the code,

30 CZ therefore, the number of the diagnosed unit, which is different from the others. In this case, the process of isolating a faulty block can be based either on the use of a reference block or on the majority principle. Having thus determined the faulty j block 1, and by the code of the test signal and the type of defect, the operator disconnects it with the help of the j switch 40 bodies 7 J. Switching the j-th switch provides a negative potential to the installation input of the J-th counter 9j, as a result of which the j-th account is reset. tl ...

50 outputs must match each other, 5 points 9. In addition, j is switch

7j rebuilds all

comparison circuits from p-input to (rt-1) are input circuits, which is necessary if the device continues to operate without J-th block 1, or when diagnosing a group of logic switches less than h. After that, the operator starts the generator 3 clock pulses J and the diagnosis of the remaining 55 n −1 logic blocks continues. In parallel, the operator retrieves the logical block in which the defect is detected and in its place establishes what they are fed through switch 5 to m comparison circuits 4, ... which do not pick up pulses at their outputs. In this case, the 3-clock pulse generator is stopped through the OR element 8 or by overflow signals from counters 9, ... 9p. In this case, the display unit 6 fixes the maximum number of operating frequency cycles generated by the 3 clock pulse generator and registered by the counters 9, ... 9. This number corresponds to the length of the test.

If at some kth output of any of the diagnosed logic inputs on the Jth cycle there appears a signal signal that does not coincide with the signals of the 1st output of the others, (n-1) logic blocks 1. „. 1, then . works out p-from m comparison schemes 4 ...- D. The output signal of the k -s comparison circuit via the element OR 8 stops the generator of 3 clock pulses, stopping the clocking of the device. Wherein . counters 9, ... 9), record the number of the cycle on which the mismatch of the output signals of diagnostics of blocks 1 ... 1 „is recorded, and the display unit 6 indicates the code of the test signal of the test generator 2. Since the circuit of the entire device is fixed when the output signals and the 1 ... 1 blocks do not fall, the logical signals are saved at their outputs. (O or 1), characterizing the state of each of the n blocks 1. .. one ,. These signals are presented to the operator.

.videopt-dimensional binary codes of the display unit 6. Compare these codes,. displayed, for example, by means of LEDs, bitwise one below the other, the operator sets the code,

TsZ therefore, the number of the diagnosed block, which is different from the others. In this case, the process of isolating a faulty block can be based either on the use of a reference block or on the majority principle. Having thus determined the faulty j block 1, and by the test signal code and the type of defect, the operator turns it off using the j switch 7 J. Switching the j-th switch provides a negative potential to the installation input of the J-th counter 9j, as a result of which the j-th account is reset. tl ...

Chika 9. In addition, j is the switch

cast another block. The connection of this unit is made by switching the 7th switch 7; to the position when the positive potential is fed to the corresponding inputs of the control circuits A ... 4 comparisons and the installation input j - g counter 9 :. As a result, j-and counter 9; It starts counting clock pulses from the moment of clocking this new block, and the comparison of output signals already partially diagnosed blocks and re-enabled does not disrupt the process as a whole, since the logical blocks 1, ... are of the combinational type.

An overflow of the j-th one or several counters 9 .. ..9 indicates that the corresponding logic block has passed the entire test .. In this case, the signal from the output of the j-th counter 9j / j through the OR 8 element stops; the generator generates 3 clock pulses , and the display unit 6 indicates the number of cycles (maximum) equal to the length of the test. The disconnection of this logical block and the production of another is performed in the same way as when a defect is detected in one of the logical blocks 1 | ... If,. - The generator of 2 tests at the same time functions on a ring. Since logical blocks 1, ... 1 "are combinational-type circuits, it does not matter from which test signal the testing process begins. It is important that for each block 1, .. 1 "the test is complete, i.e. all ring

Claims (1)

Formula image shadow Device for continuous diag the layout of logical blocks of the same type, containing a test generator, a switch, m comparison circuits (where m is the number of outputs of the diagnosed logical block), h switches (where and is the number of diagnosed logical blocks) and the display unit. 5 yu 15 20 5 Q 0 five the outputs of the test generator are connected to the information inputs of the diagnosed logical blocks, the i-th outputs of each of which (1, .., P) are connected through the switch with the corresponding information with the inputs of the i -th comparison circuit and with the corresponding information input of the first group of inputs of the display unit, the resolution inputs rti of the comparison circuits are connected to the moving contacts W: the switches, the first and second fixed contacts of which are connected to the buses of the zero and unit potentials of the device, respectively This is because, in order to improve speed by eliminating the time dependence of diagnosing each jth diagnosed logic block (j1 ... ..., fi) from each other, it contains a clock generator, the IL element , H counters, the input devices connected to the trigger input of input gene- - p Ator clock whose output is connected to the input of sync. test generator and counting inputs of the corresponding AND meters, the reset outputs of which are connected to the moving contacts of the corresponding switches, group outputs of the comparison circuits are connected to the first group of inputs of the OR element and the second group of information inputs of the display unit, the group of bit outputs h of the meters are connected to the third group information inputs of the display unit, a group of outputs overflow n counters connected to the second group of inputs of the element SH and the fourth group of information inputs of the block ind katsii, vkod OR gate coupled to the entrance lock clock generator, the test generator outputs are connected to the fifth group of information inputs of the indication unit. Compiled by A. Sirotska Editor E, Kopcha Tekhred M. Hodandat Corrector E, Roshko Order 2986/51 Circulation 6/1 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 rg1I31i. polygraphic enterprise, Uzhgorod, st. Project, 4 Subscription