SU1322289A1 - Device for checking integrated circuits - Google Patents

Abstract

The invention relates to automation and computing and can be used to control the parameters of digital integrated circuits. The purpose of the invention is to improve the control speed. This is achieved through quality control (LFie1

Description

electrical contact between the terminals of the tested microcircuit and the block of transitional contacts directly in the process of conducting the test and building the device on the TTL chip of logic. When the type of expected signals coincides with real signals, the device generates a sign characterizing the presence of contact between the terminals, the chip being tested and the control device, if these signals do not match, information is displayed

The invention relates to automation and computing and can be used to control the parameters of integrated circuits.

The purpose of the invention is to improve speed.

Figure 1 shows the functional diagram of the device for control of the chip; Fig. 2 is a block diagram of the comparison; FIG. 3 is a diagram of the control unit in FIG. 4 is a switch diagram; FIG. 3 is a diagram of the start block; Fig. 6 is a diagram of a first contact monitoring register; Fig. 7 is a diagram of the first contact monitoring unit; FIG. 3 is a diagram of a second contact monitoring unit; FIG. Fig. 9 is a diagram of a second contact control register.

The device (Fig. 1) contains a controlled chip 1, a register of 2 actions, a first information input 3 of the control unit, a control unit 4, a second information output 5 of the control unit, a register 6 of reference reactions, a comparison unit 7, outputs 8 of the reference reaction register, output 9 the comparison unit, the output 10 of the control unit stop, the start unit 11, the input 12 of the initial installation of the device, the block 13 of transition contacts, the first group of contacts 14 of the block of transition contacts, the inputs 13 of synchronization, the bits of the first contact control register, he first control register 16 contacting the third resistor 16.1, second information input 17 of the first block

matsi about the reason for the stop. The device for controlling microcircuits contains two contact monitoring registers 16 and 22, two contact monitoring units 18 and 20, comparison unit 7, switch 27, effect registers 2 and reference reactions 6, control unit A, two terminating resistors 16.1 and 22. 1, unit start II, containing a start trigger, an OR-NOT element and a terminating resistor. 3 hp f-ly, 9 ill.

O

five

contact control, first contact control block 18, second information input 19 of the second contact control block, second contact control block 5 20, second installation input 21 of the second contact control register, second contact control register 22, second matching resistor 22.1, information output 23 of the device, the second group of contacts 24 of the block of transitional contacts, the second group 23 of information inputs of the comparison unit, the output 26 of the synchronization of the control unit, the switch 27, the control input 28 switches, switch output 29, start input 30 of the control unit, device start input 31.

Comparison unit 7 (Fig. 2) contains a group of half-adders 32 and an element FIP-HE 33.

The control unit 4 (Fig. 3) contains a counter 34, a pulse generator 33, the inverter 36, a memory element 37 (ROM).

The switch 27 (figure 4) contains the first 38 and second 39 elements AND-NOT.

The start block 11 (FIG. 3) contains the OR-fft 40 element, the start trigger 41, the first matching resistor 41.1.

The first contact control register 16 (FIG. 6) contains a group of triggers 42.

The first contact control unit 18 (Fig. 7) contains a group of 5 parameters 43, a group of inverters 44, a group of flip-flops 43 and a terminating resistor 43. 1.

The second contact control unit 20 (Fig. 8) contains a com

parators 46, a group of triggers 47, a matching resistor 47.1 and a group of inverters 48. The second contact control register 22 (FIG. 9) contains a group of inverters 49.

The device works as follows.

The pulse signal NU is used to reset the triggers 42, 45, 47 and 49 blocks and registers 16, 18, 20 and 22 koytrol contacting and triggers of impact register 2, trigger trigger 41, counter 34 of control unit 4. The logic signal O from the output of the trigger 41 to the input of the generator 35 of the control unit 4 prohibits the formation of clock pulses. The device is started by a Start signal, which is fed via bus 31 to the second installation input of trigger 41 of start unit 11.

By this signal, the direct output of the trigger 41 is set to the logical state 1. The logical 1 signal from the direct output of the trigger 41 is fed to the input 30 of the control unit 4 and enables the generator 35 of the unit 4 to operate. The clock pulses from the generator 35 output to the counter 34 block 4 and consistently increase its content by one. At the output of the counter 34, the address of the ROM 37 of the block 4 is formed. At this address, the ROM 37 reads the stored information in it, which via bus 3 enters the inputs of the register of 2 actions, and bus 5 receives the inputs of the register 6. Through T / 2, where T - the generation period, from the output of the inverter 36 of the control unit 4, a pulse signal is received, which records information set at the outputs 3 and 5 of the ROM 37, into the influence register 2 and into the register 6.

From the outputs of register 2 effects information is fed to contacts 24.1, 24.224.g of the block 13 transition contacts, and through them to the inputs of the controlled chip 1. Reaction to input effects from the outputs of chip 1 through the contacts 24.p, ..., 24.p and 14.p, ..., 14.p of block 13 enters via bus 25 to the second inputs of block 7 of comparison. When the working (current) reaction of the tested chip 1 coincides with the reference from the output of the OR-NOT 33 block of the comparison block 7, the display element is received

0

five

0

five

5 0 5

the signal; ch (for example, log 1) of the proper operation of the transceiver chip 1. This signal arrives via bus 9 to the address address of the ROM 37 of the control unit 4, translates the operation algorithm of the control unit 4 (stored as a program in the ROM 37) on the branch with a sign of the validity of the chip 1.

During the test period (which may consist of both cycles and one cycle), the value of the signals at the outputs of the tested chip 1 may be: positive or negative pulse or pulse sequence; constant value of logical zero (Housing), constant value of logical unit, value of supply voltage

(+ ipit) Connecting the contacts of the block 13 transition contacts to the pins of the monitored chip 1 is carried out depending on the type of expected signal at the corresponding pin of the chip 1. For the pulse signals, figure 6 shows the connection diagram of the corresponding nth pin from the first group of contacts 14. For a signal that has the form of a constant value of a logical zero (or Housing), figure 9 presents a diagram of the connection of the corresponding contact from the first group of contacts 14. For a signal that has the form of a constant value logical unit, Fig. 8 shows the connection diagram of the corresponding contact (k) from the first group of contacts 14. For the signal having the value of the supply voltage, Fig. 7 shows the connection scheme of the corresponding (1) contact from the first group of contacts 14. I

The control of the presence of contact between the output of the tested microcircuit 1 and the block 13 of the transitional contacts with the expected pulse signal occurs as follows (Fig. 6). The impulse signal WELL, coming through the bus 12 to the first installation input of the trigger 42, sets the value at its direct output to the logical 01. If at least one pulse arrives at the synchronizing input of the trigger 42 during the test run, then the logical value 1 is written to the trigger 42 which characterizes

reliable electrical connection.

The control of the presence of a contact with the expected constant value of a logical zero occurs as follows (Fig. 9). The signal НУ, arriving at the first installation inputs of the triggers 49 via bus 12, sets the value of the signal at the direct outputs to the logical second inputs of the flip-flops 45 and switches the corresponding direct output to the logical state 1. In the event of non-inequality, i.e. there is no reliable electrical contact; the signal value at the output of the corresponding trigger does not change.

From the output of the ROM 37 of the unit 4, the input is O. If during the process of running the test on the bus 28 to the second input of the elet there is no contact, i.e. if the bus connected to the second installation input remains in the air, which is perceived at the input of chip 1 as logical 1, then the state of the flip-flops 49 does not occur. In the case of a reliable contact, a logical O signal arriving at the second setup input transfers the direct output of the trigger 49 to its own state, which corresponds to

logical one.

The control of the presence of a contact at the expected constant value of a logical unit occurs the following 1 changes the value of the signal at the output of the IS-HE element 39 (logical O). The value of the logical About bus 29 is fed to the input

control of the absence of contact, the value of the signal at the output of the element IS-HE 38 of the switch 27 corresponds to the logical 1, which, when the signal is in the same way (Fig. 8). The signal NU, after the second input of the element AND-NOT 39 is logic to the first installation inputs

triggers 47 via bus 12, sets the direct outputs to the state of logical O. If the first inputs

the comparators 46 receive a high on-30 sampling of the ROM 37 of the block 4, a logical 1 (2.4 V), then the logical 1 is also formed at the outputs, which is fed to the input of the inverter 48. The logical signal O from the output of the inverter 48 is fed to the second installation the trigger input 47 and directs the output to the logical 1 state. In the absence of contact, the signal value on

40

the output of the corresponding trigger 47 is unchanged.

Control of the presence of contact with the expected value of the supply voltage

,

the output of the contents of the ROM 37 to its outputs and the values of the signals on the output rams of the ROM 37 correspond to logic 1. The signal from logic 1 through bus 10 is fed to the second input of the OR-NOT 40 element of the start unit 11, the output of which generates a logical signal O, The logical signal O from the output of the element OR NOT 40, arriving at the first installation input of the trigger 41 of block 11, sets its direct output to the state of logical O, which, entering the input

(-Unvr) occurs as follows 5 generator 35 pulses of the clock hour (Fig.7). The signal НУ, which arrives at the first installation inputs of the flip-flops 45 via bus 12, sets the direct outputs to the state of logical O. If + and "" arrive at the first input of the comparators 43, then a logical signal 1 is generated at the corresponding outputs if the inequality

+ Unv, T,.

The signal of logical 1 from the outputs of the Comparators is fed to the inputs of inverters 44. The signal of logical About from the outputs of inverters 44 is fed to

Tots of the control block 4, prohibits the formation of clock pulses. Information on the display elements from the registers and the contacting blocks 16, 18, 20 and 22 of the control 50.

The reason for the shutdown.

If the signal at the output of the NAND 38 element of the switch 27 is equal to the logical O (if there is a reliable electrical connection of the pins of the microcircuit

1 and contacts of the block 13 transition contacts), then the signal of logical 1, arriving at the second input of the element

the second set inputs of the flip-flops 45 and transfers the corresponding direct output to the state of logical 1. In case of non-fulfillment of inequalities, i.e. there is no reliable electrical contact; the signal value at the output of the corresponding trigger does not change.

From the output of the ROM 37 of the block 4 for the input of the promontory AND-HEN 39 of the switch 27, a signal of logical 1 is received, in which the test of the running test monitors the reliability of the electrical connection of the terminals of the tested chip 1 with the block 13 of transition contacts. If at least one trigger from the registers and blocks 18, 20, 22 and 16 of the contact control does not change

Sky 1 changes the value of the signal at the output of the NAND 39 element (logical O). The value of the logical About bus 29 is fed to the input

manager

No sampling ROM 37 block 4

No sampling ROM 37 block 4

the output of the contents of the ROM 37 to its outputs and the values of the signals on the output rams of the ROM 37 correspond to logic 1. The signal from logic 1 through bus 10 is fed to the second input of the OR-NOT 40 element of the start unit 11, the output of which is a logical signal O, the signal logical O from the output of the element OR NOT 40, arriving at the first installation input of the trigger 41 of block 11, sets its direct output to the state of logical O, which, entering the input

The generator 35 pulses of the clock frequency of the control unit 4, prohibits the formation of pulses of the clock frequency. Information from the registers and blocks 16, 18, 20 and 22 of the contact control is displayed.

The reason for the shutdown.

If the signal at the output of the NAND 38 element of the switch 27 is equal to the logical O (if there is a reliable electrical connection of the pins of the microcircuit

1 and contacts of the block 13 transition contacts), then the signal of logical 1, arriving at the second input of the element

7

The AND-39 of switch 27 via bus 28 does not change the value of the signal at its output (i.e., the signal 29 remains on bus 29), therefore, control unit 4 continues the operation of the control test. The moment of arrival of logic 1 through bus 28 from the output of the ROM 37 of control unit 4 is determined by the period of checking the reliability of contact.

In block 7, the comparison of the values of the settings received from the register 6 of the reference reactions via bus 8 is compared with the actual values of the output signals of the tested chip 1 (in the block diagram presented in figure 1 the contacts of the first and second groups of the block 13 of transition contacts are connected, so how can we assume that the functions

reaction1P1, comparison block, trigger trigger

ten

ka, three terminating resistors, a switch and an OR-NOT element, the inverse S-input of the start trigger is connected to the device's start input, the trigger start output is connected to the control input of the control unit, the first and second information outputs of which are connected to information inputs according to the impact register and the register of reference reactions, the outputs of the register of reference reactions are connected to the first group of information inputs of the comparison unit, the output of which is the output of the device; the inverse R input trigger of the connection yield OR-IE, and the clock input of D-flip-flop through a first starting resistor connected to Rin

the first (master) contacts are assigned to the device to connect to the output of the HYe circuits of the tested chip 1, and the functions of the second (control) contacts are performed by the combined contacts of the first and second groups of the block 13 transition contacts, which pass through the bus 25 to the second inputs of block 7 The result of the comparison is sent along the line 9 to the display elements and to the second input of the ROM 37 of block 4 as a Goden or Marriage signal.

The arrival of the signal from the output of the comparison unit 7 determines the operation of the operation algorithm of the control unit 4 stored in the ROM 37 in the form of a testing program for the chip 1.

In the case of the tested chip 1 to the requirements laid down in the test, the Signal signal is set at the output of the comparison unit 7, and the control unit 4 remains in the state corresponding to the last control action.

Thus, the proposed device makes it possible to check the quality of the electrical contact between the terminals of the tested chip and the block of transitional contacts directly during the test, which significantly increases the response speed of the control as a whole. Building a device on chips (TTL logic) makes it possible to increase reliability.

Claims (4)

1. A device for control of microcircuits, containing an impact register, a control unit, a reference register eight Comparison unit, trigger trigger5 0 ka, three terminating resistors, a switch and an OR-NOT element, the inverse S input of the start trigger is connected to the device start input, the start trigger output is connected to the control input start terminal, the first and second information outputs of which are connected to the information inputs of the impact register and the register of reference reactions, the outputs of the register of reference reactions are connected to the first group of information inputs of the comparison unit, the output of which is the output of the device's life, the inverse R input of the start trigger with yield of the connections of the OR-IE, and the clock input of D-flip-flop through a first starting resistor connected to the row WMOs device for connection to you A power supply front bus, characterized in that, in order to improve speed, the device contains the first and second contact monitoring registers, the first and second contact monitoring blocks, the initial setup input of the device connected to the installation inputs of the impact register, the control unit, the first and second blocks contact control, to the first input of the element OR NOT and to the first installation inputs of the first and second contact control registers, the output of the synchronization of the control unit is connected with register sync 40 45 effects and reference reactions, the output of the comparison unit is connected to the information input of the control unit, the enable input of which is connected to the switch output, the second input of the element OR NOT connected to the stop output of the control unit, the enabling output of which is connected to the control input of the switch, the outputs of the first and second the contact monitoring registers and the first and second contact monitoring units are connected with a group of information inputs of the switch and form the information output of the device, the output group register influences connected to the group output device for connection to heavy bidirectional bus controlled pulse sequences chip, the clock bits contacting a first register control device connected to a group of inputs 50 for connecting to the bi-directional bus and the output bus of the pulse sequences of the controlled chip, the second group of information inputs of the comparison unit is connected to the input group of the device for connecting the output circuits of the controlled chip to the output bus, the first information inputs of the first and second contact monitoring blocks are connected to the input of the device for connecting to power supply output bus, information input and sync input of the second contact control register Res second terminating resistor are connected to an input device for connection to the output bus of the power supply, information input and second input of the first register of the mounting con onnym 20 and the clock inputs of flip-flops The control contact is connected via the third terminating resistor to the device input for connecting the output power supply bus, the second information input of the first contact monitoring unit is connected to the input of the device for connecting the supply voltage of the controlled chip to the output bus, the second information input of the second Contact monitoring unit is connected to the input device to connect to the output bus of the single potential of the controlled chip, the second installation input of the second D contacting istra control device is connected to the input for connection to the output bus of zero potential controlled chip. 2, The device according to claim 1, about t l and h a-40 mation input of the second control unit So that the control unit contains a counter, a pulse generator, an inverter and a memory element, the outputs of the first and second information fields, the stop field and the resolution field of which are the corresponding outputs of the control unit, the reset input of the counter is set the input of the control unit; the start input of the pulse generator is the start input of the control unit; the output of the pulse generator is connected to the counter input of the counter and through the inverter is connected to the synchronization output of the control unit, the output of the counter, and info The control unit input inputs form the memory element address input, the memory element selection enable input is the control unit enable input. 3. The device according to claim 1, of which is that the first contact monitoring unit contains a group of comparators, a group of inverters, a matching resistor and a group of flip-flops, with the first inputs of the group comparators forming the second information input of the first the contact control unit, the first information input of which is connected to the second inputs of the group comparators and through the matching resistor to the information group, the outputs of the group comparators are connected to the inverse S-inputs of the corresponding t through appropriate inverters iggerov group usta- novochny control input of the first contacting unit is connected to the inverted R-inputs of the group of flip-flops, the outputs of which form the output of the first contacting unit control. five 4. The device according to claim 1, characterized in that the second contact monitoring unit contains a group of comparators, a group of inverters, a matching resistor and a group of flip-flops, the first inputs of the group comparators forming the second information input of the second contact monitoring unit, the first information contacting through to the second inputs of the group comparators and to the information inputs and synchronous inputs of the group triggers, the outputs of the group comparators are connected to the inverse S-in through the appropriate inverters AMS respective triggers group setup input of the second contacting unit is connected to the control inputs of the inverse R- group flops whose outputs form the output of the second contacting unit control. 25 | 33 I 12 thirty J5 Fig 2 J h / f 37 : 2B Fi.CH Phi2.5 ETC pnu Unum. 20 Editor E. Papp Compiled by D.Vanyuhin Tehred I.Popovich Order 2866/46 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Unum Fi.e Proofreader G. Reshetnik