SU1562864A1 - Apparatus for functional parametric check of logical elements - Google Patents

Abstract

This invention relates to instrumentation technology. The goal is to increase the reliability of control of the device by reducing the error in controlling the propagation delay. The goal is achieved by the introduction of a reference signature setting unit 21, a register 20 and a pulse former 19, programmable power supplies 22 and 23. The device also contains 1 clock pulse generator, counter 2, logic drivers 3-1 ... 3 N logic levels, decoder 4, switches 5 and 7, load block 8, multiplexer 9, signature analyzer 10, fault analyzer 11, programmable power supply 13 , current consumption sensor 14, comparators 15 and 16, boundary level setting unit 17, pulse driver 18, and control unit 12. 2 hp f-ly, 2 ill.

Description

Shaper analyzer signatures 10 40 to the analyzer P Fault to issue

signal is suitable for indication and output of the device.

The boundary value of the delay

stops, the resulting signature is compared with the reference one and is copied from the signature generator to the indication register, after which the signature generator automatically collects the signal's propagation signal can be set. When at the start-stop input but, for example, a push-button switch of the analyzer 10 appears again, the LORIES, entering the delay programmer 26, or may be formed (of various sizes) in accordance with the program zero at the inputs (bit i + 1 + l of the counter 2 goes to the zero state), a new cycle of the device 50 begins: a new signature is formed, which in state 1 at the start-stop input in the signature analyzer 10 is compared with the reference signature. The result of the comparison is supplied to 55 Daring first information input of the fault analyzer 11, which in the case of inequality of the indicated signatures on the strobe signal coming from the third output of the control unit 12

HOUSE,

torus 26 from the outputs of counter 2 connected to the second group of first inputs of control unit 12. In the latter case, it is possible to measure the signal propagation in the monitored element 6, since the value of the boundary value of the delay can be reduced from one signature acquisition cycle to another, until from the analyzer 11

The g-signal signal can be set, for example, by a pushbutton switch, entered into the latch programmer 26, or it can be formed (of different sizes) in accordance with the signal input signaling program input, for example, by means of a pushbutton switch lei, included in the delay programmer 26, or may be formed (of various sizes) in accordance with the input to the inputs of the program

HOUSE,

torus 26 from the outputs of counter 2 connected to the second group of first inputs of control unit 12. In the latter case, it is possible to measure the signal propagation in the monitored element 6, since the value of the boundary delay value can decrease from one signature acquisition cycle to another until from the fault analyzer 11 to the second input of block 12 (to the first input of the OR element 27) the result will not come; In this case, the code of the intended delay value is indicated by indicator 28,

The ability to connect the inputs of the delay programmer 26 (the second group of the first inputs of block 12) to those outlays of counter 2, to which the address inputs of the multiplexer 9 Ј are connected, in our example, bits i + 1, i + 2 ,,.,., i + 1), allows control of the delay on each output of element 6 separately with the definition of the eigenvalues of the boundary value of the delay. If, however, connect the inputs of the programmer 26 to the same countercode 2 codes to which the control inputs of the power supply sources 13, 2.2, and 23 are connected (the memory switch to the i + 1 + 2, i 4 + 1 + 3 ,, ..) then it is possible to take control of the signal propagation delay of the element 6 by setting the boundary Hfrx of the delay values, depending on the VALUE of the supply voltage and the input levels of the monitored element 6.

In the process of monitoring (at different power levels and different levels of input signals), the current consumption of the monitored element 6 is monitored. For this, a comparator 15 is used, comparing the value of the current coming from sensor 14 with the limit value arriving from the second output of block 37 of assigning boundary levels. If the current consumed by element 6 exceeds the limit value, a Scrap signal is output from the comparator output to the second information input of the analyzer H, from the output of which (as in the case of inequality of signatures) the Scrap signal is output to the display, to the output of the device and (through the OR element 27) on the blocking input of the counter 2, stop the operation of the device.

During the control unit 8 loads Provides load outputs of the controlled logic element 6 to the nominal value.

To restart the device, it is sufficient through the driver 24 of the control unit 12 to reset the Counter 2.1

The second mode is used to simultaneously with the functional control to provide dynamic control of the IC (not containing incompatible inputs) with increased accuracy. In this case, the IC inputs are connected directly to the outputs of counter 2, and the duration of the pulse generated by the driver 19 is equal to the sum of the value of the propagation delay of the element 6, set by the programmer 26, (included in block 12), and the constant delay equal to the propagation delay of the counter 2 signal. Thus, the with a propagation delay of the signal generators 3, L9, .., 3, n and error control signal propagation delay member 6 it depends only on the variation Counter 2 parameters and register 20.

In order to ensure the control of logic elements (for example, ICs) that have both incompatible and compatible inputs, it is necessary to connect the inputs of the decoder 4 to the outputs of counter 2 (for example, two lower-order bits) with the help of switch 2 to the outputs the decoder is 4, and the compatible inputs are to the outputs of the logic level drivers (for example, 3.3, ..., 3.1).

Otherwise, the preparation for operation and operation of the device are no different from the first mode of operation when controlling ICs that do not have incompatible inputs. The only difference in operation is unchanged input signal levels at incompatible inputs.

In order to ensure simultaneously with the functional-parametric control of ICs containing incompatible inputs, their dynamic control with sufficient accuracy, the values of the propagation delay of the signal from the decoder 4 and the drivers 3 must match.

For each type of logic elements having incompatible inputs (for example, triggers, counters, etc.) it is advisable to make a replaceable switch.

If the number of different types of combinational ICs that do not contain incompatible inputs) to be monitored is small, then interchangeable switches can also be made for them. As a removable switch can be applied mate multi-pin connector with jumpers.

If it is necessary to control many different types of combinational ICs with the same number of pins, it is recommended to fabricate a switch on which the pins are connected to the outputs of the counter 2 using the switches (via drivers 3 or directly). ) or register entries 20.

In the proposed device, along with the operation control, with automatically varying power supply voltage, control of the current consumption and output voltage levels of the logic zero and unit of the logic element, the signal propagation delay is controlled with a reduced error.

In addition, the introduction of the second and third programmable power sources allows control of logic elements with automatically varying levels of x input signals, which increases the reliability of the parametric control.

35

Thus, the target device allows simultaneous control of the basic static and dynamic parameters with a reduced error, and therefore the reliability of the control is significantly increased. ,

Claims (3)

1. Device for functionally parametric control logic., - elements, containing a generator of clock pulses, a counter, Amplifiers of logic levels, connected by information inputs to the counter outputs, the first switch connected by the first inputs to the counter outputs, the second inputs - with shaper outputs of logic levels, inputs-outputs — with terminals for connecting the outputs of a controlled logic element, a decoder connected by inputs to the first outputs of the first switch, second commutation Ator, information and address inputs 0 5 about five - the ports of which are connected respectively to the second and third outputs of the first switch, a block of loads connected by inputs to the fourth outputs of the first switch, a multiplexer connected by address inputs to the third outputs of the first switch, and information inputs to the second outputs of the first switch, a signature analyzer connected by the first information input with the multiplexer output, and the start-stop input - with the fifth output of the first switch, a fault analyzer connected by the first information inputs Dami with outputs of the signature analyzer, control unit connected to the first, second and third outputs respectively to the installation, blocking and gating inputs of the fault analyzer, programmable power supply connected to the output of the monitored logic element, current sensor, first comparator connected to the output, the second information input of the fault analyzer, and the first input to the second output of the programmable power source and through the current consumption sensor - with bus busing, the second comparator connected to the third information input of the fault analyzer, and the first information inputs to the output of the second switch, the boundary level setting unit connected to the first outputs of the second information input of the second comparator, and the first pulse shaper connected with the output to the gate input of the second comparator, which is due to the fact that, in order to increase the reliability of the control, a reference signal setting block is introduced into it the atura, the register and the second pulse generator, whose information inputs are connected to the fourth outputs of the control unit, and the output — With the synchronous input of the register connected by information inputs to the fourth outputs of the first switch, and the outputs to the information inputs of the multiplexer; the second information inputs of the signature analyzer are connected to the outputs reference signature setting unit, programmable power supply control inputs 1515 The first input of the first comparator is connected to the second output of the boundary level setting block, the counter count input, the signature analyzer synchronous input, and the setup inputs of the first and second pulse formers are connected to the output of the clock generator , the installation and blocking inputs of the counter are connected respectively to the first and fifth outputs of the control unit, the first inputs of which are connected to the seventh outputs of the first - of the switch. 2. The device according to p., Characterized in that it introduces the second and third programmable power supply sources, the control inputs of which are connected to the sixth outputs of the first switch, and the outputs - respectively to the inputs Level zero and Unit level of the logic level drivers. 864 0 sixteen 3. Device pop. 1, characterized in that the control block comprises a reset signal shaper, a control signal shaper, a delay programmer, an OR element and an indicator connected by inputs 1 to the first block inputs, the first group of which is connected to the inputs of the control signal shaper, and the second group - with the inputs of the delay programmer connected by the outputs to the fourth outputs of the block, the second input of which is connected to the first input of the element —OR, the output of which is connected to the fifth output of the block, and the second input to the second. Each block and the first output of the control signal generator, the second outputs of which are connected to the third outputs of the block connected by the first output to the output of the reset signal generator, the input of which is connected to the third input of the block.