SU1555704A1 - Tester for checking digital units - Google Patents

Abstract

The invention relates to the field of automation and computer technology and is used in the control of digital and logic blocks. The purpose of the invention is the extension of functionality due to the control of both logical and fully integrated memory integrated circuits (ICs) that have circuit closures between each other, on a common bus and power bus, without breaking the connection between the IC and digital by block. The tester for controlling digital blocks contains a data register and two potential isolation blocks, a command register, a switching unit, a three-level key block, a command decoder, a comparison unit, a comparators unit and a reference block. IP monitoring is performed by exhaustive search of potential signals in the Gre code, which allows to unambiguously exit from the forbidden combinations at the inputs of the IC when monitoring IC with memory. 2 Il.

Description

The invention relates to an automaton, computer and computing technology and can be used to control digital blocks.

The purpose of the invention is to expand the functionality by controlling embedded in a digital unit both logical and fully accessible memory integrated circuits having circuit closures of the terminals between themselves, on a common bus and the power bus without breaking the connection between the integrated circuit (IC) and digital block.

Figure 1 shows the tester; FIG. 2 is a bit of a three-level key block.

The tester (FIG. 1) contains a data register 1, blocks 2 and 3 bus drivers, switch register 4, switching unit 5, three-level key block 6, instruction decoder 7, comparison block 8, comparators block 9, reference IC 11 controlled units. In addition, FIG. 1 shows a test formation and reaction processing (UTP) device 12 and an address selector 13 generating synchronization signals.

The device shown in Fig. 2 contains an open collector AND-HE element 14 (related to the decoder 7 commands), resistors 15-22, keys 23-25 (belonging to block 6 of three-level keys), transistor 26, paired comparator 27 (related to

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block 9 comparators) and the elements of E 28 and 29.

The IC control of a digital unit with this tester is possible for ICs that have n pins, therefore, on the corresponding cables of the tester, where it is necessary, the numbers of n or 2p cable lines are marked.

The tester for controlling digital blocks works as follows.

The data bus width (SM) of the UTR, which is implemented on the basis of the microprocessor of the system, is limited, therefore, receiving information in the registers 1 and 4 of the tester and reading the reactions through blocks 2 and 3 are done in -s. This is ensured by the sequential supply of single signals of the desired group P1, P2, P3 or P4, which are generated by the address selector in accordance with the address bus status (AC), followed by the SI sync signal.

After connecting to the tester using a test terminal of a monitored IC 11 digital unit and a reference IC 10 inserted into a special adapter, the operator indicates the code of the type of monitored IC. This code in the UTR reads the description of the inputs-outputs of this type of IC . The I / O description is an n-bit word (16-bit in IP control, having 14 or 16 outputs), each bit of which can take one of four values describing the type of output of an IC: A output is an input; With the output - counting input; B - output is one of the outputs; X - it is necessary to supply a high impedance state from block 6 to this IC output.

The signal applied to the input with code A causes a single response at any output, and a multiple change of the signal at this input from 0 to 1 causes the same type of response, even if the IC includes memory elements. The signal applied to the input with the code C, with a repeated change from 0 to 1 at certain values of the input signals at the remaining inputs, transforms the memory chip to other states. The output with the code B serves to remove the reactions at the outputs to the input actions. Conclusion with

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X code is not processed. The encoding of one output is performed with the help of two binary bits.

If ICs are monitored, having the maximum number of pins 16, then when monitoring an IC with 14 pins, the eighth and ninth pins remaining empty are encoded with code X, and the terminal numbers greater than the seventh are increased by two.

Next, the inclusion of the digital unit IC 11, i.e. pin closures on the power bus and common bus, as well as closures between the pins are determined. In the switching register 4, the signals P1 enter information, which, being fed to the switching unit 5, isolates the reference IC 10, disconnecting all communications between its terminals and the monitored unit. Then, in register 1 of data on signals P2, information is entered, which, arriving through the decoder 7 commands to the inputs of the three-level keys of block 6, causes level 1 signals at their outputs, the power of which is limited by a certain current (in the tester 300 mA). These signals are sent from the keys of block 6 to all outputs of the IC 11. If the output level O is detected on any output, it is defined in block 9 of the comparators, i.e. on this pin, the voltage level is less than 0.6 V at the maximum current of the three-level key, the Comparators block 9 at one of its outputs issues a message arriving at the information inputs of block 3, and this IC output 1} is considered closed in the digital block common bus. Similarly, closures to the power bus are detected, only from the outputs of the 6-key block, signals O are output. The output on which 1 is registered is considered closed to the power bus.

The determination of the closures on the common bus and the power bus, and further the closures between the terminals, is performed by the voltage level at the outputs of the three-level switches. The decisive element is a paired comparator, controlled by the decoder of 7 commands. A schematic diagram of one of the channels of blocks 6, 7, and 9 is shown in FIG. 2. From the diagram it can be seen that the information for one channel is encoded by two information bits arriving

from register 1 to the input of the decoder 7 (elements 28, 29, 14), which controls the three-level key (elements 15-25) and the comparator (element 26 and 27). Moreover, if a signal is applied to the input of the decoder 7, which causes level 1 at the output of the key, then from a pair of comparators a comparator is connected which determines the presence of zero, i.e. the lower of the pair 27 (the comparison is made with a reference voltage of 0.6 V). If the key issues O at the output, the upper comparator of the pair 27 is connected, and the comparison is made with EOP1 1.8 V.

The three-level key is designed to feed the required potential signal to the inputs of the tested IC 11 digital block. The comparator determines the level received at the input of the IC for comparing it with the supplied level, since the current of block 6 is limited to 300 mA, the decoder 7 commands are used to convert the input signals XI and X2 from register 1 to the control signals of the three-level key and comparator

Replacing pulsed sources of stimulating signals with potential ones allows, along with control of blocks containing only logic ICs, to control blocks containing ICs with full accessible memory (triggers, registers, counters), since the stimulating effects are maintained even between the moments of information retrieval, allowing the test IC to go to arbitrary states. Potential impacts are delivered throughout the entire monitoring cycle from installing the monitored and reference ICs into the same state, then throughout the entire time the stimuli are applied in the Gray code (this code avoids ambiguous reactions when removed from the IC inputs 10 and 11 of the forbidden sets) and until the end of control.

The results of the monitoring step, read from the outputs of block 9 through block 3 by signals P4, enter the UTR and are displayed in it for perception by the operator. The operator according to the block diagram in which the monitored IC 11 is built in determines whether the output of this pin is actually closed to the corresponding bus. If necessary, close

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The operator initiates the continuation of the program, and the position of the closed output is fixed.

Detection of short circuits between the outputs of the monitored IC is made for leads that are not closed to the common bus and the power bus. The closure between the pins is determined by the distortion of the signal applied when the current of a key of block 6 reaches its maximum value when applied to two closed pins O and 1 at the same time, since in this 5 case two keys of block 6 giving opposite values are connected by outputs and work on each other. The procedure for detecting closures is as follows. To the first one not closed to the power supply and the common bus, the output is supplied from block 6, a level 1 signal, to the next O. A signal of a high impedance state is given to all other outputs. Then O is shifted to the next output, and a high impedance state is applied to the output to which O was fed, and so on. At each new position O on the outputs of the IC, the comparator unit 9 controls the distortion of the levels of the applied voltages. For this, information from the outputs of block 9 through block 3 is read by signals P4 to the UTR. When a closure is detected, the pin numbers are fixed. Then 1 moves to the next output and the process repeats until the end of the monitoring of the closures of all outputs

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between the pins, the control is interrupted, a high-impedance signal is sent to all pins, and the UTR is shown to

c the numbers of closed pins. The operator, based on the circuit diagram of the unit in which the controlled IC is embedded, determines if there is a short circuit between these terminals.

0 actually. If it is necessary to close, the operator initiates the continuation of control, otherwise the IC is either considered faulty or incorrectly switched on. Closing Information Used

This is as follows. If there is no output among the closed pins (code B), then all closed pins, except for one, are then given a high-impedance state, and testing

The common information is fed to one input. If there is an output among the closed outputs, the high-impedance state is fed to all the outputs, and the testing information to the inputs of the IC comes from the output closed with them4

Next, the outputs of the IC 11 embedded in the digital unit are switched with the reference IC 10 outputs. The outputs that have codes A and C that have the B code, i.e. outputs, as well as pins with code X. Switching is performed using the switching unit 5, which is controlled from the switching register 4,

If from register 4 in the corresponding channel to the input of block 5 signal 1 is received, then the inputs of the reference ICO receive signals taken from the inputs of the monitored IC 11, and the signal of this channel at the output of the comparison unit 8 is zero for the whole subsequent monitoring time In this mode, the reference IC receives signals and power from the monitored unit. When entering in any channel from the register 4 O, signals from the outputs of the monitored and reference IC are received at the corresponding inputs of the comparison unit 8. At the output of this channel of unit 8 of comparison, a signal is generated comparing the reactions of both ICs to the same effect at the inputs. If there are different reactions at the corresponding output of block 8, a signal appears equal, which indicates a fault in the IC integrated into the monitored block.

After the closure of the IC outputs, further work on controlling the operability of the IC I1 is performed with the remaining inputs. The remaining inputs are the pins of both ICs, having in the initial encoding codes A and C and not closed on a common bus and power bus, and, moreover, not having received the X code due to closures with other pins.

For any type of IC — logical or memory — the initial state is set, since logical ICs can also be included as memory elements.

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Installation in the same state is performed by applying to all the remaining level inputs, which is a successive change in the state of each of the remaining inputs to the O. As a result, the O level is set to all the remaining, both ICs.

When setting the same conditions and further when tested with potential signals in the Gre code, the IP property is used to give the same response to the same input effect, even if this effect is a forbidden set on the installation inputs (this does not apply to counting inputs, since Memory ICs that are in different states may give different responses to the same input signals. Removing the forbidden dialing from two or more installation inputs by simultaneously inverting their states leads to the uncertainty of the states of the memory elements. If the forbidden set is removed, in turn by inverting the state of the setup inputs, the final state of the memory elements of the IC will be strictly defined.

After the installation is completed, the forbidden sets may be present at the inputs of the IC, which does not affect further monitoring, because the test information is fed to the inputs of the IC in the Gre code, i.e. In each control cycle, the state of So many of the remaining inputs is inverted.

After the installation of both ICs is completed, it is necessary to check whether they are installed in one state. For this, the result of the comparison of the states of all the outputs of both ICs from the outputs of block 8, the comparison through block 2 of shapers is read by the RTR signals, if at the outputs of block 8 at least 1 is fixed, it means that the installation could not be performed or malfunction of IC 11, or due to its specific activation, which prevents installation; In both cases, a message indicating that it is impossible to install both ICs in the same initial state is indicated on the display. Control is terminated.

If there is an installation in the same initial state of both ICs 10 and 11

the transition is made to the control of the directly logical functions of the monitored IC 11.

The control of the logic functions of the IC 1 I is performed by applying a complete enumeration of binary combinations in the Gre code to all the remaining inputs of the IC and comparing (each time the new code is submitted) the reactions of IC 10 and 11 to the same input action. Brute force limits the scope of control of this type to microcircuits of small and medium integration, which have a full accessible memory.

When controlling an IC with memory, each supply of a new code to the inputs of the IC is accompanied by repeated inversion of the states of one of the counting inputs (code C), then the other, and so on. at all counting inputs so that the memory chip goes through all its possible states. Each inversion of the state of any counting input is also accompanied by information retrieval for comparing reactions. The number of state inversions of the counting inputs depends on the type of IC under test and for the counters should be no less than their double maximum conversion factor, since the counters are triggered on one edge of the signal on the counting input (in the tester, taking into account the conversion factors of 2, 4, 6, 8, 10, 16 triggers and counters of the most common series of microcircuits, the number of inversions is 32).

Information about the comparison of reactions is collected from the outputs of the comparison unit 8 through the block 2 of the tire generators according to the P3 signals. If any reaction mismatches, a malfunction message is displayed and the monitoring process is interrupted, and the UTR tester is put into a mode of waiting for the input of a new type of monitored IC. In the event of a malfunction, you can get a message on which input set the reactions of the IC are different and on which output different reactions are received. The coincidence of the reactions of both integrated circuits in all control cycles indicates the operability of the controlled integrated circuit 11.

A self-test of the tester is performed by monitoring a known type of IC with a predetermined power on and a known fault introduced. Correct detection of

serviceability guarantees almost one hundred percent performance tester. Thus, a tester for monitoring digital blocks, controlling blocks by monitoring integrated circuits embedded in a given block, performs static IC monitoring without breaking the link to the block and

0 keys to the tester with test clips at the ends of extension cables. Monitoring is performed by potential signals in the Gre code, with a series of pulses applied to the counting

5 inputs of the IC, which allows controlling not only the logical ICs, but also the ICs of average integration with full access memory. The control takes into account the circuit switching of the IC, i.e. closures

0 conclusions between each other, on the common bus and the power bus, therefore the sources of potential stimulating effect (three-level keys) have protection against short-circuits on the common bus,

5 bus power and from the closure between their outputs. The control is performed by comparing the reactions, at the outputs of the reference and controlled IC with the same input effects, that

0 allows you to refuse storage in special ROMs of truth tables and transition tables for all types of controlled ICs.

The tester allows you to control most of the common circuits (in this development with up to 16 conclusions) - TTL schemes, Schottis / TTL ICs, MOS ICs, K / MOI ICs and other CSs that have levels O and 1 and power, similar to TTL ICs including full accessible memory elements (registers, counters, triggers).

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Claims (1)

Invention Formula A tester for controlling digital blocks containing a data register and two potential isolation blocks, the information inputs of the data register being information inputs of the tester, the outputs of the first and second potential isolation blocks are connected to the outputs of the tester, the control inputs of the data register, the first and second blocks potential isolation is connected to the first, second and third clock inputs of the test tera, respectively, differs from the fact that, with the aim of expanding the functionality by controlling built-in digital block, both logical and full-accessible memory integrated circuits that have circuit closures between each other, bus and power bus, without breaking the connection between the integrated circuit and the digital unit, a command register, a switching unit, a three-level key block, a command decoder, a comparison unit, a comparators unit and a reference unit are entered into it; the mand is connected to the tester's information input, the control input of the command register is connected to the fourth tester synchronization input, the output of the command register is connected to the information input of the command decoder, the data register output is connected to the control input of the switching unit, the first group of information input-outputs of which is connected to the group reference inputs 0 block and with the first group of inputs of the comparison block, the outputs of which are connected to the information inputs of the first potential isolation unit, the group of outputs of the command decoder is connected to the group of control inputs of the three-level key block, whose information inputs are connected to the buses of logical zero and tester units, the output of the command decoder is connected to the resolution input of the comparators block, the outputs of which are connected to the information inputs of the second potential isolation block, the first group of information inputs of the block a comparator connected to the bus reference voltage tester, a second group of information inputs of the comparator unit is connected with a group of three-level block key outputs from a second group of inputs comparator block, group of information inputs of switching block and is a group 5 tester outputs for connection to a group of inputs and outputs of a monitored unit. 0