SU1520548A1 - Device for diagnosis of faults of logical modules - Google Patents

Abstract

The invention relates to the field of instrumentation technology and can be used in the adjustment, monitoring and troubleshooting of digital blocks on integrated circuits. The aim of the invention is to increase the reliability of the control. For this purpose, a device containing a control unit, test generator, first data register, signature analysis unit, trigger, two AND elements, an indicator, a contact probe and two differential amplifiers, a switch, two OR elements, a NOT element, a second data register, unit of measurement counters and the third differential amplifier. 1 hp f.ly, 4 ill.

Description

The invention relates to an instrumentation technique and can be used in adjusting, monitoring and diagnosing malfunctions of digital blocks on integrated circuits.

The aim of the invention is to increase the reliability of the control.

FIG. 1 shows a block diagram of a device for diagnosing faults in logic blocks; in fig. 2 is a functional block diagram of the control unit; FIG. 3 - functional block diagram of measurement counters; in fig. 4 - functional diagram of the signature analysis block.

The device for diagnostics of faults in logic blocks (Fig. 1) contains a contact probe 1, a switch 2, a monitored block 3, a generator of 4 tests, a block 5 of control.

differential amplifiers 6-8, the S indicator 9, the element NOT 10, the first data register 11, the signature analysis unit 12, the OR element 13, the second data register 14, the measurement counter block 15, the AND element 16, the trigger 17, the OR element 18 , element And 19.

Contact probe 1 connects the monitored pins of the digital unit 3 through a differential amplifier 8 to the inputs of the signature analysis unit 12 and the measurement counter unit 15.

The switch 2 automatically connects the outputs of the monitored unit at the address specified by the control unit 5 to the output of the contact probe 1.

The test generator 4 generates a sequence 3 per controlled block

control tests in accordance with the address determined by the control unit 5. Generator 4 is made in the form of a removable reprogrammable memory device, converts the serial binary code received from the output of control unit 5 into a control test sequence, is required to check the control object (OK) and is made as a set of replaceable reprogrammable module , each of which contains information with test actions for specific types of OK.

In particular, when verifying the OK with a running unit type test, the truth table for block 4 looks as follows.

For other types of OK, the control test is defined in accordance with its internal logical structure.

Block 5, designed to control the operating modes of the entire device cutter, element 13 fixes on the indicator 9 the condition of an open circuit and a level fault, respectively. The same signals through element 18 set the trigger 17 to a position that prohibits, through element 16, outputting the results to registers 11 and 14 from the signature analysis block 12 and the measurement counter block 15, respectively. The element NOT 10 makes the choice of presenting information from the registers 11 and 14 through the element 13 to the indicator 9.

Block 15 (FIG. 3) consists of an interval imager and measurement frequency, performed on a counter 35, a conversion start trigger 36, an AND-NE element 37, a first 38, a second 39 and a third AND 40 element, an OR 41 element, a synchronization trigger 42, the counter 43 of the measurement result of the fourth 44 and an additional 45 elements And

Block 12 signature analysis (Fig. 4) contains a shift register

va and forming sync signals. Start-25 adder 47 modulo two, perlo, pa, nc.

Test address, Switch address - Shift, Pulse, Selection, Co. Mode selection, contains (FIG. 2 clock generator 20, And 21, trigger 22, I1Sh 23, counters 24 and 25, decryptors 26 and 27, and 28) 29 and the element OR 30, the buttons 31 and 32, the switches 33 and 34 modes of operation.

Differential amplifiers 6 and 8 and element 19 carry out the tolerance level control at a controlled point switched through probe 1 to the first (positive) input of amplifier 6 and the first (negative) input of amplifier 8, the second (negative input of amplifier 6) voltage of logic 1 in the range + 0.1 ... + 9.9B, and the second (positive) input of amplifier 8 is supplied with a threshold voltage of logic O in the range of + 0.1 ... 9.9V.

The differential amplifier 7 is monitored for contact with a controlled point, for which a bias voltage of -0.1 V is supplied to its first (negative) input, and a bias current is applied to the second (positive) input connected to the contact probe so that in the absence of contact between probe 1 and the controlled point of unit 3, a potential of −0.2 V is present. Output of amplifier 7, as well as element 19 che

five

0

Q

five

0

five

the second input is connected to the output of amplifier 6. Sixteen outputs of register 46 are connected to inputs of register 11. In addition, the outputs of the seventh, ninth, twelfth, and sixteenth bits of register 46 are connected to the input group of the adder 47, and its output is connected to the information input of the register 46, the synchronization and initial installation inputs of which are connected to the outputs of the control unit 5.

The device works as follows.

In the signature analysis mode, the switch 33 is in the upper position, and the function selection switch 34 is in the closed position, which determines a single reading of the input sequence from the selected point of the monitored block. By pressing the button 32 of the control unit 5, the device is transferred to the initial state ;, and after pressing the button 31, it begins a cycle of operation. In this case, the trigger 22 permits the passage of clock pulses from the generator 20 through the element 21 to the input of the counter 24 addresses of test effects and then through the decoder 26, the element 28, the elements 29 and 30 are generated clock signals Start, Shift, Mode selection. The end.

- The input sequence from the controlled point of the block 3 through the probe 1 enters the differential inputs

51

amplifiers 6–8. In the absence of a contact, a negative bias voltage detects a signal 1 at the output of amplifier 7. In the case that the signal levels at the probe input do not correspond to the selected threshold values of logic 1 and logic 0, set in the range of +0.1. ,, 9.9V, at the output of amplifiers 6 and 8, respectively, signals 1 are fixed, when they arrive at the input of element 19, the latter, together with the signal taken from the output of amplifier 7, is displayed through element t3 on indicator 9, which allows be neis Marriage equality type layer and the Open circuit

On a signal the beginning of the control block 5 is resetting the signature analysis block 12, block 15 of measurement counters and trigger 17 allowing the End signal to pass through element 16 from control block 5, which begins to give addresses to the test generator 4, stimulating the input contacts of the monitored block 3, The input sequence, taken from the control points of block 3, is fed through the probe 1 to the input of the differential amplifier 6, is compared with a threshold value and is input to the information input of the block 12 of the signature an Aliza, at which time the input of the shift comes from the control unit 5, the Shift pulses, which record the input sequence.

; At the end of the monitoring cycle, the result from block 12 is copied to register 11 by the End signal, which comes through element 16 from control block 5, and then the resulting signature is displayed on indicator 9. In the event that signals start and end appear in the control process errors of type of marriage level or open circuit, they are displayed on the indicator 9, as well as the passage through the element 18, set the trigger 17 to the position prohibiting the passage of the signal End through the element 16, the result of the control in this case is not copied from the block 12 and the signature analysis register 11,

When the device operates in the functional measurement mode, the switch 34 is set to the selected function, which gives out the operation mode of the unit 15.

486

In this case, the signal from the output of the cltta 30 prohibits the output of information from register 11 and allows the output of information from register 14.

The clock signal from the output of the generator 20 generates a grid of frequencies in block 15 used in various functional measurement modes.

If the frequency measurement mode is enabled by the signal from input F, then when a signal arrives, the start of the result of counter block 43 of the result is zeroed at the input of the block, and on the falling edge of the signal, Start Trigger sets a logical 1 at the first input of element 39. At the same time, from counter 35, through element 38 and then, through the element 41, the counting interval impulse goes through the element 39 to the input of the trigger 42 and at the output of the element 45 a logical 1 signal appears, which permits the passage of pulses from the line. The input through the element 44 to the input of the result counter 43 and schaet passage next signal start to the end conversion. On the trailing edge of the measurement interval pulse specified by counter 37, the synchronization trigger 42 prohibits the formation of a new measurement cycle before the start signal arrives.

Thus, as a result of the described measurement cycle, the result counter 43 contains the measured frequency value, which through the register 14 and the element 13 is displayed on the indicator 9,

If the period measurement mode is enabled by the signal from input T, then the operation of block 15 is performed in the same way, except that the counting interval is set by an external signal from the input line through element 40, and the filling frequency comes from counter 35 through element 37 to element 44 and further at counter 43 results

When unit 15 is operating in the pulse number counting mode, the signal from input N allows the input pulses to enter the counter input 43 of the result for the entire time between senders.

When the device operates in the cumulative signature removal mode, the switch 33 is in the lower position, and the switch of all device nodes is performed in the same manner as for signature analysis, the only difference being that the input signal from the output contacts of unit 3 enters the input of probe 1 through switch 2, which is controlled is produced by a contact counter 25 and a decoder 27 of the control unit 5. The operation of the device in this mode takes place in such a way that the Start signal is generated by element 29 only at a zero address of the counter of 25 contacts, and later when switching to the next contact at the End signal arriving at the counting input of counter 25, the probe 1 is sequentially connected through switch 2 to all output contacts of block 3 with simultaneous delivery of test messages: impacts and compression of incoming information without nulling the block 12 of signature analysis — when switching to the next contact of block 3, Last address eshifratora 27 resets the flip-flop 22 through the member 23 to its original state, and is displayed on the display 9 The overall signature of the block 3. By matching or difference from the last reference information deciding serviceability controlled unit.

Claims (2)

1. A device for diagnostics of logic block faults, containing a control unit, test generator, first data register, signature analysis unit, trigger, two AND elements, indicator, contact probe and two Differential amplifiers, the test generator start input connected to the first control unit output and the output of the test generator is the output of the device for connecting to the input of the monitored unit, the second and third outputs of the control unit are connected respectively to the sync circuit of the first data register and the input The signature analysis engine block, the fourth output of the control unit is connected to the inputs of the initial installation of the signature analysis unit and the trigger, the first and second inputs and the output of the first element I are connected respectively to the trigger output, the fifth output of the control unit and the recording input of the first data register, the first contact output the probe is connected to the first inputs of the first and second 1520548. 8 differential amplifiers, the second inputs of which are connected respectively to the single threshold setting bus and the zero threshold setting bus, the output of the first differential amplifier is connected to the first input of the second And element, the information input of the signature analysis, the output of which is connected to the information input of the first data register, and the output of the second the differential amplifier is connected to the second input of the second element AND, ten 15 20 25 thirty 35 40 45 50 55 In order to increase the reliability of the control, it contains a switch, two SHS elements, a NOT element, a second data register, a block of measurement counters and a third differential amplifier, the first input of which is connected to the bus of the open circuit level threshold, the second input of the third differential amplifier is connected to the first output of the contact probe and additionally connected to the bias current setting bus, the first and second inputs and the output of the first element OR are connected respectively to the output of the third differential amplifier, the output of the second ele The And and sync trigger, the first, second, third and fourth inputs and the output of the second element OR are connected respectively to the output of the third differential amplifier, the output of the second element And, the output of the first data register, the output of the second data register and the input of the indicator, the output of the first element And connected with the input of the record of the second data register, the input and output of the element are NOT connected respectively to the second output of the control unit and the synchronization of the second data register, whose information input is connected to the output of the unit with The measurement sensors, the initial setup input, the clock input and the information input of which are connected respectively to the fourth and sixth outputs of the control unit and the output of the first differential amplifier. The seventh output of the control unit is connected to the control input of the switch, the information inputs of which are the inputs to to the outputs of the monitored unit, and the switch output is connected to the second output of the contact probe, 2. The device according to claim. 15 of a tl and ch and th e with the fact that the control unit In order to increase the reliability of the control, it contains a switch, two SHS elements, a NOT element, a second data register, a block of measurement counters and a third differential amplifier, the first input of which is connected to the bus of the open circuit level threshold, the second input of the third differential amplifier is connected to the first output of the contact probe and additionally connected to the bias current setting bus, the first and second inputs and the output of the first element OR are connected respectively to the output of the third differential amplifier, the output of the second ele The And and sync trigger, the first, second, third and fourth inputs and the output of the second element OR are connected respectively to the output of the third differential amplifier, the output of the second element And, the output of the first data register, the output of the second data register and the input of the indicator, the output of the first element And connected with the input of the record of the second data register, the input and output of the element are NOT connected respectively to the second output of the control unit and the synchronization of the second data register, whose information input is connected to the output of the unit with The measurement sensors, the initial setup input, the clock input and the information input of which are connected respectively to the fourth and sixth outputs of the control unit and the output of the first differential amplifier. The seventh output of the control unit is connected to the control input of the switch, the information inputs of which are the inputs to to the outputs of the monitored unit, and the switch output is connected to the second output of the contact probe, 2. The device according to claim. 15 of a tl and ch and th e with the fact that the control unit contains a clock, generator, element I. trigger, four elements Ш1И, two counters, two decoders, a start button, a reset button and two switches, the first and second outputs of the clock generator are connected to the sixth output of the block and the first input of the And element, respectively, the input and output of which, respectively, to the trigger output and the counting input of the first counter, the trigger synchronization cable is connected to the start button output, the first input and output of the first PID element are connected to the reset button output and the inputs to the initial settings of the trigger and the first and second counters, the outputs of the first and second counters are connected to the inputs of the first and second decoders, respectively, in addition, the output of the first counter is connected to the first output of the unit, the first outputs of the first and second decoders are connected / ten 2054810 responsibly with the first and second pins of the first switch, the input and output of the second element of the Sh1I are connected respectively to the second output of the first decoder and the third output of the block, the third output of the first decoder is connected to the clock input The second counter and the fifth output of the block, the first and second inputs and the output of the third SHS element are connected respectively to the first output of the first decoder, the third contact of the first switch and the fourth output of the block, the first contacts of the second switch are connected to the bus potential bus, and the second contacts are connected to the sixth the output of the block and the inputs of the fourth OR element, whose output is connected to the second output of the block, and the second and third outputs of the second decoder are connected respectively to the seventh output of the block and the second th entrance to the first element of the SHS. 15 20 F1I.1 f At 5.11.11 Sdviz - the end / pestle Nacha / JO / At 15 Na But 16 Nach at 11.15, P J 5U T thirty On Yu, 11 J / f fez switch Half nag HQf, 15, n H06.1U.19 Phases. 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