SU1290265A1 - Device for setting tests - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to monitor and diagnose digital devices, such as LSI RAM. The purpose of the invention is to increase the reliability of the control by eliminating the influence of the specified tests on the result of the control. The device contains a clock pulse generator, pulse drivers, a counter, a code setting block, a number register, a control block, a switch, phase-shifting signals shapers. By introducing additional pulse shapers and phase-shifting drivers, the device provides multiple changes of information on the tested object, which allows to eliminate the influence the definition of the specified tests on the result of the control and thereby ensure a higher reliability of the control. 6 Il. i (Л С

Description

one

The invention relates to automation and computing and can be used to monitor and diagnose digital devices, such as LSI RAM.

The purpose of the invention is to increase the reliability of the control by eliminating the influence of the specified tests on the result of the control.

FIG. 1 shows a diagram of the device; Fig, 2 - the same, the generator of clock pulses; in fig. 3 - the same, the pulse former; in fig. 4 - the same, control unit; in fig. 5 - the same block inversions; in fig. 6 - time diagrams., For the operation of the device.

The device {FIG. 1) contains a generator of 1 clock pulses, the first 2.1, the second 2.2 and additional 2.3-2. G pulse shapers, a pulse counter 3, block 4 specifies the code, register 5 numbers, block 6 controls, first switch 7, drivers 8.1-8. phase-shift signals, inversion unit 9, output bus 10.

The phase-mapper 8.1 signal generator (FIG. 1) contains the first register-11, the first D-flip-flop 12, the first 13, the second 14 and the third 15 elements EXCLUSIVE OR, the first 16 and the second 17 elements 2I-OR.

The clock pulse generator (Fig. 2) contains the generator 18 of the reference frequency, the second register 19, the shift register 20, the first element 21 And the counter 22 and the first digital comparator 23.

Pulse generator 21 (Fig „3) contains the third 24 and fourth 25 registers, the second D-flip-flop 26, the first 27, the second 28 and the third 29 RS-flip-flops, the third counter 30, the second switch 31, the second digital comparator 32, the second 33, the third 34 and fourth 35 elements AND, element 36 OR.

The control unit 6 (Fig. 4) contains a pulse generator-37, a fourth counter 38, a permanent memory element 39, a matching element 40, a button 41.

Block 9 inverse (Fig. 5) contains the fifth register 42, the fourth elements 43.1-43.P EXCLUSIVE OR.

Clock generator 1 is designed to form a tact ™

25

902652

output pulses for counter 3 and synchronizing pulses for drivers 2.1–2. t pulses and register 5 numbers.

5 Shapers. T pulses are designed to generate control pulses with predetermined time parameters (delay, duration of DFD shaper 8.1-8 "

 About phase-shifted signals. The number of m formers 2.1–2. Tons of pulses is determined by the necessary number of control and synchronizing pulse pulses for

 process control. So, in this example, 8 pulse generators are needed to control the BIS RAM of the K581RU4 type.

Counter 3 is used to form

 The address for block 4 specifies the code and is a binary 10-bit counter, made on three K500PiE136 chips.

The code setting unit 4 is designed to form pulse sequences with a predetermined alternation of logical 1 and O, i.e. the required tests for testing certain functions of the control object. The length of the tests is determined by the scope of the test. The code setting unit 4 is a p-bit random access memory (RAM) made on K500RU415 microcircuits.

3-5 The number register 5 is designed to record and temporarily store the information generated by the block 4 setting the code, and transmit it (information) to the drivers 8.1-8. The phase-shift keyed signals according to the synchronization signals after the output of the shift register 20 of the clock generator 1. Register 5 of the number is an n-bit register (n is determined by the number of outputs of the monitored object), performed on the K500ta213 chips. In this example, 64 named chips are used to organize

 128-bit register 5 numbers.

The control unit 6 serves for information of the operation of the device nodes in the process of generating test test signals of an impact for a volume of 40.

55

ekta control

Switch 7 is designed to broadcast the output pulses from the formers of 2.1-2 tons of pulses per

312902

shaper inputs 8, 1-8. n on commands from control block 6. Switchboard on multiplexers (128 chips K150KP163) o

Shapers 8.1-8. Phase-controlled signals are used to generate (according to commands from block 6

pulses, the phase of which depends on the temporal position of the signals from the outputs of the control unit 6. The register 11 of each driver serves to receive and temporarily store information about the temporal relationships of the phase-shift keyed signal coming from the control unit 6, and to transfer this information to the blocks 12, 13, 14, 16 and 17, the Register 11 represents 9 bit memory register executed on three K500LP129 microcircuits.

D-flip-flop 12 is designed to shift the time information received from the register 5 numbers, the time interval specified by one of the pulse shapers of block 2 selected by the switch 7. D-flip-flop 12 is executed on the chips K500TM231, Logic elements 13 and 14 EXCLUSIVE OR They are used to form inverted and non-inverted signals that produce phase-shift keyed signals. Element 15 EXCLUSIVE OR is intended to compare signals from the outputs of elements 16 and 17 2I-OR and final formation (as a result of comparison) of the phase of the manipulated signal. Elements 16 and 17 2И-Ш1И serve to pass signals from the outputs of the register 5 of the number and switch 7 to the inputs of the element 15 EXCLUSIVE OR on the enable signals from the output of the register 11. Elements 13, 14 and 15 are filled on the K500LP107 chips, elements 16 and 17 are on two microcircuits K500LK121.

Inversion unit 9 is used to form inverted pulses from phase-shifted signals of shapers 8.1-8, according to control signals from unit 6. Switch 31 is made on a K500LK107 microcircuit, digital comparator 32 on a K500LM102 microcircuit.

The pulse generator 37 serves to form the counting pulses fed to the counter 38, intended W

(five

0

ns to form the address of element 39.

The constant memory element 39 is intended for storing the monitoring program and transmitting it through the matching element 40 to blocks 1, 2, 4, 7, 8.1-8, 9 and 9. Element 39 is a 32K memory with a depth of 64K made on the chip K57HRFZ.

The matching element 40 is a standard channel transceiver device with decoders (K559I11 series chips)

The device (Fig. 2) works as follows, I

Pressing the button 41 of the control unit 6 (FIG. 4) starts the pulse generator 37, and the counter 38 selects the addresses of the fixed memory element 39. Through the matching element 40, information about the parameters of the generated tests is stored in the registers of the memory of the nodes and blocks of the device. The register 19 of the 1 clock pulse generator records information about the length of the clock pulse following period, which ensures the specified frequency of the generated tests, and registers 24 and 25 of the pulse conditioners 2.1–2. The information about the delay values and the duration of the pulses generated in the B cells operational

The memory of block 4 specifying the code is entered into the data necessary for the formation of tests (pulse sequences) that are used as input influences for the controlled LSIs, the control inputs of the switch 7 receive information about the sequence of connecting the codes of 2.1-2.t shapers impulses to 5 inputs of drivers 8.1-8. Phase-manipulated signals; registers 11 drivers 8.1-8. P records information about the time ratios of the phase-shifted signals; is information on the implementation of the mode information output from the inversion 8.1-8.p formers. At the end of the process of recording information from the output of block 4, setting the code, the input signal for the element 21 and generator 1 of clock pulses (Fig. 2) receives a permission signal for passing pulses from the output of generator 18

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the frequency to the input of the counter 22, the outputs of the bits of which are set to the n-bit code to the digital comparator 23, where it is compared with the code written in the register 19. With the equal codes, the digital comparator 23 generates a pulse that is fed to the reset input of the counter 22 and an information input of the shift register 20, to the synchronization input of which pulses are received from the generator 18 of the reference frequency. At the output of the shift register 20, clock pulses are generated for block 2 of pulse formers, counter 3 and register 5 of the number. Upon the arrival of a clock pulse from the output of the shift register 20 of generator 1 (Fig. 6q, time t) to the S-input of the trigger 28 and the first input of the element 36 OR block 2 (Fig. 3), each of the 2.1-2.t. pulses in the mode of formation of the leading edge of the pulse (delay). At the same time, at the direct output of the trigger 28, the level of logic I is set, and at the inverse level, O, the Signal 1 is fed to the control

the input of the switch 31, allowing the passage through it of information from the output of the register 24 to the inputs of the digital comparator 32. Upon the arrival of a pulse from the generator 18 of the reference frequency of block 1 to the S input of the trigger 26 and element 35 And the counter 30 is reset and the trigger 27 is set to the state in which 1 is set at its output, arriving at the second input of element 35 and allowing clock pulses from the output of the generator 18 of the reference frequency of block I to the counting input of counter 30 of block 2 (FIG. 1). At the output of the counter 30, a p-bit code is set, which arrives at another group of inputs of the digital comparator 32, where it is compared (code) with the output information of the register 24 passing through the switch 31.

the equality of the codes at the output of the digital comparator 32 forms a pulse that arrives at the first inputs of logic elements 33 and 34 I. Since the second input of element 33 I is set to 1 (from the direct output of the trigger 28), the pulse from the output of digital comparator 32 passes through the element 33 And at the entrance trigger

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ditch 28 and 29 and element 36 OR. In this case, the trigger 28 changes its state, O is set at its direct output, and 1 at the inverse, allowing information to pass through the element 34 And in the mode of forming the trailing edge of the pulse (duration) occurring in the manner described with the difference that, instead of register 24, register 25 is active. The leading and trailing edges of the pulse are fixed by trigger 29. In FIG. 65 and B show the signals at the output of the flip-flops 29 of the driver 2.1, 2.J pulses. The leading edge of the pulse at the output of the imager 2.i is formed at time t with a delay c, and the leading front at the output of the imager 2j is formed at time tj with a delay o-j. The rising edges of these pulses are formed at times t, t, respectively. So about

0

0

at the same time, at the output of the trigger 29 of the driver of 21 pulses, a pulse of duration G is formed at the output of trigger of the driver 29 of generator 2 - a pulse of duration C,. Similarly, at the outputs of the remaining formers 2. 1–2. T pulses are formed with the specified delay and duration values.

From the output of the shift register 20 of the generator I clock pulses (Fig. 2) |. pulses arrive at the input of the counter 3 j

5 (Fig. 1)., Which selects the addresses of the memory cells of the code setting unit 4, the information from the outputs of which is fed to the inputs of the 5th register and the aetiji census by the arrival of clock pulses from the generator 1. The output information of the 5th register. (Fig. 6) from the direct outputs goes to the information inputs of the flip-flops 12 and the element 16 2И5 OR, included in the shapers 8.1-8, n phase-shifted signals. Information from the inverse outputs of register 5 is fed to the element 17 2I-OR. To sync inputs

0 flip-flops 12 and the first inputs of elements 13 of the IC: KSH) CHA1 (ALREADY OR through the switch 7 information passes from the output of the driver 21 pulses, and the first inputs of the elements 14 EXCLUSIVE

OR - information from the output of the imager 2j Ipchpulsov (1 1, j 2).

In the former 8.1-8.p, the formation of pulses occurs, the phase co-former 8,

.

The latter depends on the time position of the signals recorded in registers 11 in the form of codes of numbers.

Let in registers 11 of six shapers 8.1-8.6 of phase-shift keyed signals recorded codes of the following numbers:

000001101

011000000

010000101

101001100

011010100

000100000 At the same time, at the outputs of shapers 8.1-8.6 of phase-shift keyed signals, pulses will be generated, the shape of which is shown in FIG. 6 ,, C ,, l respectively. The pulses from the outputs of the shapers 8.1-8P of the phase-shift keyed signals arrive at the first inputs of the elements 43-1-43.P EXCLUSIVE OR (Fig. 5), the second inputs of which from the outputs of the register bits 42 receive the number code as O or I, previously described from the element of the permanent memory 39 of the control unit 6 and carrying information about the implementation of the inversion mode by the block 9. If the second inputs of the elements 43.1-43, EXCLUSIVE OR are set O, then the information from the outputs of the formers 8-1-8.P phase-shifted signals passes to the output bus of the device without and Menen. Inverting information occurs if the second inputs of the elements 43.1-43, p are set IIIII

As a result, the device provides for the formation of tests that are used as impact signals in the functional control of complex electronic circuits.

Using the device is effective when, as a result of retaining input actions on the control object, for example, a RAM chip, the main elements of this chip, for example, address registers, are as if replaced by elements of the test task device that form the address, As a result, address registers fail

YU

15

20

Thus, when controlling the LSI of the 134RU6 type, there are cases of passage of input actions recorded on the RAM to the outputs of the RAM due to faults inside the LSI, since in this case the output information of the LSI RAM is as expected, the control device qualifies an unsuitable BIS as valid. Faults of this type are detected only when functioning in the application object.

When controlling BIS. RAM types 581RU4 565RUZ, 383КП, etc., with internal memory registers of the row address and column addresses, cases of recognizing the BIS suitable for malfunctioning of the memory register of the row address are observed. This is explained by the fact that the address information of the string specified by the test generation device , from the input bus of the control object passes, mine the internal register, to the output bus, i.e. A substitution of the work 25 of the internal address register of the control object with a number register is carried out; As a result, the evaluation of the performance of the LSI is erroneous.

In addition, the presence of unchanged information on the input bus of the control object during the entire time of monitoring does not allow evaluating the dynamic properties of the input memory registers of objects with a memory of the capacitive type in relation to the storage time of information.

The introduction of 11 formers 8, 1–8, n of phase-manipulated signals makes it possible from the signals received from the outputs of the formers of 2.1 and 2. t pulses and the 5th register to generate pulses whose phase depends on the temporal position of the mentioned signals. This, in

turn, provides a multiple change of information, which is expressed in the alternation of true and false information generated at the output of devices for setting tests. If, in this case, the control object unambiguously repeats the specified test, then we can consider it unsuitable and thus delineate its departure, which is

thirty

35

40

50

The microcircuits (or other elements) are masked by the action of the device, they are cast with a correctly working element of the test setting device, which leads to the absence of a failure and low confidence of the control.

Dani tests, t, e, in the process of monitoring is carried out multiple changes of information, which allows to exclude the influence of the formed tests on the result

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Thus, when controlling the LSI of the 134RU6 type, there are cases of passage of input actions recorded on the RAM to the outputs of the RAM due to faults inside the LSI, since in this case the output information of the LSI RAM is as expected, the control device qualifies an unsuitable BIS as valid. Faults of this type are detected only when functioning in the application object.

When controlling BIS. RAM types 581RU4, 565RUZ, 383КП and others, having internal memory registers of the row address and column addresses, cases of recognizing the BIS suitable for malfunctioning of the memory register of the row address are observed. This is explained by the fact that the address information of the string set by the device test, from the input bus of the control object passes, mine internal register, to the output bus, i.e. A substitution of the work of the internal address register of the object of control with the register of the number included in the device for setting the tests is performed. As a result, the evaluation of the performance of the LSI is erroneous.

In addition, the presence of unchanged information on the input bus of the monitoring object during the entire monitoring time does not allow one to estimate the dynamic properties of the input registers of the memory of objects with a memory of the capacitive type with respect to the storage time of information.

The introduction of 11 formers 8, 1–8, n of phase-manipulated signals makes it possible from the signals received from the outputs of the formers of 2.1 and 2. t pulses and the 5th register to generate pulses whose phase depends on the temporal position of the mentioned signals. This, in

turn, provides a multiple change of information, which is expressed in the alternation of true and false information generated at the output of devices for setting tests. If, in this case, the control object unambiguously repeats the specified test, then we can consider it unsuitable and thus delineate its departure, which is

0

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0

0

The tests, t, e, in the process of control are carried out multiple changes of information, allowing to exclude the influence of the formed tests on the result of the control and thereby to ensure high reliability of control of the functioning of the object under test /

Claims (1)

Claim 5 A device for setting tests containing a register of a number, a generator, clock pulses connected by a first turn to the counting input of a pulse counter, a switch, a code setting unit and a first pulse shaper connected by control inputs to the corresponding control outputs of the control unit, as well as a second pulse shaper and an inversion unit, the outputs of which are outputs of the device, characterized in that, in order to increase the reliability of the control by eliminating the influence of the specified tests on the result control the second output is with the synchronous input of the number register, the third and fourth outputs, respectively, with the third and fourth inputs of all pulse shapers connected to the information inputs of the switch connected to the first outputs of the first inputs of the corresponding phase-shifting signals shapers, the second inputs of which are connected to the corresponding second outputs of the switch , the third inputs - with the corresponding first outputs of the register of the number connected by the second outputs with the quarter inputs corresponding phono-manipulated signals shapers, information inputs — with the first outputs of the code setting block, connected by address inputs to the outputs of a pulse counter, outputs of phase-shifted signals shapers connected to the corresponding first inputs Additional impulse drivers, n form inversion units, connected by second taps of phase-shifted signals inputs with corresponding control- (n - number register size), control unit codes, the fifth input of the second and additional pulse conditioners are connected to the device. with the corresponding control outputs of the control unit, the first inputs of the clock pulse generator are connected to the corresponding control outputs of the control unit. X  the inputs of each of the drivers of the phase-manipulated signals are connected to the corresponding control outputs of the control unit; the second output of the code setting unit is connected to the second input of the pulse generator. YU five 15 20 the second output is with the synchronous input of the number register, the third and fourth outputs, respectively, with the third and fourth inputs of all pulse shapers connected to the information inputs of the switch connected to the first outputs of the first inputs of the corresponding phase-shifting signals shapers, the second inputs of which are connected to the corresponding second outputs of the switch , the third inputs - with the corresponding first outputs of the register of the number connected by the second outputs with the quarter inputs corresponding phono-manipulated signals shapers, information inputs — with the first outputs of the code setting block, connected by address inputs to the outputs of a pulse counter, outputs of phase-shifted signals shapers connected to the corresponding first inputs - an inversion unit connected by the second inputs with the corresponding control codes of the control unit, the fifth inversion unit connected by the second inputs with the corresponding control codes of the control unit, the fifth  the inputs of each of the drivers of the phase-manipulated signals are connected to the corresponding control outputs of the control unit; the second output of the code setting unit is connected to the second input of the pulse generator. srig.1 L 5 / Y c e / r7ViJ / ft / 5 } R duig2 fis.3 I Cffb / xot aS. 8.1 .... 8.YY I I O / rr Syrey / a 6 JN V w mn FIG. 4J.1 / f u / t /// ar4f ffit / 3fo a 45 / Fig 5 r in Well 3 and n l Compiled H, Glaviznina Editor A, Gulko Tehred L. Serdyukova Proofreader. Shekmar Order 7899/44 Circulation 864 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 FS / E.6