SU1183969A1 - Device for checking logical units - Google Patents

Description

The invention relates to automation and computing and can be used to monitor the health of logical nodes and integrated circuits.

The aim of the invention is to increase the speed of the device for different types of controlled logical blocks.

FIG. 1 shows a block diagram of a device for monitoring logical blocks; in fig. 2 - driver circuit; in fig. 3 - diagram of the driver control signals; in fig. 4 is a timing diagram of ¹ device operation.

The device contains a generator, 1 pulse, shaper 2 tests, controlled unit 3, unit 4 storage of standards, comparison circuits, memory elements 6, display elements 7,

blocks 8 fixing of inputs, control unit 9, switch 10, driver 11 control pulses, switch 12, elements 13 AND, keys5 14, element 15 AND, triggers 16, elements AND NOT 17, elements OR 18, elements AND 19, elements NOT 20, two shapers 21 and 22 single pulses, trigger 23, two elements • O AND 24 and 28, counter 25, a decoder of control signals 26 and element OR 27.

The device works on the principle of comparing the input and output signals of two identical blocks of the monitored unit 3 and the unit 4 for storing the standards (Fig. 1). Input signals are fed to the comparison circuit 5 with the driver 2 tests 20 through the elements And 13, blocks 8 fixing the inputs and input pins of the control 3 1 1

unit 3 and unit 4 for storing standards. Their comparison is necessary to detect faults in the controlled unit 3 types of short circuit on the inputs. The output signals arrive at the comparison circuit 5 from the output pins of the monitored unit 3 and the unit 4 for storing the standards. The discrepancy between the values of the outputs of the monitored unit and the unit for storing the standards is memorized by the memory elements 6 and form a fault vector characterizing the location of the faulty element in the monitored unit 3. 15

Switch 12 has two positions: the first one corresponds to the control of logic blocks, the second one - to the control of microcircuits. In the nerve mode, elements AND 13 are opened and 20 keys are closed, which ensures the transmission of test (input) signals from the driver of the 2 tests to the inputs of the monitored unit and the unit for storing the standards. In the second mode, the elements And 13 are closed, but at the same time the keys 14 are opened, which ensures the transmission of input signals from the inputs of the monitored unit 3 to the inputs of the unit 4 for storing the standards. zo

Initially, all memory elements 6, input fixation blocks 8, trigger 23 and counter 25 are set to the "zero" state, which corresponds to the absence of luminescence on the display, closing of keys 14, prohibiting the passage of generator 1 pulses to the driver inputs

2 tests and the prohibition of the impact of the states of the driver shaper 2 tests on the blocks 8 fixing the inputs and the conclusions of the controlled block

3 and block 4 storage standards.

The device works as follows.

Switch 10 starts a single pulse shaper 21 (FIG. 4, and ^), which translates trigger 23 into a “single” state. A high logic level at the output of trigger 23 (FIG. 4, and *) permits the passage of pulses from generator G to counter 25 shaper 11 control pulses. The decoder 26 produces the following control signals.

With a counter condition of 25 equal to "LLC", a high log output is generated; 83969 4

The coaxial level at its inverse output (FIG. 4, and _A ), which, with the “single” state of trigger 23, allows pulses from goner 5 of torus 1 to the counter 25. The high logic level at the inverse output of the decoder 26 remains until the counter 25 is equal to "101 ".

When the counter state 25, rav10 nym "001", the output of the decoder 26 produces a control pulse (Figure 4, and _c) which, proceeding from the third control unit 9 outputs to the third inputs inputs fixing blocks 8, connects the shunt circuit for fixing the output storage unit of standards with open collector outputs.

When the state of the counter 25, equal to "010", the output of the decoder 26 produces a control pulse (figure 4, and _d ), which is supplied from the first output of the control unit 9 to the zeroing inputs of the memory elements 6, setting them to the "zero" state, and to the inputs of zeroing block fixing inputs. For this control pulse, the input latching units 8 determine the inputs and outputs by the conclusions of the standard storage unit 4. The outputs of the monitored node 3 and the standard storage unit 4 are disconnected from counter 2, and the inputs are connected to the corresponding outputs of counter 2 with a variable number of digits.

When the state of the counter 25, equal to "011", the output of the decoder 26 produces a control pulse (Fig. 4 and _d ) which, coming from the third output of the control unit 9 to the third inputs of the input locking blocks 8, disables the output fixation circuit with open collector exits.

When the state of the counter 25, equal to "100", the output of the decoder 26 produces a control pulse (Fig. 4 and _c ), which, coming from the fourth output of the control unit 9 to the installation input of the test driver 2, sets the "zero" state of the trigger 16 of those bits that correspond to the pin numbers defined as inputs for block 4 of storage of standards and controlled block 3.

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When the state of the counter 25, equal to "101", at the output of the decoder

produced control potential (figure 4, and ^), which, slept from the fifth output of the control unit 9 to the second input element And 15, allows the passage of the pulses of the generator 1 to the input of the driver 2 tests, prohibits the passage of these same pulses through the element 24 to the counter 25. The latter stops and its state, equal to '' 101 ", remains unchanged until the completion of the control of the logic block, i.e. before setting the" zero "state of the trigger 23.

Shaper 2 tests works as follows. "

After determining the inputs and outputs in blocks of 8 latching inputs on their third information outputs high or low logic levels appear.

A high logic level at the third outputs of the block 8 fixing inputs appears when fixing the output corresponding to the output of the block 4 storage standards. These logic levels arrive at the information inputs of the test driver 2 and, through elements * HE 20, set the corresponding triggers 16 to a "single" state. At the same time, high logic levels in these bits arrive at the second inputs of the And elements 19, which allows the pulse 1 of the generator to pass through the elements AND 19, OR 18 to the subsequent triggers of the driver 2. A low logic level coming from the elements NOT 20 to the inverse 8-inputs of the triggers 16 firmly "holds" the corresponding triggers 16 in the "single" state ii. Thus, the pulses of the generator 1 does not affect the state of these triggers and through the elements AND 19, OR 18 pass to the subsequent triggers 16 shaper 2 tests.

Low logic level at the third outputs of the block 8 latching inputs corresponds to the definition of the data of the outputs of the block 4 storage standards as inputs. These logical levels arrive at the information inputs of the driver 2, the elements of the KE 20 and the second inputs of the elements And 19,

thus prohibiting the passage of generator 1 pulses through AND 19 elements. A high logic level from the outputs of elements NOT 20 enters the inverse δ-inputs of the trigger 16, thereby allowing the installation of the corresponding triggers in any state through their counting input and in the "zero" state in the inverse To the entrance. The control pulse generated by the control unit 9 is supplied from its fourth output to the counting input of the test driver 2 and to the first inputs of the AND 17 elements. At the second inputs of the AND 17 elements, there is a high logic level. These bits of the driver 2 tests are set by the control pulse (figure 4, and _c ) in the "zero" state. In the bits, which correspond to the "output" pins, there is a prohibiting signal at the second inputs of the AND-NOT elements 17, and the control pulse to the inverse K-inputs of the flip-flops 16 is not received.

In the process of controlling the logical block 3, this control pulse does not appear (FIG. 4, υ _β ), therefore, it does not have any influence on all the discharges.

Thus, the information outputs of the shaper 2 tests, corresponding to the outputs of the reference and controlled blocks, are set to the "single" state and are held in this state during the entire monitoring. Through the elements AND 19, OR 18 creates the possibility of passing the generator pulses to subsequent triggers shaper 2 tests.

The direct outputs of the triggers of the shaper group of 2 tests, corresponding to the inputs of the reference and controlled unit, are set to the "zero" state, and in the further monitoring process they are not fed to their inverse K and 5 inputs. This ensures the normal functioning of the respective triggers 16 on their counting input. Circuit circuit through elements And 19,

OR 18 is closed on the second inputs of the elements And 19, therefore, the data of the trigger 16 remain active.

The final binary combination of test driver 2 will be

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a combination of "III ... I", and the number of digits of this combination will be determined by the number of inputs of the reference and controlled blocks. The next 5-pulse generator 1 sets the driver of 2 tests to the state of "LLC ... O". Therefore, a sign of the end of control of the logic block On all binary combinations of the shaper of 10 2 tests, I am the transition of the last trigger of the shaper group of 2 tests to the "zero" state. The positive front of the transition of this trigger in the "zero" state receives 15 from the second input of the control unit 9 to the input of the single pulse shaper 22 (FIG. 4, D5). Element And 28 is open for the passage of this positive front only when the state of the counter 25 is equal to "101", i.e.

when the inputs are defined and the 2 test driver is tuned. En on the corresponding inputs. Therefore, transients occurring at the initial stage of the device operation do not affect the control unit. A single pulse from the output of the former 22 sets the trigger 23 to the "zero" state, and thus the counter 25 is set to the "LLC" state.

The process of control of the logic block on all combinations of the shaper 2 tests is over. The luminescence of the display elements 7 determines the fault vector characterizing the type and location of the fault. The absence of the glow of the indicators means the health of the logic unit.

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Claims (2)

1. DEVICE FOR THE CONTROL OF LOGICAL BLOCKS, containing a pulse generator, a unit for storing standards, comparison elements, memory elements, keys, display elements, input latching units, a group of elements AND, a control unit containing a decoder of control signals, a counter, the first element I, two switch, and the output of the first element And is connected with the counter input of the counter, the information outputs of which are connected to the information inputs of the decoder of control signals, the first output of which is connected to the inputs of zeroing the input lock blocks and the control inputs of memory elements, the second output of the decoder of control signals, the first contact of the first switch connected to the first inputs of the elements of the group and the first control inputs of the keys, respectively, the second contact of the first switch is connected to bus number of the left potential and the first contact of the second switch, the outputs of the elements And groups are connected respectively to the information inputs of the input latching units, the first information outputs of which are combined respectively with the information inputs of the keys, the first inputs of the comparison elements and the corresponding outputs of the monitored block, the second information outputs input latching blocks are connected to the second inputs of the comparison elements, to the information outputs of the keys and to the corresponding pins of the xp block standards, third information outputs of input locking blocks are connected to second § control inputs of keys, outputs of comparison circuits are connected to information inputs of memory elements, information outputs of which are connected to inputs of corresponding display elements, characterized in that in order to increase device performance for different types controlled blocks, a test driver, two AND elements, two single pulse formers, a trigger, an OR element, and the pulse generator output connected to the first input of the first element And the first input of the second element And the second input of the first element And which is connected to the inverted output of the decoder control signals, the third output of the decoder control signals connected to the input of the test driver, the fourth output of the decoder control signals connected to the second input of the second element And with the first entrance of the third 5C „„ 1183969 1183969 The second element And the output of the second element And is connected to the counting input of the test driver, the information inputs of which are connected to the third information outputs of the input fixation blocks, the information, e outputs of the test driver are connected to the second inputs of the And elements of the group, respectively, the output of the test end of the test driver is connected with the second input of the third element And, the output of which is connected to the input of the first shaper of single pulses, the output of which is connected to the first input of the element OR, the second input of which is connected not the second contact of the second switch, the third contact of which is connected to the input of the second shaper of single "pulses, the output of which is connected to the input of the trigger setup, the reset input of which is connected to the output of the OR element, the direct output of the trigger is connected to the third input of the first And element and to the reset input counter. 2. Device pop. 1, characterized in that the driver, the test contains a group of elements AND, a group of elements AND-NOT, a group elements NOT, a group of elements OR, a group of triggers, the group of information inputs of the driver are connected to the inputs of the elements NOT the groups and with the first inputs of the elements AND groups, the outputs of the elements NOT groups are connected to the inverse inputs of the installation of the group triggers, the second inputs of which are combined with the zeroing input of the driver, the outputs of the elements of the NAND group are connected respectively to the inverse reset inputs of the group triggers, the counting input of the driver is connected to the synchronous input of the first channel ggera group and with a second input of the first AND gate group iversnye outputs of flip-flops are connected to first inputs of OR element group, straight group triggers outputs connected. with information outputs of the former, the second inputs of the OR elements of the group are connected to the outputs of the corresponding AND elements of the group, the output of the ίth element OR is connected to the counting input ΐ + 1th group trigger, the output of the ηth element OR is connected to the output "end of tests" shaper.