SU766053A1 - Majority-redundancy flip-flop - Google Patents

Description

one

The invention relates to computing and impulse technology and can be used to build redundant triggers of conventional reliability. .five

Known redundant trigger containing elements AND, AND-NOT, OR, and three trigger, single outputs of which are connected to the inputs of the majority element, in addition, single output 10 trigger each channel connected.n to one of the inputs of the elements AND-NOT, and OR other channels , the other inputs of the NAND elements of each channel are connected to the outputs of the elements AND of the corresponding 5 channels and, through inverters, to the elements OR 1.

The disadvantages of this redundant trigger are the presence of a common major element for three channels, the failure of which leads to the failure of the entire device, the lack of feedback majority of the memory elements (triggers) and the absence of elements that provide a complete backup trigger. during operation, that if there is no check of e FIX failures in a single three-channel microcorrector element leads to the fact that the device becomes weaker than the reliability of the non-reserved trigger .

A redundant trigger is known, containing in each channel a pgsh block and a two-stage control scheme implemented on AND-NOT, OR-NOT elements, and the zero element of each channel's PSI block is designed as a majority element whose inputs are connected to the outputs of the unit elements of the pLLT block. of all channels, the first stage of the control circuit is performed on the OR element, the output of the first element And the second stage of the control circuit is connected to one of the inputs of the second element And the same stage, the other input of which is connected to one From the inputs of the single element of the memory unit and to the input of the first stage of the control circuit, and the output to the output of the single element of the memory unit, another input is connected to the zero output of trigger 2.

Claims (2)

The disadvantage of this redundant trigger is that it is impossible to carry out a complete check of the functioning of the redundant trigger during its operation in the composition of the blocks and calculator devices. Htoc instrumentation that ultimately reduces its reliability. The purpose of the invention is to demonstrate Reliability by ensuring complete verification of the operation of the device during its operation. To achieve the goal, a major-redundant trigger contains in each channel an AND-OR-NOT element and a major element with an inverse output connected to the output bus and to the first input of the first-valve of the AND-OR-NE element whose second input is connected to the reset bus, the first input of the second valve electrHta AND OR-NOT is connected to the clock bus, its other inputs are connected, respectively, to 1 service buses, and the output of each element R-rfilH-HR- is connected to the corresponding input major element - in each channel The additional inputs of the first and second gates of the AND-OR-NOT element are connected to the unit imitation circuit, the first input of the third gate of the XIOR-NE element is connected to the imitation zero bus, and the second input is connected to the horizontal bus. chheni istatsii. The drawing shows the block diagram of the majority-redundant trigger: pa. The scheme contains in each channel element 1 AND-OR-NOT and major element 2, the output of the major element 2 is connected to the output bus 3 and to the first input of the first valve of the element 1 AND-OR-NOT, the second input of which is connected to the reset bus 4, ne the second input of the second gate of the element 1 is AND-OR-NOT connected to the clock bus 5, the other inputs, respectively, to the condition bus 6, d An additional input of the first and second valves of the element 1 are AND-OR-NOT connected to the 7 imitation units, the first input of the third valve element 1 is AND-OR-NOT connected to the 8 imitation zero, and w Entry to bus 9 imitation resolution. The output of element 1 is AND-OR-NOT of each channel is connected to the corresponding input of the majority element 2 of each channel. The major-redundant ifpurrep works as follows. In the main mode, high-level signals correspond to logic, are sent to buses 7 and 4 and are not present on buses 8 and 9. Information is written to the majority-reset trigger on high-level signals on buses 5, Before recording information on buses 4 and 5, signals are high, not received. At the same time, since at least one input of each valve of the 1 AND-OR-NOT elements is a logical O, the output of the 1 AND-OR-NOT elements is set to a state, and at the outputs of the majologic receptacle elements 2, the state of the logical O, Since the outputs of the major elements 2 are connected to the first inputs of the first valves of the elements 1 AND-OR-NOT, then when a 4-signal logical major-redundant trigger arrives at the buses, the trigger remains in the reset (zero) state. Further, if, when a high signal arrives at the bus, it is missing at least on the orfiJOM of the inputs connected to the bus (M b, the majority-redundant trigger does not change its zero state. But if at the time the logical bus arrives at all the inputs of the second valves elements 1 AND-OR-NOT connected to buses 6 will have high-level signals, then the outputs of the .1 AND-OR-NOT elements will set the state of the logical O, and the outputs of the majority elements 2 will have the state of the logical, while all entrances perk gates element In 1 AND-OR-NOT, signals appear logically, the majority-redundant trigger is set to one, and if in any channel the signal of logic i on bus 4 does not disappear, and on buses 5 and 6 there are no high-level signals due to equipment failures, or if there are corresponding failures on the inputs of element 1 AND-IL11g-NOT, triggers (elements 2 of memory) in each channel of the device store the same info | ation. If any element 1 AND-OR-NOT fails, such as an open-circuit failure, the trigger (memory element) of this channel is inoperable, but on all output buses 3 the information is true. If any major element fails at the output. Iqy, the device will function, since the information on the two other output buses 3 will be exceeded. In the mode of automatic testing (for example, using tests) of devices, the components of which are majority-redundant triggers, the full functionality of the elements of the majority-redundant trigger as well as the main equipment generating signals arriving at buses 4-6 is determined follow the way. During the entire time of the test, the tire 9 receives a signal that the test is carried out in three stages. At the first stage, in the first channel on bus 8 and on bus 7, the signal is logical O, therefore, regardless of the state at the other inputs of element 1, AND-OR-NOT at the output of element 1, AND-OR-NOT in the perd channel and at the corresponding inputs of the majority ElementJEv 2; the state of Logic 1 is set, the signal of the logic channel is sent to the bus 8 in the second channel, therefore, regardless of the state at the inputs of the first and second valves of the element 1, AND-OR-NOT at its output and at the corresponding inputs; logical O, the third channel of the device operates in the main operation mode and at the output of element 1 H-OR-NOT the state is determined by signals on buses 4 6, Thus, the state on the code of all major elements 2 is determined by signals on buses 4- 6 thr At the same time, if at the output of element 1 AND-OR-NOT in the third channel the state of logical 0 is set by test, then analyzing the state of the outputs of the majority elements 2, failures of type 06 are detected at the outputs of elements 1 AND-ILINE in the second and third channels and inputs of the major elements 2, connected to these outputs, as well as in the elements connected to bus 8 in the first and third channels, and failures of the type Short sticking to the elements connected to tires 4-7 in the third channel-. If on the 1-AND-OR-NO element 1 in the third channel the state is logical, then, analyzing the state of the outputs of the major elements 2, failures of the type Short circuit at the outputs of the elements 1 AND-ILY-NE in the first and third channels are detected and at the inputs of the majority elements 2 connected to them, as well as in e-mails connected to bus 8 in the second channel, and failures of Obfoas type in elements connected to buses 4 - 6 and 6 in the third channel and in elements connected to bus 8 in the first channel. When checking the operation of the device in this mode, the test of the test is set in such a way that the code of Running Zero, i.e. A logical O signal arrives at any input if there are logic signals at the other inputs of the valve. Thus, at the output of element 1 AND-OR-NOT in the first channel, the state of logical 1 in the second channel is the state and control of the majority of bodies. The state of the output of the element I AND-OR-NOT of the third channel is detected. Type Open and Type Short Circuit by analyzing the states at the corresponding inputs and outputs of the device elements. On the second test etrap, all of the above for the first channel occurs in the second channel, for the second channel — in the third, and for the third channel — in the first. At the third stage of testing, the above described for testing at the first stage for the first channel occurs in the third channel, for the second channel - in the first channel, and for the third channel - in the second channel. Thus, from each channel, alternately to the inputs of the majority element 2 elements are simulated O, to the test function, which ensures a complete check of all the elements of the device and the elements of the devices that set the signals / that go to the buses 4-9. In addition, with certain types of failures of elements 1 AND-OR-NOT in two channels, and for any types of failures, elements 1 AND-OR-NOT in two channels, and for any types of failures, devices that give signals to buses 4 - 6 in two channels The majority-backup trigger functions normally, since using the signals on buses 7-9, it is tuned to the remaining healthy channel, while the majority-backup trigger functions as described for the first stage of the verification mode. As the analysis and calculations showed, this major-redundant trigger allows, firstly, to provide 100% verification of the device without direct access to the elements of the device and, secondly, in the presence of a multitude of various failures in two channels, to reorganize the device from a serviceable channel and outputting to one hundred to all, outputs of true information, while its reliability approaches the value of Р + - Р) + ЗРх (1 - Р) versus the reliability of the known equal Р ЗР (1 - Р), where Р is the reliability of one channel. In addition, it should be noted that tires 8 and 9 duplicate each other by the presence of a logical O signal. Duplication is due to the fact that according to statistics, failures of the type Open for many classes of elements constitute 90 - 95% of all failures, and Obrish for these elements is similar to the logical signal. I The invention formula Major-redundant trigger containing in each channel the AND-OR element -NOT and a main part with inverse output connected to the output bus and to the first input of the first gate of the AND-OR-NO element whose second input is connected to the reset bus, while this is the first input of the second valve of the AND-OR-NOT element to the clock bus, its other inputs are connected, respectively, to the conditions bus, and the output of each AND-OR-NOT element is connected to the corresponding input of each major element, which is different By the fact that, in order to increase reliability by ensuring full testing of the device's operation during its operation, in each channel the additional inputs of the first and second valves of the AND-OR-NOT element are connected to the unit simulation bus, the first: the third input of the AND-ILINE element is connected to bus imitation zeros, and the second input is to the imitation bus. Sources of information taken into account in the examination 1. Copyright sovdetstvo USSR 387528, cl. H 03 K 21/00 1970. 2. USSR author's certificate 375824, cl. H 05 K 10/00 1970. channel o channel i canon