SU1141414A1 - Device for checking digital units - Google Patents

Abstract

1. DEVICE FOR CONTROL OF DIGITAL KNOTES, containing a clock generator, the first AND element, OR elements, a counter, a bit comparison unit, a group of 2 meters (where VI is the number of outputs of the tested node), I fault identification block, a decoder, and outputs the counter is connected respectively to the inputs of the tested node, the output of the fault identification block is connected to the control input of the clock generator, the outputs of the bit comparison block are connected respectively to the inputs of the decoder, characterized in that The purpose of checking the accuracy of the control, the second element AND, the element NOT, the pulse shaper, two registers, two memory blocks, the AND-NOT element are entered into the device, the installation input of the device is connected to the installation input of the counter, the installation inputs of the group counters, the counting input the counter is connected to the clock of the first element And, the first input of which is connected to the output of the clock generator and to the input of the element NOT, the output of which is connected to the first input of the second element And, the second input of which is connected to the output of the first memory block, the group of control inputs of which is connected to the outputs of the counter, the group of control inputs of the second,: memory memory and the inputs of the AND-NOT element, the output of which is connected to the second input of the first AND element and is the output of the device , the group of outputs of the second memory block is connected to the group of information inputs of the first register, the group of outputs of the tested node is connected to the group of information inputs of the second register, the control inputs of the first and second registers are connected to the output of the generator (L l pulse, the input of which is connected to the output of the second element I, the outputs of the first and second registers are connected respectively to the first and second groups of inputs of the block of this comparison, the outputs of the devifrater are connected respectively to the counting inputs of the counters of the group and to the inputs of the elements OR, the output of which is connected to the control input of the malfunction identification unit, the groups of the formation inputs of which are connected to the outputs of the counters of the group, the group of alarms of the malfunction identification block is a group Exit devices. 2. The device POP.1, characterized in that, the block identification of faults contains 2 groups of two elements And,

Description

information inputs of the block, the output group of which is connected to the outputs from the first through (P-1) -th decoder, the input groups of which are connected respectively to the output groups of the corresponding comparison node, the outputs of the elements AND of each group are connected to the inputs of the corresponding comparison node and to the control inputs corresponding switch14

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Torah. The group of information inputs of each switch is connected to the output group of the corresponding comparison node, the control input of the block is connected to the second inputs of elements And groups, the outputs of the switches are connected respectively to the inputs of the (2 + 1) -th comparison node, the last output of the depot / ifrator is the output of the block .

The invention relates to automation and computing and can be used to diagnose faults in logic blocks. A device for control is known: integrated circuits containing a reference integrated circuit, buffer elements, a comparator unit, an indi block, a terminal status selector integrated cxei "B i, a test stop decoder, the outputs of the buffer elements connected to the inputs of the reference integrated circuit, with the first group the inputs of the comparison unit and with the group of information inputs of the deactivation condition stop conditions, the outputs of the reference microcircuit are connected to the second group of inputs of the comparison unit whose output is the first control input A test stopping conditions controller, with a control input of the display unit, the outputs of which are connected to the outputs of the buffer elements and inputs of the selector of the output states of the integrated circuit, the output of which is the second control of the decoder input of the test stop conditions, the output of which is the device output , a group of inputs which is connected to the inputs-buffer elements. This device is intended for checking the functioning and diagnostics of malfunctions of computing equipment and automation. The device provides the ability to stop the test (with fixation of the state of the object) directly in the tact in which the difference between the output signals of the controlled and reference circuits ij is detected. However, the analysis of the tests and the behavior of these circuits is carried out by observing the state of their outputs by the operator, which does not allow the use of this device for the automated monitoring and diagnostics of logic circuits, and, as a result, slows down the diagnostic process. The closest in technical essence to the proposed invention is a device for diagnosing faults in logic circuits, comprising a clock generator, a pulse counter, a syndrome calculator, a decoder, OR elements, fault counters, an AND element, and a fault identification unit, the output of the clock generator connected to the input the pulse counter, the outputs of the reference and the diagnosed circuits are connected to the decoder via the syndrome calculation blocks, the inputs of the fault identification block are connected to the output and fault counters, the inputs of which are connected to the corresponding output of the decoder through the OR elements, prohibiting the output of the fault identification block are connected to the input of the clock generator, the counter outputs are connected to the inputs of the And element whose output is connected to the control input of the fault identification block and to the control input of the clock identifier generator. This device automates the process of diagnosing logic circuits 2j. . The known device has insufficient accuracy of the control results, since it allows fixing the malfunction of the controlled logic circuit only under the conditions of the correctness of the tests used and the good condition of the reference circuit. These conditions are not always satisfied in practice and therefore, in order to diagnose malfunctions of logic circuits in objects, it is necessary to check both the correctness of the test and the operability of the reference circuit. Such a need arises, for example, when the device detects a difference in the output signals of the monitored and the reference circuit. If the sequence of input signals of the monitored circuit is correct, then this difference is possible even if it is completely in good condition, it controls my circuit and is the result of the ambiguous behavior of both circuits due to the spread of its own delays in their elements. The known device does not have the ability to test the test, which makes it difficult to detect many malfunctions of logic circuits, which especially reduces the reliability of diagnostics of complex logic circuits. The purpose of the invention is to increase the monitoring accuracy. The goal is achieved that a device for controlling digital nodes containing a clock generator, the first AND element, the OR element, a counter, a unit of comparison, a group of 2 counters (where c is the number of outputs the tested node), the fault identification block, the decoder, the counter outputs are connected respectively to the inputs of the tested node, the fault identification block output is connected to the control input of the clock generator, the bits of the block Comparison is connected respectively to the inputs of the decoder, the second element AND, the element -NE, pulse shaper, two registers, two memory blocks, the AND-NOT element are entered, the device installation input is connected to the installation input of the counter, the installation inputs of the group counters, the counter input of the counter is connected to the output of the first element And, the first input of which is connected to the output of the clock generator and to the input of the element NOT, the output of which is connected to the first input of the second element And, the second input of which is connected to the output of the first a memory block, the group of control inputs of which is connected to the outputs of the counter, a group of control inputs of the second memory block and the inputs of the AND-NOT element whose output is connected to the second input of the first element AND is the output of the device; the group of outputs of the second block memory connected to the group. the information inputs of the first register, the group of outputs of the tested node are connected to the group of information inputs of the second register, the control inputs of the first and second registers are connected to the output of the pulse shaper, whose input is connected to the output of the second element And, the outputs of the first and second registers are connected respectively to the first and the second group of inputs of the block is. bit comparison, the outputs of the decoder are connected respectively to the counting inputs of the group counters and to the inputs of the OR element, the output of which is connected to the control input of the fault identification block, groups of information inputs of which are connected to the outputs of the counter counters, the group of outputs of the failure identification block is a group of outputs of the device. The fault identification block contains 2 groups of two elements each, And, () comparison nodes, 2 switches, a decipheror, the first inputs of the elements AND the corresponding group are the corresponding group of information inputs of the block, the output group of which is connected to the outputs from the first to (F) 1) -th decoder, the groups of inputs of which are connected respectively to the groups of outputs of the corresponding node craw-. The outputs of the elements AND of each group are connected to the inputs of the corresponding switch, the group in-. The formation inputs of each switch are connected to the output group of the corresponding comparison node, the control input of the block is connected to the second inputs of the elements AND groups. the outputs of the switches are connected respectively to the inputs of the (2 + 1) -th comparison node, the last output of the decoder is the output of the block. FIG. 1 shows a functional diagram of the device; in fig. 2 implementation of the identification block of faults. The device contains a clock generator 1, element 2, counter 3, element 4, element 5, memory block 6, element NE-7, pulse generator 8, memory block 9, node 10 to be checked, register 11, register 12, unit 13 for comparison, decoder 14, element OR 15, device installation input 16, meter counters 17, fault identification unit 18, device 19. Fault identification block 18 (Fig. 2) contains AND elements of 20 groups, comparison nodes 21, commutators 22, decoder 23. The device operates as follows. Through installation input 16, the device is reset. At the outputs of counter 3 and group 17 counters, a combination identical to zero appears. At the output of the NAND 7 element, a signal of the logical unit appears, which is fed to the input of the And 2 element, and impulses from the clock generator 1 pass to the input of the counter 3, simultaneously a pulse from the clock generator pos. It goes to the input element HE 4 and in order to avoid false triggering (at the time of changing the data at the counter output) the output element AND 5 will be a logical zero. This time is determined by the transient of the counter and is provided by the pulse duration from the clock. The clock generator 1 and the counter specify a sequence of binary combinations, which are input actions for blocks 6 and 9 of the memory and for the tested node 10. These input combinations in de addresses go to blocks 6 and In block 6 of the memory the addresses of forbidden combinations are stored. If the input action is correct, a signal appears at the output of the bat 6, corresponding to the level of the unit, which is supplied through element 5 to the pulse shaper 8. The pulse driver circuit is designed in such a way that it converts a signal into a pulse of a certain duration. This pulse arrives at the control input of the flip-flops 11 and 12. During this time, a binary combination is formed at the information inputs of the first and second registers, respectively, from the outputs of memory block 9 and the tested node 10. With the arrival of a pulse at the control inputs of the registers at the output of register 11 reference output combinations are stored, which are stored in block 9 and are functions of input effects, while at the output of register 12 there is an output combination from the tested node 10, which is also a function of input effects, but may have any possible values determined by the nature of single faults in the diagnosed circuit. The resulting binary combination enters block 18. The information from block 13 goes to decoder 14, each output of which corresponds to one number from the set of possible malfunctions of the tested node. However, there are situations when different faults result in the appearance of C at the output of the tested node with identical error sequences. The proposed device allows diagnosing such faults. The decoder signals are distributed to counters (faults), each of which is assigned to one of the faults. The contents of the counters are fed to the input of the block 18 identification of faults. In the case of the occurrence of a signal at the input of any counter from the code of the element OR 15, a comparison resolution signal is received at the control input of the fault identification unit 13. The circuit block 18 may be implemented on the basis of the microprocessor. Consider the operation of block 18 in accordance with FIG. 2. With the arrival of the control signal at the inputs of elements AND 20, the code sequence from the outputs of the counters goes in pairs (from each pair of counters) to the corresponding comparison node 21. At one of the outputs of the comparison node, a signal appears indicating which of the multi-digit numbers is greater, or indicating their equality. The output combination of the comparison node is the address input of the corresponding commutator 22, which connects to its output a larger value, and in the case of equality of numbers, any (predetermined) one of them. The circuit is built on the iiramidal principle. From the outputs of the switches, the data gets to the (2 + 1) -th comparison node. At the same time, the outputs of the comparison nodes are connected to the corresponding inputs of the decoder 23, through which the indication of the type of fault can be indicated. The equality output of the (2 +1) -th comparison node is; control: for the decoder and allows the indication of the type of fault, if any. . If the test action from the output of the counter 3 (pulses) is incorrect, a single signal at the output of memory block 6 does not appear, and information from the outputs of the tested node 10 and memory block 9 is not received at block 18. In the absence of a malfunction, the check continues until a single combination appears at the outputs of the counter (pulses), which enters the input of an AND-NE element 7, at the output of which a logical zero signal appears, which enters the input of the AND element. 2, impeding the passage of pulses from the clock of the generator 1 to the counter 3 (pulses), a simultaneously zero signal arrives at the output 19 of the device, signaling the end of the test. An introduction to the proposed device of the memory block 6 makes it possible to verify the tests for correctness, which, along with the reference signal of the memory block 9, reduced as the generator of the reference signal, significantly increases the reliability of the control due to the decrease in the probability of occurrence of errors of the first kind, i.e. the likelihood of declaring valid schemes worthless. The use of the device allows the verification of logical nodes with an increased degree of integration.

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Claims (2)

1. DEVICE FOR DIGITAL CONTROL UNITS, comprising a clock generator, the first AND gate, OR elements, counter, bitwise comparison, block, a group of 2 ^minutes counters (wherein And is the number of outputs of the checked node), ι the fault identification block, the decoder, 'the outputs of the counter connected respectively to the inputs of the checked node, the output of the fault identification block connected to the control input of the clock generator, the outputs of the bitwise comparison block connected respectively to the inputs of the decoder, which differs that, in order to increase the reliability of control, the second element And, the element is introduced into the device NOT, pulse shaper, two registers, two memory blocks, AND element, and the installation input of the device is connected to the installation input of the counter, with the installation inputs of the group counters, the counter input of the counter is connected to the output of the first element And, the first input of which is connected to the clock output generator and with the input of the element NOT, the output of which is connected to the first input of the second element AND, the second input of which is connected to. the output of the first memory block, the group of control inputs of which are connected to the outputs of the counter, with the group of control inputs of the second memory latch and the inputs of the AND-NOT element, the output of which is connected to the second input of the first AND element and is the output of the device, the group of outputs of the second memory block is connected with the group of information inputs of the first register, the group of outputs of the checked node is connected to the group of information inputs of the second register, the control inputs of the first and second register-5 ditches are connected to the output of the shaper pulse whose input is connected to the output of the second AND element, the outputs of the first and second registers are connected respectively to the first and second corpse of the inputs of the bitwise comparison unit, the decoder outputs are connected 'respectively to the counting inputs of the group counters and to the inputs of the elements OR, Output which is connected to the control input of the fault identification unit, the group of information inputs of which are connected to the outputs of the group counters, the output group of the fault identification unit is a group of outputs. devices. 2. Device pop. 1, characterized in that the fault identification unit contains 2 'groups of two And elements, (2 +1) comparison nodes, 2 ° switches, a decoder, and the first AND elements of the corresponding group are the corresponding group THREADS 1141414 information inputs of the block, the group of outputs of which is connected to the outputs from the first to (n-1) th decoder, the groups of inputs of which are connected respectively with the groups of outputs of the corresponding comparison node, the outputs of the elements of each group are connected to the inputs of the corresponding comparison node and to the control inputs corresponding switch, the group of information inputs of each switch is connected to the group of outputs of the corresponding comparison node, the control input of the block is connected to the second inputs of elements AND groups, outputs switches are connected respectively to the inputs of the (2 ^g '+ 1) th comparison node,. The last output of the dep / emitter is the output of the block.