SU785891A1 - Radio signal simulator - Google Patents

Description

(54) RADIO SIMULATOR

one

This invention relates to radio signal simulators and can be used in radionavigation equipment simulators.

A radio signal simulator is known, comprising a master oscillator which, through series-connected time generator, a waveform converter and a filtering unit, is connected to an output signal unit, a control unit and a carrier frequency generator associated with waveform converter 1.

The disadvantage of the known simulator is the low efficiency of signal simulation.

The aim of the invention is to increase the efficiency of signal imitation.

The goal is achieved by the fact that the simulator has a logical switching unit and an information register, while the master oscillator is also connected to a logical switching unit, which is connected to a waveform converter via an information register.

FIG. Figure 1 shows the simulator structure; in fig. 2 - the schedule of operation of the waveform converter; in fig. 3 is a diagram of one of the possible implementation options for the simulator nodes.

The simulator contains a master oscillator 1, a shaper 2 timing diagrams, a waveform converter 3, a carrier frequency generator 4, a filtering unit 5, an output signal unit 6, a control unit 7, a logic switching unit 8, AND-NE logic elements 9, an information register 10, bits 11 of the register, made on the elements of AND-NOT, a group of 12 clock pulses of the forward stroke, a busbar group of 13 clock pulses of the reverse stroke, key circuits 14, current-supplying resistor 15, output transformer 16 and the unit 17 for setting zero.

The simulator works as follows.

The signal of the master oscillator 1 is fed to the shaper of 2 time diagrams, from the output of the latter to the converter 3, pulses are sent, the sequence of which corresponds to the timing diagram - the order of the sequence (the pulse format of the simulated signal.

Upon receipt of the next pulse from the imaging unit 2 to the converter 3

the latter begins to form the leading edge of the simulated signal, converting the input video impulse into a pulse signal, the leading edge of which varies according to the required law (from time to to time ti in Fig. 2). The signal can be both radio pulse and video pulse. The formation is carried out by a sequential stepwise change — the instantaneous values of the output signal of converter 3 increase at successive moments of time set by the clock signal of generator 1, coming through block 8 to one of the clock inputs of converter 3. When the time tt is reached, i.e. forming the leading edge, from the auxiliary output of the converter 3, the control input of the block 8 receives a control signal, the latter is activated and switches the clock signal g generator 1 to another clock input of converter 3. After that, the operating mode of converter 3 is reversed and the back front of the simulated signal is formed, and a sequential step change occurs - decreasing the instantaneous values of the output signal of converter 3 from time ti to time tj (Fig. 2 ). Due to the reversible mode of operation, the law of variation of the instantaneous values of the signal at the trailing edge of the pulse corresponds to the law adopted for the leading edge, and the simulated signal turns out to be symmetrical about the midpoint of the pulse, i.e., relative to time ti (Fig. 2).

The signal generated by the converter 3 is fed to the filtering unit 5 and further to the output signal block 6.

Since the laws of signal change at the leading and trailing fronts are identical, they are specified in converter 3 by the same converter elements, therefore, with its reversible mode of operation, the number of elements defining the waveform is reduced by half compared to the normal conversion mode.

Block 8 can be implemented both on electromechanical elements, and on logic elements and on microchips.

The required operating mode of converter 3 can be provided when building a converter based on a reversible counter or register whose structures are well known.

When constructing converter 3 on the basis of a counting register on logic elements, the amount of equipment of converter 3 can be reduced due to the structure of the register. An example of one of the possible options for the implementation of device nodes using the elements AND-NOT is shown in FIG. 3

The following scheme works (Fig. 3) as follows.

Tires of 12 clock pulses of the forward stroke are fed through block 8 to clock pulses, as the clock pulses arrive, bits 11 of register 10 are triggered, at the outputs of the first (left according to the diagram) shoulders of bits 11, single signals are set sequentially from the first bit to the last these signals are sent to the key circuit .14, to the second inputs

0 which receives pulse signals from the generator 4 of the carrier frequency. From the key circuits 14, the pulse signals are fed through the casing resistors 15 to the output transformer 16. The latter acts as an accumulator of current signals defined by the resistors 15, an output signal is generated at its output, the carrier frequency of which is set by the generator 4, and the amplitude increases 14, with the increment law being determined by the values of the resistors 15.

After the last bit 11 of the register 10 has been triggered, i.e. when all the bits have been set to one, the control signal from it goes to block 8, which turns off, the clock pulses

 groups of 12 forward runs for a group of backstop tires 13, from which the clock pulses arrive at the inputs of the logic circuits of the second arms of bits 11 of register 10. The bits of the information register 10 are j, start to switch to the initial zero state sequentially from the last to the first on the other hand, when the sequential, but in reverse order, deactivation of the key circuits 14 occurs while the amplitude of the output signal decreases; The law of changing the trailing edge is symmetric to the law of changing the leading edge of the signal. After the transition of the first register bit to the initial state, the signal from it enters the block 17, which forms the zero setting signal, with which the converter 3 is brought to the initial state. The circuit is ready to receive the next pulse.

The generated signal is supplied to the filtering unit 5 and further to the output signal unit 6.

5 The information register can be both single-touch, push-pull and even multi-tact, it does not matter in principle and affects only the number of buses of clock pulses and the formation of clock pulses for the register, and it can be attributed to the register structure or to the logic block 8 switch. The proposed simulator increases the efficiency of signal imitation by forming a signal symmetrical with respect to ces of the pulse,

In the proposed embodiment, a register is used that provides a reverse conversion mode with a reduced number of elements in the register itself about 1.5 times smaller than when implementing a reverse register with controllable links in each bit.

Claims (1)

Invention Formula A radio signal simulator containing a master oscillator, which, after properly connected time generator, a waveform converter and a filtering unit, is connected to the output signal unit, the control unit and a carrier frequency generator associated with a waveform converter, characterized in that, in order to increase the efficiency of signal imitation, it has a logical switching unit and an information register, with STOM the master oscillator is also connected to a logical switching unit, which is connected to the information register waveform converter. Sources of information taken into account in the examination 1. USSR author's certificate in application No. 2359679/12, cl. G 09 B 9/00, 1976 (prototype). 7 IG Output to the block From the block. four