SU818021A1 - Repetition rate scaler with fractional division coefficient - Google Patents

Description

The invention relates to a pulse technique and can be used to build digital frequency synthesizers and formative _; time intervals.

A device for dividing the pulse repetition rate, containing counting / 5 decadal, AND, OR, controlled / integer divider [1].

A disadvantage of the known device is the low speed.

The closest in technical essence to the proposed one is a pulse frequency divider with a fractional variable division coefficient, comprising a ten-day frequency divider with a constant division coefficient, performed on counting decades, selection matrices J $ coefficients, fixing circuit and pulse shaper, decades of tenths and hundredths fractions of a division coefficient, a block of a shift of coefficients, a transfer block, and a coincidence block, while the inputs of decades of hundredths of a fraction of a division coefficient are connected to the output, and decades of tenths fractions of the coefficient de-; the input of which is connected to the output of the pulse shaper, the outputs of decades of tenths and hundredths of a division factor through logic blocks are connected to shift units, a decade of units is connected via a shift unit by one to the output of a shift unit of coefficients of a decade of tenths, and between a decade of units and subsequent decades a frequency divider with a constant division factor included an additional logical transfer circuit [2], The known device has an increased speed, but its disadvantage is the complex native division ratio control circuit and the inability remote dividing ratio ..

The purpose of the invention is the expansion of functionality while simplifying it.

The goal is achieved by the fact that a pulse divider of the pulse repetition rate with a fractional division coefficient contains counting decades of units, tens, hundreds, tenths and hundredths of a division coefficient, units of shift units, tenths and hundredths of a fraction of a division coefficient, the transfer unit / first input of which is connected with the output of the counting decade of units, the second output with the first output of the counting unit of tens, and the first output with the counting input of the counting decade of tens, the first output of which is connected to the counting input of the counting decade of hundreds, and the latching block, the output to of which 5 is connected to the counting input of a countable decade of tenths of a division factor, the first output of which is connected to a counting input of a counting decade of hundredths of a division coefficient, zeroing block, decoders, shift triggers of tenths and hundredths of a division coefficient, blocks are introduced control the shift of units and tenths of the division coefficient, multiplexers and an inverter whose input is connected to the input bus, the first input of the latching unit and the third input of the transfer unit, and the output of the counting input of the counting decade of units and the first input an ode to the odnul unit, the second, third and fourth inputs of which are connected to the corresponding inputs of the fixation unit and the outputs of the corresponding multiplexers, the first input of the first of which is connected to the second output of the transfer unit is an information input with the second output of the unit shift unit, the first inputs of the second and third multiplexers - the second output counting decades tens and hundreds, and ²⁵ data inputs - with the bus control, the output unit is connected to the reset inputs of setting counting decades to zero units, tens and hundreds, and the second outputs of decades of tenths and hundredths of 30 divisions are connected to the inputs of the corresponding decoders and code inputs of the corresponding multiplexers, the information inputs of which are connected to the first outputs of the corresponding shift blocks, and the outputs to the 35 first inputs of the corresponding shift triggers, the second inputs of which are connected to the outputs of the corresponding decoders, while the output of the shift trigger of tenths of the division coefficient is connected to the first input of the unit for controlling the shift of ⁴⁰ units, the stroke of which is connected to the first input of the unit shift unit, the second input of the unit shift control unit is connected to the first input of the shift control unit of tenths of the division coefficient and the output of the shift trigger of hundredths of the division coefficient, the third input - with the second output of the shift unit of tenths of the coefficient division, the first input of which is connected to the output of the shift control unit of tenths of a division coefficient, 50 the second input of which is connected to the second output of the shift block of hundredths of a division coefficient, and the second the moves of the units of the shift units, tenths and hundredths of the division coefficient are connected to the control buses. ⁵⁵

The drawing shows a structural electrical circuit of a pulse frequency divider.

It contains counting decades of 1–5 units of tens, hundreds, tenths and hundredths of a division coefficient, multiplexers 6–10, blocks 11–13 of shifting units, tenths and hundredths of a division coefficient, a fixing block 14, a zeroing block 15, a transfer block 16, triggers 17 and 18 of the shift of tenths and hundredths of a division factor, blocks for controlling the shift of units and tenths of a division factor, inverters 21, decryptors 22 and 23 of zero counting decades, input bus 24, output 25 bus, output 26 counting hundredths fraction of the division ratio, bus 27 control SD a whig of hundredths, an output bus 28 of a trigger of thousandths of a division ratio, control buses 29-33.

Consider the operation of the device on the example of the implementation of the coefficient with two fractional bits ^{p 0} 10 loo

U) where K ₀ , K _t , Ki. - the whole part, tenths, hundredths of a division coefficient, respectively.

To obtain K _tp, it is necessary to obtain the coefficient (Ko + - ¹ ^ -) Κι times, and the coefficient (KoH——) - (100-Κι) times, i.e. in a hundred counting cycles, it is necessary to change the coefficient from To + —-- to

Ko (change the program of tenths from K ₄ to K / + 1).

With an integer division coefficient, a shift per unit division coefficient of the counting decade 1 does not occur.

The divider works in this case as follows.

In the initial state, on the bus 24 of the divider there is a low level of the input signal F _o . All counting decades of the divider are in the zero state (0000). High level signals are sent to buses 31-33, which specify units, tens and hundreds of divisor ratios, respectively. Low level signals are sent to buses 29 and 30, which prohibit the installation of hundredths and tenths, respectively, of the divisor division factor. Bus 25 has a low signal strength. A pulse sequence (high input signal level) with a repetition period T _о continuously arrives from bus 24 to the first input of block 14 and through the inverter 21 to the counting input of counting decade 1 and the first input of block 15. All counting decades 1-5 work in code 8— 4-2-1. The outputs of each counting decade are connected to the coding inputs (code input) of the corresponding multiplexer, with the exception of the outputs, the counting decade of units in which the outputs with a binary weight of 2 ° and 2 ^{2 are} directly connected to the coding inputs of the multiplexer of units of the division coefficient, and the outputs of the counting decade of units with a binary weight of 2 'and 2 ^3, soya818021 are dinamized through block 16 with the coding inputs of the units multiplexer, respectively. Signal A on bus 25 appears with a high level at time instants defined by the following general logic equation:

where l

BUT)

- a symbol * of the logical product of the output signals of multiplexers of units, tens, etc. division ratio;

- output signal j-ro multiplexer;

~ divider multiplexer number.

To perform division with a fractional division coefficient, the divider counts the division cycles (a multiple of ten) and performs a shift per unit of the division coefficient set at the information input n ^e j of the multiplexer

6. The counting of the cycles is carried out by counting decades 4 and 5. A shift of 1 by one is carried out ^ block 11 Zero decoders give an output signal when the state of the counting decades is 0000, multiplexers 9 and 10 with states at the coding inputs corresponding to the information inputs n ^ and n'J · . In the general case, the divisor contains j (j = 0, -1,.,., - βο), shift groups of interconnected devices 4, 9, 12, 17, 20, and 22, and the number of shift groups is equal to the number of digits of the decimal fraction. The shift control scheme in general is described by the generalized logical equation ^ = τ _1Λ ιν т, _рхх / where is the output signal of the shift control unit of the jth group of the shift - ^{Г £} О

Tg ^ -1 is the output signal of the shift trigger (j - 1) of the shift group; the output of the shift trigger (j-2) of the shift group;

- input of unit 9 (j — 1) of the shift group;

i (j = 0, is the number of the shift group;

2-O-group of shift units of coefficient, division factor;

J -1-group shift of tenths of a division factor, etc. The shear control circuit controls the corresponding shear unit, the output signal of which is described by the logical equation where X | and X. \ ₅

-inputs i and (i + Ι) of setting j-oro shift unit per unit fractional fraction of the division coefficient;

- 0, -1, ...- "in

A feature of multiplexers 7, 8, etc. is that their information inputs are direct installation inputs of tens, hundreds, etc. division ratio. When obtaining division factors with fractions, when the number of units is 9 (at X ° ₉ there is a high signal level), block II, under the influence of the signal of the corresponding block 19, supplies a control signal to the information input at ° _{0 of} multiplexer 6, which leads to a false working divider mode, because the counting decade has the largest binary code 1001. In order to avoid errors in this situation (when the number of units is set to 9 and it is necessary to increase the fractionality, 10 increase the coefficient per unit in certain counting cycles, i.e., receive 10), block 16 has been introduced, which delays for one period of completion That filling of the counting decade 2 and forms the binary vector 1010 corresponding to the information input n, ₀ at the input of the code mul _{15 of} tiplexer 6. Consequently, during the operation of the divider, the control signal n? the information inputs of the multiplexer 6 is fed a high level to one of 11 inputs, i.e. 1 = 0, ..., 10, 20 and the information inputs of the remaining multiplexers are supplied with their own control signal n ^ high level to one of 10 inputs, i.e. 1 = 0, ..., 9.

In general, the division coefficient of the proposed divider is determined from the arithmetic ^{25 of the} metic expression.

_n "> ·

The last formula is valid for all values of Ker Ker and characterizes the range of variation of the division coefficient of the divisor.

Claims (2)

(54) THE DIVIDER OF THE PULSE OF THE PULSE OF A PULSE WITH A CROSS-FACTOR OF DIVISION of the counting decade of units, the second input is with the first output of the unit shift unit, and the first output is with the counting input of counting decade of ten, the first output of which is connected to the counting input of the counting decade of hundreds, and block fixing, the output of which is connected to the counting input of the counting decade, the tenth fractions of the division coefficient, the first output of which is connected to the counting input of the counting decade, the hundredths of the division factor, a nulling unit, decoders, shift triggers are introduced tenths and hundredths of a division factor, units of control of units and tenths of a division factor, multiplexers and an inverter whose input is connected to the input bus, the first input of the fixing unit and the third input of the transfer unit, and the counting input of the counting decade of units and the first the input of the unit one, the second, third and fourth inputs of which are connected to the corresponding inputs of the fixing unit and the outputs of the respective multiplexers, the first input of the first of which is connected to the second output of the transfer unit inf the input input with the second output of the unit shift unit, the first inputs of the second and third multiplexers - with the second outputs of the counting decades of tens and hundreds, and the information inputs - with the control bus, while the output of the zeroing unit is connected to the inputs of the setting of zero counting decades of units, dec and the second outputs of the decade and tenths and hundredths of the division factor are connected to the inputs of the corresponding decoders and code inputs of the corresponding multiplexers, whose information inputs are connected to the first outputs with Shift blocks and outputs with the first inputs of the corresponding shift triggers, the second inputs of which are connected to the outputs of the corresponding decoders, while the shift trigger output of the tenth division factor is connected to the first input of the unit shift control unit whose output is connected to the first input of the shift unit units, the second input of the unit for controlling the shift of units is connected to the first input of the unit for controlling the shift of the tenth shares of the division factor and the output of the shift trigger hundredths of the factor The third input is with the second output of the shift unit of the tenth shares of the division factor, the first input of which is connected to the output of the shift control unit of the tenth shares of the division factor, the second input of which is connected to the second output of the shift unit hundredths of the division factor, and the second inputs of the shift blocks units, tenths and hundredths of the division factor are connected to the control buses. The drawing shows a structural electrical circuit of the pulse frequency divider. It contains counting decades of 1–5 units of tens, hundreds, tenths and hundredths of the division factor, multiplexers 6–10, blocks 11–13 units of shift, tenths, and co. dividing factors, fixing unit 14, zeroing unit 15, transfer unit 16, tenth and hundredth shift triggers 17 and 18, dividing ratio shift units, tenth and dividing unit blocks 19 and 20, inverter 21, decoders 22 and 23 zero counting decades, bus 24 input, bus 25 output, bus 26 output counting decade hundredths of the division factor, bus 27 control of hundredths, output bus 28 trigger thousandths of the division factor, control bus 29-33. Consider the operation of the device on the example of the implementation of the coefficient with two fractional bits where KO, K ,, KJ. - the whole part, the tenth, one hundredth of the division factor, respectively. To get Ktp, you need the coefficient () to get Ki RZZ, and the coefficient (Ko + -.-) - (lOO-Ki) times, i.e. in one hundred cycles of counting, the coefficient must be changed from Ko + -y to (change the program of the tenths from 1C (to KI -f 1). With an integer division factor of one division factor of the counting decade 1 does not occur. The divisor in In this case, as follows: In the initial state, a low level of the input signal FO is present on the splitter bus 24. All counting decades of the divider are in the zero state (0000). High-level signals are sent to the buses 31-33, respectively webs and hundreds of division factors divider. Low level signals are sent to buses 29 and 30, which prohibit the installation of hundredths and tenths, respectively, of the divider division factor. Low level is set on pin 25. Pulse sequence FO (high input signal) with a follow-up period That continuously flows from bus 24 to the first input of the block 14 and through the inverter 21 to the counting input of the counting decade 1 and the first input of the block 15. All counting decades 1-5 work in the code 8-4-2-1. The outputs of each counting decade are connected to the coding inputs (code input) of the corresponding multiplexer, with the exception of the outputs, the counting decade of units, in which the outputs with a binary weight of 2 ° and 2 are directly connected to the coding inputs of the multiplexer units of the division factor, and the outputs of the counting decade of units with a binary weight 2 and 2 are connected via block 16 to the coding inputs of the multiplexer units, respectively. Signal A on bus 25 appears with a high level at times determined by the following general logical equation:.) Where is the type of multiplexer output of units, ten, and more. .d division ratio; output signal j-ro multiplexer; -number multiplexer divider. To implement division with a fractional division factor, a divider is counted (divisible by ten) and a shift by one division factor set at the information input of multiplexer 6. The counting cycles are counting decades 4 and 5. The shift K {per unit carried out The block 11 Zero Decoders output the output when the counting decade state is 0000, multiplexers 9 and 10, at the states at the coding inputs corresponding to the information inputs n and HL. In the general case, the divisor contains j (j 0, -1, ..., -), the shift groups of the interconnected devices 4, 9, 12, 17, 20, and 22, and the number of shift groups is equal to the number of digits of the decimal fraction. The shift control scheme in general terms is described by the generalized logical equation j-4j-iv T.-axgЦ - r -i J S; - output of the shift control unit of the j-th shift group; Тг - 1-output signal of the shift trigger (J - 1) of the shift group; Tii-z.-shift trigger output (J-2) of the shift group; x - set 9 input (j-1) of the shift group; 3 (, - 1 ,, ..- ео) -number of the shift group; h O-group shift units of the division factor; J-i-shift group tenths of the division factor, etc. The shift control circuit controls the corresponding shift block, the output of which is described by a logic equation; / -. . . ,,. sj, -inputs i and (i + 1) setting the j-oro shift unit per unit fractional fraction of the division factor; j 0, -l, ...- “e by the special feature of multiplexers 7, 8, etc. is that their information inputs are direct inputs of installations of tens, hundreds, etc. division ratio. Upon receipt of division factors with fractions, when the number of units is 9 (there is a high signal level for Xd), unit 11, under the influence of the signal of the corresponding unit 19, sends a control signal to the information input n ° c of multiplexer b, which causes the divider to fake mode, because the counting decade has the largest binary code 1001. To avoid errors in this situation (when the number of units is set to 9 and it is necessary to get a fraction to increase the coefficient by one in certain counting cycles, i.e. Obtain 10), block 16 is entered which delays by one period sequencers That filling counting decades 6 and generates 2 dviochny vector 1010 corresponding to data input from the multiplexer nj code input. Consequently, during the operation of the divider, the control signal n to the information inputs of the multiplexer 6 is fed to a high level to one of the 11 inputs, i.e. 1 0, ..., 10, and the information inputs of the remaining multiplexers are supplied with their own control signal with a high level to one of the 10 inputs, i.e. i 0, ..., 9. In general, the division factor of the proposed divider is determined from an arithmetic expression. X..1x1.0 The latter formula is valid for all KöckY values and characterizes the range of variation of the divider division factor. The invention Pulse Frequency Divider with a fractional division factor containing counting decades of units, tens, hundreds, tenths and hundredths of the division coefficient, units of units shift, tenths and hundredths of the division factor, the transfer unit, the first input of which is connected to the output the counting decade of units, the second input with the first output of the unit shift unit, and the first output with the counting input of the counting decade of tens, the first input of which is connected to the counting input of the counting decade of hundreds, and the fixation unit, the output of which Connected to the counting input of the counting decade are the tenth shares of the division factor, the first output of which is connected to the counting input of the counting decade, hundredths of the division factor, characterized in that, in order to extend the functionality while simplifying, it introduced nulling block, decoders, shift triggers tenths and hundredths of a division factor, units of control of units and tenths of a division factor, mutiliplexors and an inverter whose input is connected to the input panel, the first input of the unit f The output and the third input of the transfer unit, and the output to the counting input are countable decades of units and the first input of the zeroing unit, the second, third and fourth inputs of which are connected to the corresponding inputs of the fixing unit n outputs of the corresponding multiplexers, the first input of the first of which is connected to the second output of the unit transfer, information input - with the second output of the unit shift unit, the first inputs of the second and third multiplexers with the second outputs of the counting decades of tens and hundreds, and information inputs with the control bus n At the same time, the output of the zeroing unit is connected to the installation inputs of zero counting units, tens and hundreds, and the second outputs of the decades of the tenth and hundredths of the division factor are connected to the inputs of the corresponding decipherors and code inputs of the corresponding multiplexers, the information inputs of which are connected to the first outputs the corresponding shift blocks, and the outputs with the first inputs of the corresponding shift triggers, the second inputs of which are connected to the outputs of the corresponding decipherors, while the output of the shift trigger is ten ten x shares of the ratio divided to the first input of the unit of control of the shift of units, the output of which is connected to the first input of the unit of shift of units, the second input of the unit of control of the shift of units is connected to the first input of the unit of control of shift of the tenth shares of the division factor , the third input is with the second output of the shift unit of the tenth shares of the division factor, the first input of which is connected to the output of the shift control unit of the tenth shares of the division factor, the second input of which connected to the second output of the shift second decimal dividing ratio, and the second inputs of the shift block units, tenths and hundredths of a division ratio connected to the control shnnami. Sources of information taken into account in the examination 1. USSR author's certificate number 506130, cl. H 03 K 23/00, 01/17/74. 2. USSR author's certificate number 436446, cl. H 03 K 25/00, 05.10.71.