SU1307378A1 - Digital average phase-meter - Google Patents

Abstract

The invention relates to the field of information and measurement technology. It can be used in both analog and digital instruments for measuring phase shift. The purpose of the invention is to improve the accuracy of phase shift measurement. To achieve this goal, the logic block 1, the source 7 of the reference voltage, the integrators 10, 11, the latch 12 level, the voltage converter 13 in the time interval, the keys 14, 15 are entered into the device. The device also contains the formers 2.3, the generator 4, match element 5, counter 6, trigger 16, keys 8.9. The description of the invention provides examples of the implementation of logic block 1 and control block. The device provides the integrators 10, 11 and converter 13 that are synchronous with the input frequency, which eliminates a number of errors. 3 il. (O (L W V i I 0U9.f

Description

The invention relates to an information-measuring technique and can be used both in analog and digital digital devices for measuring phase shift.

The purpose of the invention is to improve the accuracy of phase shift measurement.

Fig. 1 shows a block diagram of a digital phase meter of an average value in Fig. 2 — time diagrams of its operation.

The digital average phase meter (Fig. 1) contains logic unit 1, drivers 2 and 3, generator 4, coincidence element 5, counter 6, reference voltage source 7, keys 8 and 9, integrators 10 and 11, latch 12, converter 13 voltages per time interval, keys 14 and 15, and tigger 16,

The inputs of the driver 2 and 3 are the inputs of the phase meter. The output of the driver 3 is connected to the first input of the trigger .16 and through the logic unit with the control input of the switch 9. The output of the driver 2 is connected to the second input of the trigger 16, the output of which is connected to the control input of the switch 8. The output of the source 7 of the sample voltage through the switches 8 and 9 is connected to the first inputs of the respective integrators 10 and 11, the outputs of which are connected to the first and second inputs of the latch 12 level.

The output of the latch 12 is connected to the input of the voltage converter 13 in the time interval and through the keys 14 and 15 to the second inputs of the integrators 10 and 11, respectively. The output of the voltage converter 13 in the time interval is connected to one of the inputs of the matching element 5 and to the key 14 input. The second input of the matching element is connected to the output of the generator 4. The outputs of unit 1 are connected to the first and second control inputs of the latch 12, to the control the inputs of the Converter 13 and the key 15.

The digital average phase meter operates as follows (Fig. 2).

The frequency divider 17 generates a sinal and with a period h in n times larger than the period of the input signal. Integrator 11 during the time interval

integrates voltage U

razheni:

source 7 is the reference voltage, and for the time interval + hg is the output voltage of the latch 12 level. At time h, the latch 12 of the level carries out memorization of the output voltage of the integrator 11.

The signal controlling the latch 12 of the level and the keys 9 and 8 connecting the inputs of the integrator 11 to the outputs of the source 7 of the reference voltage is generated by the logic unit 1 under the action of the output signal of the driver 3.

For the output voltage of the integrator 11 at times

h. 3,

J, n, -n the following are valid:

and

,( )about.

d .dPCHJ d

i

i

d (| h) - Uj (h) - || u; (h) d t,

where h

llo

conversion cycle, equal to the periods T of the input signal

the integration constant over the inputs of the integrator 11. When writing expressions for wil (c)

The fact is used that the latch 12 at the moment of time h remembers the output voltage; e of the integrator 11 and its storage until the moment of time h h, i.e.

and

, (t) /

. | ь

and H)

five

Substituted for U

 hf 2

(t) to

 transform the view:

and

(h) 2 and

3 ° I (| h) 0.

and.

Further, the operation process of the integrator 11 is periodically repeated.

The integrator 10 during the time interval About t b h integrates the voltage at the output of the key 8 connecting the voltage U of the source 7

the reference voltage of torus 10 for

to the input of the integral intervals vre 31307378

the values of t determined by the phase shift if between the input voltages Uj. . The formation of time intervals t is carried out by the formers 2 and 3 together with the trigger 16.

During the time interval

-sr.

defined by the converter 13, the integrator 10, along with the voltage U ,, integrates the output voltage Ug of the latch 12 of the level input to the input of the integrator 10 via the key 14, controlled by the output signal of the voltage converter 13 in the time interval.

For the output voltage of the integrator 10 at times 0;

- h- - h 2 2

and

the expressions are 0-b

CtO) tx

Oef and, (0) | I and d t j

i,

u, (h) u, (s and u d t

(h). | l J U, d t-ljUjdiV 3

about /

voltage in in s also in ra 12, with during

x

il2b) il | h) +

S M and 2 J

where h is a constant of the integration time across the inputs of the integrator 10. Execute the integration operation

and considering equality

tx

Ij.

d t

i.cp

 -U

d t

o0

we obtain the expressions for) in the form:

t.

U (h / 2) and od t;

ABOUT

t "

U (h) n I j tt

tx

U, (| h) I 1 J

t

i

Uc (2h) n 1J t.

Solving together a system of equations

one

:

ABOUT

 t

four

VP

Uj f,

h n T,

W

determine the output voltage for the output time interval t of the converter 13:

. 27

a- J5

The formation of the time interval t (vp is carried out by the converter 13,

diV 3

which can be built, for example, as shown in FIG. 3, by the push-pull scheme. In the time interval t (.p, the output voltage of latch 12, which is present at its output during the time interval

i - t: h. As a reference

voltage converter voltage 13 in the time interval is also used output voltage latch 12, which is present at its input during the time interval

25

The combination of generator 4, coincidence element 5, and counter 6 is a converter in the 35fi code of the time interval t ,,.

Compared with converter 13.

In this case, the output code is determined by the expression

N

fo he

2-

. .

Synchronous with the input frequency, the work of the integrators and the voltage converter in the time interval allows us to eliminate the errors inherent in the prototype.

An example of the implementation of the logic unit 1 and the control unit of the device included in the converter 13 is shown in FIG. Za and Sv.

The logical block (fig.Za) consists of a quartz oscillator, three two-input elements AND, two triggers with separate inputs, a pulse counter, an OR-NOT element and two drivers, each of which contains three OR-NOT elements and a two-input element AND.

513

The control unit (fig.Zv) contains a trigger with separate inputs, two AND two-phase elements, an ORID element and two identical shapers.

The input signal of block 1 is fed to the shaper of short pulses, and the output signal of the shaper a is the output of the i block.

Output voltage U; presented in figure 2. Similarly, in the course of the driver b, the output h of the logic unit 1 receives a signal and (figure 2). U signals; and U, set the trigger of the logic block alternately to the zero and one states. By filling the counter of unit 1 with pulses of a quartz oscillator, signal 1 is formed, which is a sequence of pulses

duration - ° (figure 2). Comparative

NIN signals 1, as well as the signal from the course of the lower trigger of logic unit 1 (Fig. 3a), a signal K is generated.

In the control unit, the trigger is set by the output signal of the driver C to one and the output signal of the driver of d is set to the zero state. In this case, its direct output is output X of the control unit. An output driver assembled on two AND elements produces a X signal.

Claims (1)

The operation of the control unit is illustrated by the state diagram shown in Fig. 3c. Invention Formula An average digital phase meter containing two drivers. five ABOUT five 0 five the trigger, the first and second keys, the generator, the frequency divider and the counter, the driver inputs are the device inputs and their outputs are connected to the trigger inputs whose output is connected to the control input of the first key, the generator output is connected to the counter input through the second key , characterized in that, in order to improve the accuracy of phase shift measurement, a logic block, a source of exemplary voltage, - two integrators, a level clamp, a voltage converter in the time interval, a third, the first and third keys are connected to the first inputs of the first and second integrators, the outputs of which are connected to the first and second inputs of the level lock, the output of which is connected to the input of the voltage converter in a time interval and through the fourth and fifth keys - with the second inputs of the first and second integrators, the first output of the voltage converter in the time interval is connected to the control inputs of the second and fourth keys, the output of the second driver Connected to the input of the logic unit and the input of a frequency divider, the output of which is connected to the control input of the third The 5 keys, the first, second, third and fourth outputs of the logic unit are connected to the first and second control inputs of the latch and to the control inputs of the fifth key and 0 voltage to time converter. t -t t ipu. 2 To shunt e OK f} ff) -T-t. Fi9. 3